KR840007337A - 디지탈 신호 합성회로 - Google Patents

디지탈 신호 합성회로 Download PDF

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Publication number
KR840007337A
KR840007337A KR1019830006219A KR830006219A KR840007337A KR 840007337 A KR840007337 A KR 840007337A KR 1019830006219 A KR1019830006219 A KR 1019830006219A KR 830006219 A KR830006219 A KR 830006219A KR 840007337 A KR840007337 A KR 840007337A
Authority
KR
South Korea
Prior art keywords
synthesis circuit
digital signal
signal synthesis
selection means
selecting
Prior art date
Application number
KR1019830006219A
Other languages
English (en)
Other versions
KR910008740B1 (ko
Inventor
다께히로(외 4) 스기다
Original Assignee
오오가 노리오
소니 가부시끼 가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 오오가 노리오, 소니 가부시끼 가이샤 filed Critical 오오가 노리오
Publication of KR840007337A publication Critical patent/KR840007337A/ko
Application granted granted Critical
Publication of KR910008740B1 publication Critical patent/KR910008740B1/ko

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10527—Audio or video recording; Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B27/00—Editing; Indexing; Addressing; Timing or synchronising; Monitoring; Measuring tape travel
    • G11B27/02—Editing, e.g. varying the order of information signals recorded on, or reproduced from, record carriers
    • G11B27/031—Electronic editing of digitised analogue information signals, e.g. audio or video signals
    • G11B27/038—Cross-faders therefor
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04K—SECRET COMMUNICATION; JAMMING OF COMMUNICATION
    • H04K1/00—Secret communication
    • H04K1/06—Secret communication by transmitting the information or elements thereof at unnatural speeds or in jumbled order or backwards

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Control Of Amplification And Gain Control (AREA)
  • Complex Calculations (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Analogue/Digital Conversion (AREA)
  • Electronic Switches (AREA)

Abstract

내용 없음

Description

디지털 신호 합성회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 크로스페이드의 설명에 제공하기 위한 선도.
제2도는 본 발명의 한 실시예를 도시하는 계통도.
제3도는 제2도의 동작설명에 제공하기 위한 신호파형도.

Claims (5)

  1. 복수개의 디지탈 데이타를 선택하는 제1의 선택수단과, 상기 디지털 데이타의 한쪽과 궤환신호를 선택하는 제2의 선택수단과, 상기 제1 및 제2의 선택수단의 절환을 제어하는 제어수단과, 상기 제1 및 제2의 선택수단의 출력을 가산함과 동시에 그 가산출력을 상기 궤환 신호로서 상기 제2의 선택 수단에 공급하는 가산 수단을 구비하고 그 가산수단으로부터 최종출력을 얻도록 한 것을 특징으로 하는 디지탈 신호 합성회로.
  2. 제1항에 의한 디지탈 신호합성회로에 있어서, 2개의 디지탈 입력신호 X, Y의 연산이
  3. Z＝·X＋(1－Y) (k : 일정치 n : 임의의 정수)
  4. 형태로 표시되도록 한 것을 특징으로 하는 디지털 신호합성회로.
  5. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019830006219A 1982-12-27 1983-12-27 디지탈 신호 처리 회로 KR910008740B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP57230601A JPS59122040A (ja) 1982-12-27 1982-12-27 デイジタル信号処理回路
JP57-230601(??) 1982-12-27
JP230601 1982-12-27

Publications (2)

Publication Number Publication Date
KR840007337A true KR840007337A (ko) 1984-12-06
KR910008740B1 KR910008740B1 (ko) 1991-10-19

Family

ID=16910295

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019830006219A KR910008740B1 (ko) 1982-12-27 1983-12-27 디지탈 신호 처리 회로

Country Status (6)

Country Link
US (1) US4612627A (ko)
EP (1) EP0117357A3 (ko)
JP (1) JPS59122040A (ko)
KR (1) KR910008740B1 (ko)
AU (1) AU570226B2 (ko)
CA (1) CA1253617A (ko)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5041998A (en) * 1989-11-30 1991-08-20 The Grass Valley Group Inc. Digital video mixer
US20040207628A1 (en) * 1997-12-30 2004-10-21 Hoddie J. Peter Method and apparatus for chaining two or more tweens to provide non-linear multimedia effects
JP3726574B2 (ja) * 1999-08-05 2005-12-14 ヤマハ株式会社 Ｄ／ａ変換装置
KR200363966Y1 (ko) 2004-07-02 2004-10-07 서진미 파이프 확관장치

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3564226A (en) * 1966-12-27 1971-02-16 Digital Equipment Parallel binary processing system having minimal operational delay
US3564227A (en) * 1967-12-14 1971-02-16 Potter Instrument Co Inc Computer and accumulator therefor incorporating push down register
GB1363073A (en) * 1970-07-17 1974-08-14 Solartron Electronic Group Generation of trigonometrical and other functions by interpolation between point values
US3789204A (en) * 1972-06-06 1974-01-29 Honeywell Inf Systems Self-checking digital storage system
GB1480503A (en) * 1973-09-13 1977-07-20 Siemens Ag Calculating unit for serial multiplication
US3919535A (en) * 1974-08-21 1975-11-11 Singer Co Multiple addend adder and multiplier
JPS5542384A (en) * 1978-09-21 1980-03-25 Mitsubishi Electric Corp Pcm sound reproducer
JPS5633703A (en) * 1979-08-25 1981-04-04 Fanuc Ltd Signal converting circuit
GB2059203B (en) * 1979-09-18 1984-02-29 Victor Company Of Japan Digital gain control
EP0042452B1 (en) * 1980-06-24 1984-03-14 International Business Machines Corporation Signal processor computing arrangement and method of operating said arrangement
US4467444A (en) * 1980-08-01 1984-08-21 Advanced Micro Devices, Inc. Processor unit for microcomputer systems
NL8100307A (nl) * 1981-01-23 1982-08-16 Philips Nv Werkwijze voor het verzwakken van een digitaal signaal en een inrichting voor het uitvoeren van deze werkwijze.
US4455611A (en) * 1981-05-11 1984-06-19 Rca Corporation Multiplier for multiplying n-bit number by quotient of an integer divided by an integer power of two
SE8202741L (sv) * 1981-05-11 1982-11-12 Rca Corp Kompatibelt, transkodningsbart och hierarkaliskt digitaltelevisionssystem

Also Published As

Publication number Publication date
EP0117357A2 (en) 1984-09-05
JPS59122040A (ja) 1984-07-14
AU570226B2 (en) 1988-03-10
EP0117357A3 (en) 1987-07-15
CA1253617A (en) 1989-05-02
KR910008740B1 (ko) 1991-10-19
JPH0374543B2 (ko) 1991-11-27
US4612627A (en) 1986-09-16
AU2225883A (en) 1984-07-05

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Year of fee payment: 12

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