KR910001383B1 - 논리회로 - Google Patents

논리회로 Download PDF

Info

Publication number
KR910001383B1
KR910001383B1 KR1019880003320A KR880003320A KR910001383B1 KR 910001383 B1 KR910001383 B1 KR 910001383B1 KR 1019880003320 A KR1019880003320 A KR 1019880003320A KR 880003320 A KR880003320 A KR 880003320A KR 910001383 B1 KR910001383 B1 KR 910001383B1
Authority
KR
South Korea
Prior art keywords
circuit
potential
output
input
logic circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
KR1019880003320A
Other languages
English (en)
Korean (ko)
Other versions
KR880012011A (ko
Inventor
마사지 우에노
Original Assignee
가부시키가이샤 도시바
아오이 죠이치
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시키가이샤 도시바, 아오이 죠이치 filed Critical 가부시키가이샤 도시바
Publication of KR880012011A publication Critical patent/KR880012011A/ko
Application granted granted Critical
Publication of KR910001383B1 publication Critical patent/KR910001383B1/ko
Expired legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09448—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/013—Modifications for accelerating switching in bipolar transistor circuits
    • H03K19/0136—Modifications for accelerating switching in bipolar transistor circuits by means of a pull-up or down element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/088—Transistor-transistor logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
KR1019880003320A 1987-03-27 1988-03-26 논리회로 Expired KR910001383B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP62071874A JPS63240128A (ja) 1987-03-27 1987-03-27 論理回路
JP62-71874 1987-03-27

Publications (2)

Publication Number Publication Date
KR880012011A KR880012011A (ko) 1988-10-31
KR910001383B1 true KR910001383B1 (ko) 1991-03-04

Family

ID=13473097

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880003320A Expired KR910001383B1 (ko) 1987-03-27 1988-03-26 논리회로

Country Status (4)

Country Link
US (1) US4877975A (cg-RX-API-DMAC10.html)
EP (1) EP0285068A3 (cg-RX-API-DMAC10.html)
JP (1) JPS63240128A (cg-RX-API-DMAC10.html)
KR (1) KR910001383B1 (cg-RX-API-DMAC10.html)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2635805B2 (ja) * 1990-07-31 1997-07-30 株式会社東芝 低ノイズ型出力バッファ回路
US5218243A (en) * 1991-11-20 1993-06-08 National Semiconductor Corporation Bicmos ttl output buffer circuit with reduced power dissipation
JP3142018B2 (ja) * 1992-03-12 2001-03-07 日本テキサス・インスツルメンツ株式会社 負荷駆動回路
US5343092A (en) * 1992-04-27 1994-08-30 International Business Machines Corporation Self-biased feedback-controlled active pull-down signal switching
JP3338783B2 (ja) * 1998-09-24 2002-10-28 エヌイーシーアクセステクニカ株式会社 トランジスタ回路
US9018986B2 (en) * 2013-01-21 2015-04-28 Via Technologies, Inc. Output buffers

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5720027A (en) * 1980-06-25 1982-02-02 Nec Corp Logical gate circuit
US4409498A (en) * 1980-12-30 1983-10-11 International Business Machines Corporation Transient controlled current switch
US4605870A (en) * 1983-03-25 1986-08-12 Ibm Corporation High speed low power current controlled gate circuit
US4567378A (en) * 1984-06-13 1986-01-28 International Business Machines Corporation Driver circuit for controlling signal rise and fall in field effect transistor processors
US4737665A (en) * 1985-01-15 1988-04-12 Texas Instruments Incorporated Adjustable speed up circuit for TTL-type gates
JPH0720060B2 (ja) * 1985-08-14 1995-03-06 株式会社東芝 出力回路装置
US4622482A (en) * 1985-08-30 1986-11-11 Motorola, Inc. Slew rate limited driver circuit which minimizes crossover distortion
US4746817A (en) * 1987-03-16 1988-05-24 International Business Machines Corporation BIFET logic circuit

Also Published As

Publication number Publication date
JPS63240128A (ja) 1988-10-05
US4877975A (en) 1989-10-31
EP0285068A2 (en) 1988-10-05
JPH0519328B2 (cg-RX-API-DMAC10.html) 1993-03-16
KR880012011A (ko) 1988-10-31
EP0285068A3 (en) 1990-06-13

Similar Documents

Publication Publication Date Title
US4845386A (en) Bi-MOS logic circuit having a totem pole type output buffer section
EP0231667A2 (en) Output buffer circuits
US4804868A (en) BiMOS logical circuit
EP0173288A2 (en) Voltage level converting circuit
US4839537A (en) BicMO logic circuit
KR960012719A (ko) 전압 클램프 회로와 클램프 해제 회로를 갖는 BiCMOS 푸쉬-풀 형 논리 장치
JPH0583004B2 (cg-RX-API-DMAC10.html)
KR930001439B1 (ko) BiCMOS용 출력회로
US4612458A (en) Merged PMOS/bipolar logic circuits
US5166551A (en) High speed output circuit without fluctuation for semiconductor integrated circuits
JPH0629824A (ja) 論理信号切り換え回路
US5198704A (en) Bi-CMOS output circuit with limited output voltage
JPH0732362B2 (ja) Ｔｔｌ型ゲート用可変スピードアツプ回路
US4877975A (en) Logic circuit having an output signal with a gentle leading edge
JPH0633715Y2 (ja) トランジスタ−トランジスタ論理回路
KR910005588B1 (ko) 논리회로
EP0069853A2 (en) A TTL logic gate
US5077490A (en) Schottky-diode emulator for BiCMOS logic circuit
US5107143A (en) Signal output circuit included in bus driving integrated circuit
US5066874A (en) Signal output circuit having bipolar transistor in output stage and arranged in cmos semiconductor integrated circuit
KR940005975B1 (ko) 출력회로
US5361004A (en) TTL-CMOS output stage for an integrated circuit
US5166544A (en) Pseudo Darlington driver acts as Darlington during output slew, but has only 1 VBE drop when fully turned on
JPH02280412A (ja) バイ・ｍｏｓ半導体集積回路
US5258661A (en) High noise tolerance receiver

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

G160 Decision to publish patent application
PG1605 Publication of application before grant of patent

St.27 status event code: A-2-2-Q10-Q13-nap-PG1605

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 10

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 11

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 12

FPAY Annual fee payment

Payment date: 20030228

Year of fee payment: 13

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 13

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20040305

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20040305

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000