KR900019138A - MOS transistor manufacturing method and structure - Google Patents

MOS transistor manufacturing method and structure Download PDF

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Publication number
KR900019138A
KR900019138A KR1019890007370A KR890007370A KR900019138A KR 900019138 A KR900019138 A KR 900019138A KR 1019890007370 A KR1019890007370 A KR 1019890007370A KR 890007370 A KR890007370 A KR 890007370A KR 900019138 A KR900019138 A KR 900019138A
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KR
South Korea
Prior art keywords
type
regions
active regions
type active
mos transistor
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KR1019890007370A
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Korean (ko)
Inventor
구정석
강대관
박영준
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이만용
금성반도체 주식회사
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Priority to KR1019890007370A priority Critical patent/KR900019138A/en
Publication of KR900019138A publication Critical patent/KR900019138A/en

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Abstract

내용 없음No content

Description

모스 트랜지스터 제조 방법 및 구조MOS transistor manufacturing method and structure

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 본 발명에 따른 모스 트랜지스터의 구조도, 제5도는 본 발명에 따른 모스 트랜지스터 제조 공정도.4 is a structural diagram of a MOS transistor according to the present invention, Figure 5 is a manufacturing process diagram of the MOS transistor according to the present invention.

Claims (2)

P형 실리콘 기판(7) 상에 액티브 마스크를 사용하여 필드 트랜치를 실시하는 공정과, 상기 공정후n+주입을 하여 배리드 가드링(9d, 9e)을 만드는 공정과, 상기 공정후 다시 웰 주입을 한후 드라이브인 하여 n+형액티브영역(9d)(9e)과 n형 웰(8)을 형성하는 공정과, 상기 공정후 트랜치를 산화물로 채우는 공정과, 상기 공정후 p+형 액티브 영역(10a~10c)과 n+형 액티브 영역(9a~9c) 및 게이트(12a~12b)를 형성하는 공정을 포함하여 구성된 것을 특징으로 하는 모스 트랜지스터 제조 방법.A field trench is formed on the P-type silicon substrate 7 using an active mask, n + implantation is performed to form the buried guard rings 9d and 9e after the step; And then driving in to form n + type active regions 9d and 9e and n type wells 8, filling the trenches with oxide after the step, and p + type active regions 10a to 10c after the step. And forming a n + type active region (9a to 9c) and a gate (12a to 12b). P형 실리콘 기관(7)상에 형성된 n형 웰(8)과, 필드 산화물 트랜치 격리 영역(11a, 11b)(11c)과, 상기 필드 산화물 트랜치 격리 영역(11a, 11b)아래에 형성된 n+형 액티브 영역(9d, 9e)과, N형 웰(8)과 P형 실리콘 기판(7)상에 형성된 n+형 액티브 영역(9a)(9b, 9c)과, N형 웰(8)과 P형 실리콘 기판(7) 상에 형성된 p+형 액티브 영역(10a, 10b)(10c)과, 상기 p+형 액티브 영역(10a, 10b) 사이의 n+형 액티브 영역(9b, 9c) 사이에 형성된게이트 (12a)(12b)로 구성된 것을 특징으로 하는 모스 트랜지스터 구조.N-type wells 8 formed on the P-type silicon engine 7, field oxide trench isolation regions 11a and 11b and 11c, and n + type actives formed below the field oxide trench isolation regions 11a and 11b. Regions 9d and 9e, n + type active regions 9a (9b and 9c) formed on N type well 8 and P type silicon substrate 7, N type well 8 and P type silicon substrate Gates 12a and 12b formed between p + type active regions 10a and 10b and 10c formed on (7) and n + type active regions 9b and 9c between the p + type active regions 10a and 10b. MOS transistor structure characterized in that consisting of. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890007370A 1989-05-31 1989-05-31 MOS transistor manufacturing method and structure KR900019138A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890007370A KR900019138A (en) 1989-05-31 1989-05-31 MOS transistor manufacturing method and structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890007370A KR900019138A (en) 1989-05-31 1989-05-31 MOS transistor manufacturing method and structure

Publications (1)

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KR900019138A true KR900019138A (en) 1990-12-24

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KR1019890007370A KR900019138A (en) 1989-05-31 1989-05-31 MOS transistor manufacturing method and structure

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KR (1) KR900019138A (en)

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