KR940003023A - Method for manufacturing mask ROM using lower layer tunnel - Google Patents

Method for manufacturing mask ROM using lower layer tunnel Download PDF

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Publication number
KR940003023A
KR940003023A KR1019920012091A KR920012091A KR940003023A KR 940003023 A KR940003023 A KR 940003023A KR 1019920012091 A KR1019920012091 A KR 1019920012091A KR 920012091 A KR920012091 A KR 920012091A KR 940003023 A KR940003023 A KR 940003023A
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KR
South Korea
Prior art keywords
tunnel
layer
mask rom
lower tunnel
semiconductor substrate
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KR1019920012091A
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Korean (ko)
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KR960002776B1 (en
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민병운
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김주용
현대전자산업주식회사
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Priority to KR1019920012091A priority Critical patent/KR960002776B1/en
Publication of KR940003023A publication Critical patent/KR940003023A/en
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Publication of KR960002776B1 publication Critical patent/KR960002776B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices

Abstract

본 발명은 마스크 롬 제조방법에 관한 것으로, 반도체 기판(9)에 상기 반도체 기판(9)과 다른 형(type)의 하층터널층(15)을 성장시키는 제1단계, 상기 제1단계 후에 상기 하층터널(15)과 반대형의 웰(well)(17)을 상기 하층터널(15)상에 에피탁셜(epitaxial) 성장시키는 제2단계, 상기 제2단계 후에 게이트 산화막(11), 폴리실리콘을 차례로 증착하여 예정된 크기로 마스크 패턴한 후에 상기 폴리실리콘과 상기 게이트 산화막(11)을 차례로 선택식각하여 게이트 전극(19, 20, 21, 22)을 형성하고 상기 웰(17)과 반대형의 불순물 이온을 주입하여 고농도 활성영역(7')을 형성하는 제3단계, 및 상기 제3단계 후에 공핍형 트랜지스터로 형성할 트랜지스터(21)의 활성영역에 상기 하층터널(15)의 불순물 이온과 같은 형태의 불순물 이온을 상기 하층터널(15) 깊이까지 주입하는 제4단계를 구비하는 것을 특징으로 하는 하층 터널을 이용한 마스크 롬의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a mask ROM, the first step of growing a lower tunnel layer (15) of a different type from the semiconductor substrate (9) on the semiconductor substrate (9), and after the first step, the lower layer. A second step of epitaxially growing a well 17 of the opposite type to the tunnel 15 on the lower tunnel 15, followed by the gate oxide film 11 and the polysilicon after the second step. After depositing and masking the pattern to a predetermined size, the polysilicon and the gate oxide layer 11 are sequentially etched to form gate electrodes 19, 20, 21, and 22, and impurity ions opposite to the well 17 are formed. An impurity having the same shape as impurity ions of the lower tunnel 15 in the active region of the transistor 21 to be formed as a depletion transistor after the third step of implanting and forming a high concentration active region 7 ′. A fourth step of implanting ions to the depth of the lower tunnel 15 It is related with the manufacturing method of the mask rom using the lower layer tunnel characterized by the above-mentioned.

Description

하층 터널을 이용한 마스크 롬의 제조방법Method for manufacturing mask ROM using lower layer tunnel

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 일실시예의 마스크 롬 구조도.2 is a mask ROM structure diagram of an embodiment according to the present invention.

Claims (3)

하층 터널을 이용한 마스크 롬의 제조 방법에 있어서, 반도체 기판(9)에 상기 반도체 기판(9)과 다른 형(type)의 하층 터널층(15)을 성장시키는 제1단계, 상기 제1단계 후에 상기 하층 터널(15)과 반대형의 웰(well)(17)을 상기 하층 터널(15)상에 에피탁셜(epitaxial)성장시키는 제2단계, 상기 제2단계 후에 게이트 산화막(11), 폴리실리콘을 차례로 증착하여 예정된 크기로 마스크 패턴한 후에 상기 폴리실리콘과 상기 게이트 산화막(11)을 차례로 선택 식각하여 게이트 전극(19,20,21,22)을 형성하고 상기 웰(17)과 반대형의 불순물 이온을 주입하여 고농도 활성영역(7')을 형성하는 제3단계 및 상기 제3단계 후에 공핍형 트랜지스터로 형성할 트랜지스터(21)의 활성영역에 상기 하층 터널(15)의 불순물 이온과 같은형의 불순물 이온을 상기 하층 터널(15) 깊이까지 주입하여 플러그 고농도 활성영역(7'')을 형성하는 제4단계를 구비하는 것을 특징으로 하는 하층 터널을 이용한 마스크 롬의 제조 방법.In the method of manufacturing a mask ROM using a lower tunnel, a first step of growing a lower tunnel layer 15 of a different type from the semiconductor substrate 9 on the semiconductor substrate 9, and after the first step, A second step of epitaxially growing a well 17 opposite to the lower tunnel 15, and after the second step, the gate oxide 11 and the polysilicon After depositing a mask pattern to a predetermined size, the polysilicon and the gate oxide layer 11 are sequentially etched to form gate electrodes 19, 20, 21, and 22, and impurity ions opposite to the well 17. Impurity of the same type as impurity ions in the lower tunnel 15 in the active region of the transistor 21 to be formed as a depletion transistor after the third step and the third step of forming the high concentration active region 7 ' Inject ions to the depth of the lower tunnel 15 to And a fourth step of forming the high concentration active region (7 ''). 제1항에 있어서, 상기 제1단계인 반도체 기판(1), 제2단계의 웰(17)은 각각 p형이고, 상기 제1단계의 하층 터널층(15), 제4단계의 플러그 활성영역(7'')은 각각 n형인 것을 특징으로 하는 하층 터널을 이용한 마스크 롬의 제조 방법.The semiconductor substrate 1 of the first step and the wells 17 of the second step are p-type, respectively, and the lower layer tunnel layer 15 of the first step and the plug active region of the fourth step of the first step. (7 '') is a n-type mask rom manufacturing method using a lower tunnel, characterized in that each. 제1항에 있어서, 상기 제1단계의 반도체 기판(1), 제2단계의 웰(17)은 각각 n형이고, 상기 제1단계의 하층 터널층(15), 제4단계의 플러그 고농도 활성영역(7'')은 각각 p형인 것을 특징으로 하는 하층 터널을 이용한 마스크 롬의 제조 방법.The semiconductor substrate 1 of the first step and the wells 17 of the second step are respectively n-type, and the lower tunnel layer 15 of the first step and the plug high concentration activity of the fourth step of the first step. A method of manufacturing a mask rom using an underlayer tunnel, in which the regions 7 '' are each p-type. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920012091A 1992-07-07 1992-07-07 Mask rom manufacturing method KR960002776B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920012091A KR960002776B1 (en) 1992-07-07 1992-07-07 Mask rom manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920012091A KR960002776B1 (en) 1992-07-07 1992-07-07 Mask rom manufacturing method

Publications (2)

Publication Number Publication Date
KR940003023A true KR940003023A (en) 1994-02-19
KR960002776B1 KR960002776B1 (en) 1996-02-26

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Application Number Title Priority Date Filing Date
KR1019920012091A KR960002776B1 (en) 1992-07-07 1992-07-07 Mask rom manufacturing method

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