KR920007091A - Manufacturing Method of Semiconductor Device - Google Patents

Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR920007091A
KR920007091A KR1019900014908A KR900014908A KR920007091A KR 920007091 A KR920007091 A KR 920007091A KR 1019900014908 A KR1019900014908 A KR 1019900014908A KR 900014908 A KR900014908 A KR 900014908A KR 920007091 A KR920007091 A KR 920007091A
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South Korea
Prior art keywords
ion implantation
forming
well
region
source
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KR1019900014908A
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Korean (ko)
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KR930008853B1 (en
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고윤학
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation

Abstract

내용 없음.No content.

Description

반도체 장치의 제조방법Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제 1 도는 종래의 고압 및 저압 병용 시모스 트랜지스터의 제조공정도.1 is a manufacturing process diagram of a conventional high voltage and low voltage combination CMOS transistor.

제 2 도는 본 발명의 로코스를 이용한 고압 및 저압 병용 시모스 트랜지스터의 제조공정도.2 is a manufacturing process diagram of a high-pressure and low-voltage combined CMOS transistor using Locos of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

51 : P- 웰 52 : N-웰51: P-well 52: N-well

53, 58 : 산화막 54, 56 : 감광성 물질53, 58: oxide film 54, 56: photosensitive material

55, 57 : 이온주입영역 59 : 질화막55, 57: ion implantation region 59: nitride film

60 : 필드산화막 61 : P+형 필드이온주입영역60: field oxide layer 61: P + type field ion implantation region

62 : N- 형 소오스, 드레인 영역 63 : N+형 필드이온주입영역62: N-type source and drain region 63: N + type field ion implantation region

64 : P- 형 소오스, 드레인 영역 65 : 게이트 산화막64: P-type source, drain region 65: gate oxide film

66 : 게이트 풀리 67 : 측벽 스페이서66: gate pulley 67: sidewall spacer

68, 69 : N+형 소오스, 드레인 영역 70, 71 : P+형 소오드, 드레인 영역68, 69: N + type source and drain region 70, 71: P + type source and drain region

Claims (4)

고압 및 저압 병용 시모스 트랜지스터를 제조하는 방법에 있어서, 트윈 웰(Twin well) 형성공정으로 기판상에 P- 웰(51)과 N- 웰(52)을 각각 형성하는 공정과, P- 웰(51)내에 저농도의 N- 형 소오스, 드레인 영역과 N- 웰(52)내에 N+ 형 필드이온주입영역을 형성하기 위한 1차 이온주입공정과, P- 웰(51)내에 P+ 형 필드이온주입영역과 N-웰(52)내에 저농도의 P-소오스, 드레인 영역을 형성하기 위한 2차 이온주입공정과, 필드산화막(60)과 각 웰(51), (52)내에 고압용 모스 트랜지스터의 저농도 소오스, 드레인 영역(62), (64)과 필드이온주입영역(61), (63)을 형성하는 공정과, 게이트 산화막(65)을 각 모스 트랜지스터의 게이트 영역에 형성하고, 게이트 산화막(65)위에 게이트 폴리 패턴(66)을 정의하는 공정과, 게이트 폴리 패턴(66)의 측벽에 스페이서(67)를 형성하고, 이 스페이서(67)를 마스크로 하여 보론이온과 인이온을 각각 주입하고 침투시켜 고농도의 P+ 형과 N+ 형의 소오스, 드레인 영역(68-71)을 각각 형성하는 공정으로 이루어지는 것을 특징으로 하는 반도체 장치의 제조방법.A method for manufacturing a high-voltage and low-voltage CMOS transistor, comprising: forming a P-well 51 and an N-well 52 on a substrate by a twin well forming process, and a P-well 51 A primary ion implantation process for forming a low concentration N-type source, drain region and N + type field ion implantation region in the N-well 52, and a P + type field ion implantation region in the P-well 51 A secondary ion implantation process for forming a low concentration P-source and drain region in the N-well 52, a low concentration source of a high-voltage MOS transistor in the field oxide film 60 and each of the wells 51 and 52, Forming the drain regions 62, 64 and the field ion implantation regions 61, 63; and forming a gate oxide film 65 in the gate region of each MOS transistor, and forming a gate over the gate oxide film 65. The process of defining the poly pattern 66, the spacer 67 is formed in the side wall of the gate poly pattern 66, and this spacer 67 As a mask each of implanting boron ions and phosphorus ions to penetrate to method of manufacturing a semiconductor device which comprises the step of respectively forming the source and drain regions (68-71) of the high-concentration P + type and the N + type. 제 1 항에 있어서, 상기 1차 이온주입공정은 기판상에 산화막(53)을 성장시킨 다음 감광성 물질(54)을 도포하는 스텝과, 상기 감광성 물질(54)을 사진식각하여 P- 웰(51)내에 소오스, 드레인 영역과 N- 웰(52)내에 필드이온주입영역이 형성될 부위를 노출시키는 스텝과, 상기 감광성 물질(54)을 마스크로 하여 인이온을 주입하여 고압용 모스 트랜지스터의 저농도의 소오스, 드레인 영역 형성용 이온주입영역(55')과 필드이온주입영역 형성용 이온주입영역(55")을 형성하는 스텝으로 이루어지는 것을 특징으로 하는 반도체 장치의 제조방법.The method of claim 1, wherein the primary ion implantation process comprises the steps of growing an oxide film 53 on a substrate and then applying a photosensitive material 54, and photo-etching the photosensitive material 54 P-well (51). Exposing the source, the drain region and the site where the field ion implantation region is to be formed in the N-well 52, and injecting ions using the photosensitive material 54 as a mask to reduce the concentration of the high-voltage MOS transistor. A method of manufacturing a semiconductor device, comprising the steps of forming a source, a drain region forming ion implantation region (55 ') and a field ion implantation region forming ion implantation region (55 "). 제 1 항에 있어서, 2차 이온주입공정은 감광성 물질(56)을 기판전면에 걸쳐 다시 도포하는 스텝과, 상기 감광성 물질(56)을 사진식각하여 P- 웰(51)내에 필드이온주입영역과 N- 웰(52)내에 저농도의 소오스, 드레인 영역이 형성될 부위를 노출시키는 스텝과, 상기 감광성 물질(56)을 마스크로 하여 보론이온을 주입하여 고압용 모스 트랜지스터의 저농도 소오스, 드레인 영역을 형성하기 위한 이온주입영역(57")과 필드이온주입영역 형성용 이온주입영역(57')을 형성하는 스텝으로 이루어지는 것을 특징으로 하는 반도체 장치의 제조방법.The method of claim 1, wherein the secondary ion implantation process comprises the step of applying the photosensitive material 56 over the entire surface of the substrate, and photo-etching the photosensitive material 56 into the P-well 51 and the field ion implantation region. Exposing a portion where a low concentration source and drain region is to be formed in the N-well 52, and injecting boron ions using the photosensitive material 56 as a mask to form a low concentration source and drain region of the high-voltage MOS transistor. A method of manufacturing a semiconductor device, comprising the steps of forming an ion implantation region (57 ") and an ion implantation region (57 ') for forming a field ion implantation region. 제 1 항에 있어서, 상기 필드산화막(60)을 950℃에서 240분간 로코스공정으로 이용하여 성장시키는 것을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the field oxide film (60) is grown by a LOCOS process at 950 ° C for 240 minutes. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900014908A 1990-09-18 1990-09-18 Manufacturing method of semiconductor apparatus KR930008853B1 (en)

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KR1019900014908A KR930008853B1 (en) 1990-09-18 1990-09-18 Manufacturing method of semiconductor apparatus

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Application Number Priority Date Filing Date Title
KR1019900014908A KR930008853B1 (en) 1990-09-18 1990-09-18 Manufacturing method of semiconductor apparatus

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KR920007091A true KR920007091A (en) 1992-04-28
KR930008853B1 KR930008853B1 (en) 1993-09-16

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