KR900018845A - 데이터통신에 적합한 버스구성 - Google Patents

데이터통신에 적합한 버스구성 Download PDF

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Publication number
KR900018845A
KR900018845A KR1019900006710A KR900006710A KR900018845A KR 900018845 A KR900018845 A KR 900018845A KR 1019900006710 A KR1019900006710 A KR 1019900006710A KR 900006710 A KR900006710 A KR 900006710A KR 900018845 A KR900018845 A KR 900018845A
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KR
South Korea
Prior art keywords
bus
fifo
ram
system bus
network
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KR1019900006710A
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English (en)
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KR920008452B1 (ko
Inventor
에이치 가츠마타
고이치 다나카
도시유키 야구치
아키라 가누마
아키히토 니시카와
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
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Publication of KR900018845A publication Critical patent/KR900018845A/ko
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Publication of KR920008452B1 publication Critical patent/KR920008452B1/ko

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Communication Control (AREA)
  • Computer And Data Communications (AREA)
  • Small-Scale Networks (AREA)
  • Bus Control (AREA)

Abstract

내용 없음

Description

데이터통신에 적합한 버스구성
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따른 데이터통신제어장치와 그 주변부의 전체구성도, 제2도는 본 발명에 따른 데이터통신제어장치의 실시예의 구성도, 제3도는 본 발명에 따른 데이터통신제어장치의 다른 실시예의 구성도.

Claims (2)

  1. 네트워크버스(NB) 및 시스템버스(SB)간의 데이터전송을 제어하는 데이터통신제어장치에 있어서, 상기 네트워크(NB)에 접속된 네트워크버스 인타페이스(10′)와, 상기 시스템버스(SB)에 접속된 시스템버스 인타페이스(60′), 전송데이터를 기억하기 위한 2포트메모리를 포함한 FIFO/RAM(40′), 이 FIFO/RAM(40′)내의 2포트메모리에 대해 억세스를 행하기 위한 DMA부(50′), 데이터를 전송함에 있어서 상기 네트워크버스 인타페이스(10′)와 시스템버스 인타페이스(60′), FIFO/RAM(40′) 및 DMA부(50′)를 제어하는 마이크로프로세서(20′), 상기 FIFO/RAM(40′)내의 2포트메모리의 포트 1측을 적어도 상기 네트워크버스 인타페이스(10′)와 마이크로프로세서(20′) 및 DMA부(50′)에 접속시키기 위한 제1내부버스(B1), 상기 FIFO/RAM(40′)내의 2포트메모리의 포트 2측을 상기 DMA부(50′)에 접속시키기 위한 제2내부버스(B2) 및, 상기 마이크로프로세서(20′)를 상기 시스템버스인타페이스(60′)에 접속시키기 위한 제3내부버스(B3) 및, 상기 DMA부(50′)와 시스템버스 인터페이스(60′)를 접속시키는 제4내부버스(B4)를 구비하여 구성된 것을 특징으로 하는 데이터통신에 적합한 버스구성.
  2. 제1항에 있어서, 상기 제3내부버스(B3)를 상기 제1내부버스(B1)에 통합시켜 공통화한 것을 특징으로 하는 데이터통신에 적합한 버스구성.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900006710A 1989-05-13 1990-05-11 데이터통신에 적합한 버스구성 KR920008452B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP120151 1989-05-13
JP01-120151 1989-05-13
JP1120151A JPH077955B2 (ja) 1989-05-13 1989-05-13 データ通信制御装置

Publications (2)

Publication Number Publication Date
KR900018845A true KR900018845A (ko) 1990-12-22
KR920008452B1 KR920008452B1 (ko) 1992-09-29

Family

ID=14779225

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900006710A KR920008452B1 (ko) 1989-05-13 1990-05-11 데이터통신에 적합한 버스구성

Country Status (5)

Country Link
US (1) US5586263A (ko)
EP (1) EP0398178B1 (ko)
JP (1) JPH077955B2 (ko)
KR (1) KR920008452B1 (ko)
DE (1) DE69029053T2 (ko)

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FR2685512B1 (fr) * 1991-12-19 1994-02-11 Bull Sa Controleur de transfert multiple de donnees entre une pluralite de memoires et un bus d'ordinateur.
US5664223A (en) * 1994-04-05 1997-09-02 International Business Machines Corporation System for independently transferring data using two independently controlled DMA engines coupled between a FIFO buffer and two separate buses respectively
JP3531074B2 (ja) * 1994-11-28 2004-05-24 富士通株式会社 記憶装置制御システム
FR2755523B1 (fr) * 1996-11-05 1998-12-04 Bull Sa Circuit electrique pour echanger des donnees entre un microprocesseur et une memoire et calculateur comprenant un tel circuit
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FR2800952B1 (fr) * 1999-11-09 2001-12-07 Bull Sa Architecture d'un circuit de chiffrement mettant en oeuvre differents types d'algorithmes de chiffrement simultanement sans perte de performance
JP4097883B2 (ja) 2000-07-04 2008-06-11 松下電器産業株式会社 データ転送装置および方法
EP1233346A1 (de) * 2001-02-14 2002-08-21 Micronas GmbH Netzwerk-Co-Prozessor für Kraftfahrzeuge
US20020184381A1 (en) * 2001-05-30 2002-12-05 Celox Networks, Inc. Method and apparatus for dynamically controlling data flow on a bi-directional data bus
FI20012173A (fi) * 2001-11-09 2003-05-10 Nokia Corp Synkronisoiva paikallisverkko
CN113949454B (zh) * 2021-09-08 2023-02-14 国网电力科学研究院有限公司 光纤/e1转换设备、安全稳定控制系统站间通信方法

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Also Published As

Publication number Publication date
JPH02299337A (ja) 1990-12-11
US5586263A (en) 1996-12-17
DE69029053T2 (de) 1997-04-03
EP0398178A3 (en) 1991-05-08
EP0398178B1 (en) 1996-11-06
EP0398178A2 (en) 1990-11-22
KR920008452B1 (ko) 1992-09-29
JPH077955B2 (ja) 1995-01-30
DE69029053D1 (de) 1996-12-12

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