KR900013575A - 하이브리드 회로기판상의 후막 전기부품 제조방법 - Google Patents

하이브리드 회로기판상의 후막 전기부품 제조방법 Download PDF

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Publication number
KR900013575A
KR900013575A KR1019900001275A KR900001275A KR900013575A KR 900013575 A KR900013575 A KR 900013575A KR 1019900001275 A KR1019900001275 A KR 1019900001275A KR 900001275 A KR900001275 A KR 900001275A KR 900013575 A KR900013575 A KR 900013575A
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KR
South Korea
Prior art keywords
thick film
substrate
electrical component
film electrical
paste
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KR1019900001275A
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English (en)
Inventor
에스 타만카르 사티시
제이 킬스크너 마크
Original Assignee
래리 아아르 커세트
더 비이오우시이 그루우프 인코포레이팃드
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Application filed by 래리 아아르 커세트, 더 비이오우시이 그루우프 인코포레이팃드 filed Critical 래리 아아르 커세트
Publication of KR900013575A publication Critical patent/KR900013575A/ko

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/702Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof
    • H01L21/705Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof of thick-film circuits or parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867Applying pastes or inks, e.g. screen printing

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)

Abstract

내용 없음

Description

하이브리드 회로기판상의 후막 전기부품 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음

Claims (17)

  1. 하기 (a)-(d) 단계들로 구성되는, 하이브리드 회로기판상의 후막 전기 부품제조 방법 : (a) 도포하기 적합한 페이스트를 기판상에 제공하는 단계; (b) 기판상에 페이스트를 도포하는 단계; (c) 기판상의 페이스트를 건조시키는 단계; 및 (d) 불활성 가스와 이산화탄소로 구성되는 주변내 고온에서 기판을 소성시키는 단계.
  2. 제1항에 있어서, 주변이 이산화탄소 약 0.5부피%-약 50부피%를 포함하는 방법.
  3. 제2항에 있어서, 주변이 이산화탄소 약 2부피%-약 25부피%를 포함하는 방법.
  4. 제1항에 있어서, 스크린 인쇄로 페이스트를 기판상에 도포하는 방법.
  5. 제1항에 있어서, 후막 전기부품이 저항기인 방법.
  6. 제1항에 있어서, 후막 전기부품이 유전체인 방법.
  7. 제1항에 있어서, 후막 전기부품이 도체인 방법.
  8. 제7항에 있어서, 도체가 비금속(base metal)인 방법.
  9. 제8항에 있어서, 비금속이 구리 또는 이들의 합금인 방법.
  10. 제9항에 있어서, 비금속이 실질적으로 구리인 방법.
  11. 하기 (a)-(d) 단계들로 구성되는, 하이브리드 회로기판상의 후막 전기부품 제조방법,
    (a) 도포하기 적합한 페이스트를 기판상에 제공하는 단계; (b) 기판상에 페이스트를 도포하는 단계; (c) 기판상의 페이스트를 건조시키는 단계; 및 (d) 이산화탄소로 구성되는 주변내 고온에서 기판을 소성시키는 단계.
  12. 제11항에 있어서, 전기부품이 유전체인 방법.
  13. 제11항에 있어서, 후막 전기부품이 저항기인 방법.
  14. 제11항에 있어서, 후막 전기부품이 도체인 방법.
  15. 제14항에 있어서, 도체가 비금속으로 구성되는 방법.
  16. 제15항에 있어서, 비금속이 구리이거나 이들의 합금인 방법.
  17. 제15항에 있어서, 비금속이 실질적으로 구리인 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900001275A 1989-02-03 1990-02-02 하이브리드 회로기판상의 후막 전기부품 제조방법 KR900013575A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US30642989A 1989-02-03 1989-02-03
US07/306,429 1989-02-03

Publications (1)

Publication Number Publication Date
KR900013575A true KR900013575A (ko) 1990-09-06

Family

ID=23185246

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900001275A KR900013575A (ko) 1989-02-03 1990-02-02 하이브리드 회로기판상의 후막 전기부품 제조방법

Country Status (6)

Country Link
EP (1) EP0381430A3 (ko)
JP (1) JP2601554B2 (ko)
KR (1) KR900013575A (ko)
AU (1) AU625722B2 (ko)
CA (1) CA2007199C (ko)
ZA (1) ZA90154B (ko)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000124157A (ja) * 1998-08-10 2000-04-28 Vacuum Metallurgical Co Ltd Cu薄膜の形成法
US8053867B2 (en) 2008-08-20 2011-11-08 Honeywell International Inc. Phosphorous-comprising dopants and methods for forming phosphorous-doped regions in semiconductor substrates using phosphorous-comprising dopants
US7951696B2 (en) 2008-09-30 2011-05-31 Honeywell International Inc. Methods for simultaneously forming N-type and P-type doped regions using non-contact printing processes
US8518170B2 (en) 2008-12-29 2013-08-27 Honeywell International Inc. Boron-comprising inks for forming boron-doped regions in semiconductor substrates using non-contact printing processes and methods for fabricating such boron-comprising inks
US8324089B2 (en) 2009-07-23 2012-12-04 Honeywell International Inc. Compositions for forming doped regions in semiconductor substrates, methods for fabricating such compositions, and methods for forming doped regions using such compositions
US8629294B2 (en) 2011-08-25 2014-01-14 Honeywell International Inc. Borate esters, boron-comprising dopants, and methods of fabricating boron-comprising dopants
US8975170B2 (en) 2011-10-24 2015-03-10 Honeywell International Inc. Dopant ink compositions for forming doped regions in semiconductor substrates, and methods for fabricating dopant ink compositions

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4234367A (en) * 1979-03-23 1980-11-18 International Business Machines Corporation Method of making multilayered glass-ceramic structures having an internal distribution of copper-based conductors
JPS59995A (ja) * 1982-06-16 1984-01-06 富士通株式会社 銅導体多層構造体の製造方法
JPS60149191A (ja) * 1984-01-17 1985-08-06 株式会社日立製作所 Lsi実装基板の製造方法
US4622240A (en) * 1985-11-12 1986-11-11 Air Products And Chemicals, Inc. Process for manufacturing thick-film electrical components
JPS6369786A (ja) * 1986-09-09 1988-03-29 電気化学工業株式会社 メタライズ層をもつた窒化アルミニウム基板の製法
CA1274430A (en) * 1986-10-14 1990-09-25 E. I. Du Pont De Nemours And Company Controlled atmosphere firing process
US4772488A (en) * 1987-03-23 1988-09-20 General Electric Company Organic binder removal using CO2 plasma
JPS6441298A (en) * 1987-08-07 1989-02-13 Mitsubishi Electric Corp Manufacture of ceramic circuit substrate

Also Published As

Publication number Publication date
EP0381430A2 (en) 1990-08-08
EP0381430A3 (en) 1991-05-02
JPH02277282A (ja) 1990-11-13
ZA90154B (en) 1990-12-28
JP2601554B2 (ja) 1997-04-16
CA2007199A1 (en) 1990-08-03
AU4883690A (en) 1990-08-09
AU625722B2 (en) 1992-07-16
CA2007199C (en) 1993-05-18

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