KR900002169A - 부동 소수점 연산장치 - Google Patents

부동 소수점 연산장치 Download PDF

Info

Publication number
KR900002169A
KR900002169A KR1019890010030A KR890010030A KR900002169A KR 900002169 A KR900002169 A KR 900002169A KR 1019890010030 A KR1019890010030 A KR 1019890010030A KR 890010030 A KR890010030 A KR 890010030A KR 900002169 A KR900002169 A KR 900002169A
Authority
KR
South Korea
Prior art keywords
output
incrementer
receiving
mantissa
shifting
Prior art date
Application number
KR1019890010030A
Other languages
English (en)
Other versions
KR920005226B1 (ko
Inventor
아끼라 가쓰노
Original Assignee
야마모도 다꾸마
후지쓰 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP63174872A external-priority patent/JP2645422B2/ja
Priority claimed from JP63201891A external-priority patent/JP2578482B2/ja
Application filed by 야마모도 다꾸마, 후지쓰 가부시끼가이샤 filed Critical 야마모도 다꾸마
Publication of KR900002169A publication Critical patent/KR900002169A/ko
Application granted granted Critical
Publication of KR920005226B1 publication Critical patent/KR920005226B1/ko

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/535—Dividing only
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/552—Powers or roots, e.g. Pythagorean sums
    • G06F7/5525—Roots or inverse roots of single operands
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/535—Indexing scheme relating to groups G06F7/535 - G06F7/5375
    • G06F2207/5355—Using iterative approximation not using digit recurrence, e.g. Newton Raphson or Goldschmidt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/535—Indexing scheme relating to groups G06F7/535 - G06F7/5375
    • G06F2207/5356—Via reciprocal, i.e. calculate reciprocal only, or calculate reciprocal first and then the quotient from the reciprocal and the numerator
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G06F7/487—Multiplying; Dividing
    • G06F7/4873—Dividing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49936—Normalisation mentioned as feature only
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942—Significance control
    • G06F7/49947—Rounding
    • G06F7/49957—Implementation of IEEE-754 Standard

Abstract

내용 없음.

Description

부동 소수점 연산장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 부동 소수점 연산 장치의 종래예를 도시한 회로도.
제2도는 본 발명을 설명하는 요약 블록도.
제3도는 본 발명의 실시예에 따른 부동소수점 연산장치를 도시한 회로도.

Claims (4)

  1. 하나의 가수와 다른 하나의 가수를 승산하기 위한 고정 소수점 승산 수단(10)과, 출력을 정규화하기 위한 고정 소수점 승산 수단(10)의 출력을 수신하는 첫번째 오른쪽 이동 수단(13)과, 첫번째 오른쪽 이동수단(13)의출력을 수신하는 인크리멘터 수단(15)과, 첫번째 오른쪽 이동 수단(13)의 출력을 수신하고, 그의 출력을 인크리멘터 수단(15)에 공급하는 반올림 제어 수단(14)과, 인크리멘터 수단(15)의 캐리 신호를 수신하고, 캐리신호가 공급될때 인크리멘터 수단(15)의 출력을 오른쪽으로 이동시키기 위한 두번째 오른쪽 이동수단(16)과, 첫번째 오른쪽 이동 수단(13)의 출력을 수신하고, 제산 또는 제곱근 연산에서 반복근사중 하나의 연산이 첫번째 오른쪽 이동 수단(13)의 출력 대신에 반전출력을 인크리멘터 수단(15)에 각각 공급하기 위한 반전 수단과, 반복근사중 하나의 연산이 각각 실행될때 인크리멘트 신호가 공급되는 인크리멘터 수단(15)과, 제곱근 연산의 반복근사중 하나의 연산이 실행될때 인크리멘터 수단의 출력을 오른쪽으로 이동시키는 두번째 이동 수단(16)등을 포함하고, 2개의 입력으로부터 가수들을 연산하기 위한 가수연산 수단과, 2개의 압력으로부터 신호들을 연산하기 위한 신호연산수단(30)과, 연산되는 2개의 압력으로부터 지수들을 연산하기 위한 지수연산 수단으로 이루어지는 부동소수점 연산처리장치.
  2. 제1항에 있어서, 고정 소수점 승산 수단(10)이 중간결과 승산기와 가산회로(11) 및 다른 가산기(12)로 이루어지고, 다른 가산기(l2)의 캐리가 고정소수점 승산수단(10)의 출력을 1비트만큼 오른쪽으로 이동시키기 위한 첫번째 오른쪽 이동 수단(13)에 공급되는 부동소수점 연산처리장치.
  3. 제1항에 있어서, 가수 연산 수단이 인버터 수단과 인크리멘터 수단 사이에 멀티플렉서(42)를 더 포함하기 때문에, 멀티플렉서(42)가 제산 또는 제곱근 연산에서 반복근사중 각각 하나의 연산에 대한 제어신호가 주어지지 않을때 첫번째 오른쪽 이동수단(13)의 출력을 선택하고 제어신호가 주어질때 반전수단의 출력을 선택하는 부동소수점 연산처리장치.
  4. 하나의 가수와 다른 하나의 가수로 승산하기 위한 고정 소수점 승산 수단(10)과, 출력을 정규화하기 위한 고정소수점 승산 수단(10)의 출력을 수신하는 첫번째 오른쪽 이동 수단(13)과, 첫번째 오른쪽 이동 수단(13)의 출력을 수신하는 인크리멘터 수단(15)과, 첫번째 오른쪽 이동 수단(13)의 출력을 수신하고, 그의 출력을 인크리멘터 수단(15)에 공급하는 반올림 제어수단(14)과, 인크리멘터 수단(15)의 캐리신호를 수신하고, 캐리신호가 공급될 때 오른쪽으로 인크리멘터 수단(15)의 출력을 이동시키기 위한 두번째 오른쪽 이동수단(16)과, 첫번째 오른쪽 이동 수단(13)의 출력을 수신하고, 제곱근 연산에서 반복근사중 하나의 연산이 실행될때, 이진수 표시에서 소수점 이하의 모든 비트들이 반전되고 소수점 이상의 모든 비트들 "10"이 세트되는 그의 출력을 첫번째 오른쪽 이동 수단(13)의 출력대신에 인크리멘터 수단(l5)에 각각에 공급하기 위한 반전수단과, 제곱근 연산에서 반복근사중 하나의 연산이 실행될때 인크리멘트 신호가 공급되는 인크리멘터 수단등을 포함하고 2개의 입력으로부터 가수들을 연산하기 위한 가수연산수단과, 2개의 입력으로부터 신호들을 연산하기 위한 신호연산수단(30)과, 연산되는 2개의 입력으로부터 지수들을 연산하기 위한 지수연산수단으로 이루어지는 부동소수점 연산처리장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890010030A 1988-07-15 1989-07-14 부동 소수점 연산장치 KR920005226B1 (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP174872 1988-07-15
JP63174872A JP2645422B2 (ja) 1988-07-15 1988-07-15 浮動小数点演算処理装置
JP185005 1988-07-15
JP63201891A JP2578482B2 (ja) 1988-08-15 1988-08-15 浮動小数点演算器
JP201891 1988-08-15

Publications (2)

Publication Number Publication Date
KR900002169A true KR900002169A (ko) 1990-02-28
KR920005226B1 KR920005226B1 (ko) 1992-06-29

Family

ID=26496328

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890010030A KR920005226B1 (ko) 1988-07-15 1989-07-14 부동 소수점 연산장치

Country Status (4)

Country Link
US (1) US4999801A (ko)
EP (1) EP0351242B1 (ko)
KR (1) KR920005226B1 (ko)
DE (1) DE68929114T2 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100958163B1 (ko) * 2007-08-29 2010-05-18 세종대학교산학협력단 3차원 그래픽 가속기를 위한 부동소수점 누승기장치 및 그처리방법

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5293558A (en) * 1988-11-04 1994-03-08 Hitachi, Ltd Multiplication, division and square root extraction apparatus
US5220524A (en) * 1990-12-13 1993-06-15 Micron Technology, Inc. Machine method to perform newton iterations for reciprocals
US5206823A (en) * 1990-12-13 1993-04-27 Micron Technology, Inc. Apparatus to perform Newton iterations for reciprocal and reciprocal square root
US5157624A (en) * 1990-12-13 1992-10-20 Micron Technology, Inc. Machine method to perform newton iterations for reciprocal square roots
JPH04283831A (ja) * 1991-03-13 1992-10-08 Fujitsu Ltd 除算器
JP2722858B2 (ja) * 1991-06-03 1998-03-09 松下電器産業株式会社 開平演算装置
US5278782A (en) * 1991-06-03 1994-01-11 Matsushita Electric Industrial Co., Ltd. Square root operation device
US5272660A (en) * 1992-06-01 1993-12-21 Motorola, Inc. Method and apparatus for performing integer and floating point division using a single SRT divider in a data processor
US5204829A (en) * 1992-07-10 1993-04-20 Lsi Logic Corporation Interleaving operations in a floating-point numeric processor
US5377134A (en) * 1992-12-29 1994-12-27 International Business Machines Corporation Leading constant eliminator for extended precision in pipelined division
US5671170A (en) * 1993-05-05 1997-09-23 Hewlett-Packard Company Method and apparatus for correctly rounding results of division and square root computations
US5341321A (en) * 1993-05-05 1994-08-23 Hewlett-Packard Company Floating point arithmetic unit using modified Newton-Raphson technique for division and square root
US5404324A (en) * 1993-11-01 1995-04-04 Hewlett-Packard Company Methods and apparatus for performing division and square root computations in a computer
US5729481A (en) * 1995-03-31 1998-03-17 International Business Machines Corporation Method and system of rounding for quadratically converging division or square root
CN1075646C (zh) * 1996-01-19 2001-11-28 张胤微 一种高速乘法器
JP3352887B2 (ja) * 1996-09-09 2002-12-03 株式会社東芝 クランプ付除算器、このクランプ付除算器を備えた情報処理装置及び除算処理におけるクランプ方法
US5847979A (en) * 1996-10-31 1998-12-08 Samsung Electronics Company, Ltd. Method and apparatus for generating an initial estimate for a floating point reciprocal of a square root
DE69808362T2 (de) * 1997-04-01 2003-03-06 Matsushita Electric Ind Co Ltd Multiplizierverfahren und Multiplizierschaltung
JP4086459B2 (ja) * 2000-11-13 2008-05-14 Ｎｅｃエレクトロニクス株式会社 固定小数点データ生成方法及び固定小数点データ生成回路
NZ524378A (en) 2003-02-24 2004-12-24 Tait Electronics Ltd Binary shift and subtract divider for phase lock loops
US7467174B2 (en) * 2004-09-23 2008-12-16 Wisconsin Alumni Research Foundation Processing unit having decimal floating-point divider using Newton-Raphson iteration
US20060129624A1 (en) * 2004-12-09 2006-06-15 Abdallah Mohammad A Method and apparatus for performing a divide instruction
US7539720B2 (en) 2004-12-15 2009-05-26 Sun Microsystems, Inc. Low latency integer divider and integration with floating point divider and method
US20060179092A1 (en) * 2005-02-10 2006-08-10 Schmookler Martin S System and method for executing fixed point divide operations using a floating point multiply-add pipeline
US7747667B2 (en) * 2005-02-16 2010-06-29 Arm Limited Data processing apparatus and method for determining an initial estimate of a result value of a reciprocal operation
US8015228B2 (en) * 2005-02-16 2011-09-06 Arm Limited Data processing apparatus and method for performing a reciprocal operation on an input value to produce a result value
US8339689B1 (en) * 2006-06-30 2012-12-25 Marvell International Ltd. Exposure correction for scanners
US7949701B2 (en) * 2006-08-02 2011-05-24 Qualcomm Incorporated Method and system to perform shifting and rounding operations within a microprocessor
US8452831B2 (en) * 2009-03-31 2013-05-28 Oracle America, Inc. Apparatus and method for implementing hardware support for denormalized operands for floating-point divide operations
US8681973B2 (en) * 2010-09-15 2014-03-25 At&T Intellectual Property I, L.P. Methods, systems, and computer program products for performing homomorphic encryption and decryption on individual operations
US9086890B2 (en) 2012-01-06 2015-07-21 Oracle International Corporation Division unit with normalization circuit and plural divide engines for receiving instructions when divide engine availability is indicated
CN111353118B (zh) * 2018-12-20 2023-09-19 华润微集成电路(无锡)有限公司 开平方的方法及相应的用于开平方的电路
CN113407235B (zh) * 2021-06-28 2022-07-08 珠海一微半导体股份有限公司 一种基于硬件加速的运算电路系统及芯片

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0111587B1 (en) * 1982-12-23 1986-11-05 International Business Machines Corporation Method and apparatus for division operations
US4594680A (en) * 1983-05-04 1986-06-10 Sperry Corporation Apparatus for performing quadratic convergence division in a large data processing system
JPS60142738A (ja) * 1983-12-30 1985-07-27 Hitachi Ltd 内挿近似を使用する除算装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100958163B1 (ko) * 2007-08-29 2010-05-18 세종대학교산학협력단 3차원 그래픽 가속기를 위한 부동소수점 누승기장치 및 그처리방법

Also Published As

Publication number Publication date
US4999801A (en) 1991-03-12
EP0351242A3 (en) 1991-09-11
DE68929114T2 (de) 2000-04-13
KR920005226B1 (ko) 1992-06-29
EP0351242B1 (en) 1999-12-15
EP0351242A2 (en) 1990-01-17
DE68929114D1 (de) 2000-01-20

Similar Documents

Publication Publication Date Title
KR900002169A (ko) 부동 소수점 연산장치
EP0377837B1 (en) Floating point unit having simultaneous multiply and add
JPS5776635A (en) Floating multiplying circuit
TW345645B (en) Method and apparatus for performing high-precision multiply-add calculations using independent multiply and add instructions
KR960002061A (ko) 부동소수점수를 위한 산술연산장치
JPH04290122A (ja) 数値表現変換装置
KR900005284A (ko) 부동 소수점 승산용 스티키 비트 예측기
US5195052A (en) Circuit and method for performing integer power operations
KR100264960B1 (ko) 연산수의 승산/제산 방법과 그 장치
EP0551531A1 (en) Apparatus for executing ADD/SUB operations between IEEE standard floating-point numbers
US7337202B2 (en) Shift-and-negate unit within a fused multiply-adder circuit
US5170371A (en) Method and apparatus for rounding in high-speed multipliers
KR920003493B1 (ko) 부동 소숫점 표기를 기초로 하는 연산회로
KR880008143A (ko) 부동소수점 연산장치
JPH0540605A (ja) 浮動小数点乗算装置
KR920020850A (ko) 부동 소숫점 승.제산장치
KR20040033198A (ko) 부동소수점의 곱셈 및 누산장치
RU2022338C1 (ru) Устройство для умножения
JPH0251732A (ja) 浮動小数点演算器
JPH07200259A (ja) 演算処理方法および演算処理装置
JPH02112022A (ja) 浮動小数点形式の乗算器
SU898424A1 (ru) Устройство дл умножени и делени
GB2296803A (en) Apparatus for arithmetically operating floating-points
KUMAR et al. A Butterfly Architecture Based on Binary Signed-Digit Representation of Floating-Point
JPS60235241A (ja) 浮動小数点加算回路

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20050623

Year of fee payment: 14

LAPS Lapse due to unpaid annual fee