KR900001820B1 - The loop back circuit of analog and digital signal - Google Patents

Abstract

The circuit having a function of measuring analog/analog and digital/ digital gain and characteristic of a PCMODEC equipped semiconductor chip has an AD loop back signal selector (10) comprising a signal state checkers (A,B,C) detecting and discriminating digital signal (Di), loop back signal (LBi) and analog signal (Ai), a logic signal generators (D,E) generating a logic signal according to the state discriminated by the first and the third signal state checker, a loop signal selector (F) selecting one loop back signal according to the output signals of the first and the second logic state generators (D,E) and the second state checker, and a compensator (G,H) compensating the loopback signal selector (F).

Description

Loopback Circuit for Analog and Digital Signals

1 is a loopback circuit diagram of a conventional pulse code modulation code decoder (PCMCODEC).

2 is a circuit diagram of the embodiment of FIG.

3 is a loopback circuit diagram of the pulse code modulation crypto decoder of the present invention.

4 is a circuit diagram of the AD loopback signal selection circuit 10 of FIG.

5 is an exemplary circuit diagram of FIGS. 4A-F.

6 is an exemplary circuit diagram of FIG. 4 G, H, and an electronic switch, and Table 1 is a truth table of the loopback signal selection unit.

* Explanation of symbols for main parts of the drawings

1: A / D converter 2: D / A converter

3: Transmission filter 4: Reception filter

5 IC chip 6 Loopback signal level correction unit

10: AD loopback signal selection circuit ES ₁ : first electronic switch

ES ₂ : second electronic switch A: first signal state determiner

B: second signal state determiner C: third signal state determiner

D: first output logic generator E: second output logic generator

F: Loopback signal selector G: Analog loopback signal level correction

H: Digital loopback signal level correction unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse code modulation cryptographic decoder (aka PCMCODEC), and more particularly to measuring gain and characteristics of a digital versus digital signal by looping back both analog and digital signals in a semiconductor chip in which a circuit of a pulse code modulation crypto decoder is incorporated. In addition, the present invention relates to analog and digital signal loopback circuits that enable measurement of gain and characteristics of analog-to-analog signals.

In general, the code decoder of pulse code modulation has a function of selecting and outputting a specific signal while converting an analog signal into a digital signal or a digital signal into an analog signal in a transmission / reception system with a communication device, a telephone exchange or a computer terminal related to the transmission and reception of information. Have. In such a code decoder of pulse code modulation, a conventional loopback technique for measuring gain and characteristics in a chip is composed of a circuit system as shown in FIG. This is described as follows.

The digital input signal Di coming from the outside of the chip 5 is output as an analog output signal AO via the D / A converter 2 and the receiving filter 4. The analog output signal (AO) is output to the outside of the IC chip (5) by a wire, and furthermore, the electronic switch (ES), the transmission filter (3), and the A / D converter (within the IC chip (5)). The digital output signal DO is provided outside the IC chip 5 through 1). At this time, the electronic switch ES selectively transmits the analog output signal AO or the analog input signal Ai to the transmission filter 3 for the analog loopback signal ALBi coming from the outside of the IC chip 5. Will be supplied. On the other hand, a specific circuit of the electronic switch ES is composed of an inverter IO and two bidirectional gates G ₁ and G ₂ , as shown in FIG. ₂ . Here, the analog loopback signal generator 7 receives an external signal EXi and generates an analog loopback signal ALBi. The analog loopback signal ALBi is provided to the electronic switch ES via the level compensator 6. The analog loopback signal ALBi corrected by the level correction unit 6 becomes a signal inverted from the signal inverted by the inverter IO in the electronic switch ES and is connected to the bidirectional gates G ₁ and G ₂ . Each is provided. Accordingly, the analog input signal Ai or the analog output signal AO is provided to the transmission filter 3.

In such a conventional loopback circuit, only the digital signal is looped back and used to measure the normal electrical operation state or gain of the IC chip. Therefore, only the gain and characteristics of the digital input signal versus the digital output signal can be measured inside the chip. Therefore, when measuring the gain and the characteristic of the analog input signal versus the analog output signal, it is necessary to measure the gain and the characteristic of the pulse code modulated encryption decoder by connecting the wire in order to extract the signals to the outside of the chip. It takes a long time to do this, and also, when the wire is connected to the outside of the chip to pull out the signal, the possibility of noise inflow, etc. can not be excluded, thereby causing a problem that the reliability of the circuit in the IC chip is lowered.

SUMMARY OF THE INVENTION An object of the present invention is to enable a loopback of an analog or digital signal converted by a pulse code modulated encryption decoder by an electronic switch and an AD loopback signal selection circuit in a chip, thereby incorporating a pulse code modulated encryption decoder circuit. The present invention provides a loopback circuit for analog signals and digital signals that gives ease of measurement when measuring the characteristics and gain of the circuit and prevents the reliability of the semiconductor chip from deteriorating due to the inflow of external noise.

The present invention is characterized in that each of the first and second electronic switches is controlled by an output of an AD loopback signal selection circuit operated with a loopback signal, an analog input signal and a digital input signal, thereby transmitting a transmission filter by the first and second electronic switches. Analog and digital signals consisting of an analog signal loopback circuit consisting of an A / D converter, an A / D converter, and a receiving filter, and a digital signal loopback circuit consisting of a D / A converter, a receiving filter, a transmitting filter, and an A / D converter. In the loopback circuit of the present invention, in the AD loopback signal selection circuit of the loopback circuit, a first signal state determination unit for detecting and determining the presence or absence of an electrical signal related to a digital signal and a second signal for determining the presence or absence of a loopback signal are determined. A status determination section and a third signal status determination section related to the analog signal, and output the presence or absence of these signals as logic outputs, respectively. The first and second output logic generators, a loopback signal selector for selecting the loopback type as their logic outputs, and an analog and digital loopback signal level corrector for correcting the level of the output signal of the loopback signal selector. They are in loopback circuits of analog and digital signals.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. 3 shows a basic circuit diagram of the present invention. Here, the first electronic switch in which the analog input signal Ai coming from the outside or the analog output signal AO output from the receiving filter 4 inside the chip to the outside is controlled by the AD loopback signal selection circuit 10 is provided. Connected to the transmission filter 3 through the ES ₁ ), the digital input signal Di coming from the outside or the digital output signal DO output from the A / D converter 1 inside the chip to the outside is connected to the AD loopback. It is connected to the D / A converter 2 through the second electronic switch ES ₂ controlled by the signal selection circuit 10, and the AD loopback signal selection circuit 10 has an external loopback signal LBI analog. And digital input signals Ai and Di, and the output of the transmission filter 3 is input to the A / D converter 1 and the output of the D / A converter 2 is input to the reception filter 4. Connected. FIG. 4 is a detailed circuit diagram of the AD loopback signal selection circuit 10. The first signal state determiner A and the second signal related to the loopback signal LB are detected by detecting the presence or absence of a digital input signal Di. A first signal state determination unit (e) for detecting and determining the presence or absence of the state determination unit (B) and the analog input signal (Ai) is provided, and generates the logic according to the state determined therefrom. The loopback signal in accordance with an input state such as an output logic generator D and E, an output logic of the first and second output logic generators D and E, an output logic of the second signal state determiner B, and the like. A loopback signal selector (F) for selecting the type of the loopback signal selector (F) is provided and loops back the analog loopback signal (F ₁ ), the loopback signal (F ₁ ), and the digital signal to loop back the analog signal of the loopback signal selector (F). receiving analog and digital loop back the digital loopback signal (F ₂₎ The call level corrector (G, H) is provided. 5 and 6 are circuit diagrams of an embodiment of the AD loopback signal selection circuit 10. As shown in FIG.

Here, the first signal state determining unit A includes a CMOS circuit composed of transistors M ₁ , M ₂ , and M ₃ , M ₄ , transistors M ₅ , M ₆ , and capacitor C ₁ . The second and third signal state determination units (B, C) are also equivalent or identical to the circuit configuration of the first signal state determination unit (A). In addition, the first and second output logic generators D and E, which receive the outputs of the first and third signal state determination units A and C, include the transistors M _7- M ₁₀ , the capacitor C ₂ , and the inverter I. ₁ , I ₂ ) to have the same configuration. Also, the loopback signal selector F, which receives the outputs of the second signal state determiner B and the first and second output logic generators D and E, includes an AND gate A ₁ -A ₄ and an or gate O. ₁ , O ₂ ) and inverter I ₃ to generate the digital loopback signal F ₂ of the analog loopback signal F ₁ . Meanwhile, the analog and digital loopback signal level correction units G and H of FIG. 6 have the same configuration as the transistors M _{11 to} M ₁₄ and the inverters I _{4 to} I ₇ . The _first and second electronic switches ES ₁ and ES ₂ receiving the outputs of the chiefs G and H, respectively, have the same configuration as the bidirectional gates CG ₁ and CG ₂ and the inverter I ₈ .

Referring to the operation and effects of the present invention configured as described above are as follows. In FIG. 5, when the signal is not looped back, the loopback signal LBi is not applied or the OV is applied to the second signal state determination unit B, which determines the presence or absence of the loopback signal LBi. At this time, the loopback signal LBi through the CMOS of the transistors M ₁ , M ₂ and M ₃ , M _{4 of} the second signal state determination unit B outputs a low level. As shown in -4, the outputs F ₁ and F ₂ of the loopback signal selector F are all output at a low level regardless of whether the first and second output logic generators D and E are output. . Accordingly, low levels are output from the analog and digital loopback signal level correction units G and H shown in FIG. 6 to operate the bidirectional gate CG ₂ of the first and second electronic switches ES ₁ and ES ₂ . Therefore, the analog input signal Ai through the first electronic switch ES ₁ is provided to the transmission filter 3, and the digital input signal Di through the second electronic switch ES ₂ is a D / A converter. It is provided in (2). Therefore, as can be seen in FIG. 3, the digital input signal Di is output as it is through the D / A converter 2 and the receiving filter 4 as an analog output signal AO, and the analog input signal Ai is Through the transmission filter 3 and the A / D converter 1, the digital output signal DO is output as it is. Meanwhile, in FIG. 5, when the loopback signal LBi is present and the digital input signal Di is input, the outputs of the second signal state determination unit B and the first output logic generation unit D become high level. . As a result, the output of the AND gate A ₁ of the loopback signal selector F becomes high level, thereby outputting the high level from the OR gate O ₁ , and the output of the AND gate A ₁ becomes the inverter ( through the I ₃₎ are input to the AND gate (a ₄₎ is the output of the AND gate low level (a _4). In other words, analog loopback signal F ₁ outputs high level and digital loopback signal F ₂ remains low level. Therefore, as the high level is output from the analog loopback signal level correction unit G and the low level is output from the digital loopback signal level correction unit H, the bidirectional gate CG ₁ operates in the first electronic switch ES ₁ . In the second electronic switch ES ₂ , the bidirectional gate CG ₂ is operated. Therefore, as can be seen in the circuit diagram of FIG. 3, the analog output signal AO output from the receiving filter 4 is input to the transmitting filter 3 through the first electronic switch ES ₁ and the digital input signal ( Di) is input to the D / A converter 2, so that a digital signal loopback circuit is formed. On the other hand, in FIG. 5, when the loopback signal LBi is present and the analog input signal Ai is input, the analog loopback signal F ₁ of the loopback signal selection unit F is shown in FIG. Since the output is at a low level and the digital loopback signal F ₂ is output at a high level, at this time, the bidirectional gate CG ₂ and the bidirectional gate CG _{1 of the first} and second electronic switches ES ₁ and ES ₂ are respectively. It will work.

Accordingly, as can be seen from the circuit diagram of FIG. 3, the analog input signal Ai is input to the transmission filter 3 through the first electronic switch ES ₁ and the digital output signal DO of the A / D converter 1. ) Is input to the D / A converter 2 through the second electronic switch (ES ₂ ), so that the loopback circuit of the analog signal is configured.

In the present invention as described above, since the analog signal or the digital signal converted by the pulse code modulation code decoder is looped back by the electronic switch in the chip, the external noise is introduced when measuring the gain and characteristics of the pulse code modulation code decoder. This suppresses and shortens the measurement time.

Claims (2)

In the pulse code modulation / decryption decoder, which is composed of an A / D converter (1), a D / A converter (2), a transmission filter (3), and a reception filter (4), a digital signal Di and a loopback signal LBi. A first signal state determiner A, a second signal state determiner B, a third signal state determiner C, and a first signal state determiner configured to detect and determine the presence or absence of an analog signal Ai; First and second output logic generators (D) and (E) for generating the logic in accordance with the state determined by (A) and the third signal state determiner (C), and the first and second output logic generators. A loopback signal selection unit (F) for selecting the type of the loopback signal in accordance with an input state such as the output logic of (D) and (E) and the output logic of the second signal state determination unit (B), and the loopback signal selection Analog and digital to correct negative F output level. First and second electronic switches ES ₁ and ES connected to the loopback signal level correction units G and H to form an AD loopback signal selection circuit 10 and controlled by an output of the AD loopback signal selection circuit 10. ₂ ) the analog signal and the digital signal loopback circuit. 2. The transmission filter 3 is connected to the analog input / output signals Ai and Ao through the electronic switch ES ₁ , and the electronic switch ES _{2 to the} D / A converter _2. The loopback circuit of the analog signal and the digital signal, characterized in that the digital input and output signals (Di, Do) through the () is connected to be input.

Images