KR970002188B1 - A monitoring device of pseudo container path - Google Patents

Abstract

The virtual container path state monitor having a line matching unit connected to an external device, a decoder for decoding the signal input from the line matching unit to an NRZ(Non Return to Zero) signal, a first buffer for buffering transmission data, a second buffer for buffering the data received from a virtual container demultiplexer, a transmission clock generator for receiving a reception clock from the virtual container demultiplexer and generating a transmission clock, and a coder for coding the NRZ signal input from the second buffer according to the transmission clock and outputting it to the line matching unit, has a pseudo random signal generator for receiving an unstable oscillation clock from an exterior and generating a pseudo random signal; a first selector for selecting one of the transmission pseudo random signal received from the pseudo random signal generator and the reception NRZ signal received from the decoder by the control of a select control signal of a CPU and outputting it to the first buffer; a second selector for selecting one of the reception clock received from the line matching unit and the unstable oscillation clock by the control of the select control signal and outputting a write clock to the first buffer; a third selector for selecting one of the reception NRZ signal received from the decoder and the transmission NRZ signal received from the second buffer by a loop select signal of the CPU; a fourth selector for selecting one of the reception clock received from the line matching unit and the transmission clock received from the transmission clock generator by the loop select signal; and a pseudo random signal detector which is initialized by a reset signal of the CPU, receives the pseudo random signal from the third selector according to the clock received from the fourth selector, compares the input signal with the pseudo random signal and outputs the result to the CPU.

Description

Virtual Container Path Status Monitor

1 is a block diagram of a virtual container path state monitoring apparatus according to the present invention.

* Explanation of symbols for the main parts of the drawings

100: PRBS signal generator 200: line signal decoder

300: line signal encoder 410 to 440: selector

500: VC mapping buffer 600: PRBS signal detector

700: VC history buffer 800: transmit clock generator

The present invention relates to a path state monitoring apparatus of a virtual container (VC) for identifying a function of a low speed multiprocessor applied to a synchronous multiplexer of a digital synchronous transmission system. In particular, a pseudo random binary sequence (PRBS) Virtual container path status monitoring that can monitor path status by generating binary sequence signals, detecting pseudo random binary sequence (PRBS) signals input to the slow multi-processing unit according to its own or remote loopback function, and comparing the transmitted / received signals Relates to a device.

In testing a path of a virtual container used in a transmission system, in the past, by manually testing using an external measuring device, the path of a virtual container cannot be continuously monitored automatically, and thus it is not possible to quickly cope with a path failure.

Therefore, there is a need for a test apparatus that can detect the failure point through the loopback or remote loopback function of the system itself that can monitor the function of the switching circuits in the transmission system and respond quickly to the switching function request.

Therefore, the present invention devised in accordance with the above requirements, a functional test for a redundant multiple / demultiplex circuit used to increase the availability of the system in the normal operation state of the system to generate a pseudo random binary sequence (PRBS) signal To provide a virtual container path state monitoring device that can automatically test the path state by using a generator and a detector that detects a signal received by looping back the signal, and can easily implement test access to the multipath of VC1. There is this.

In order to achieve the above object, the present invention provides a line matching means connected to an external device, decoding means for decoding a signal input from the line matching means into an NRZ signal, first buffering means for buffering data for transmission; Second buffering means for buffering data received from the virtual container demultiplexer, transmission clock generation means for receiving a reception clock from the virtual container demultiplexer and generating a transmission clock, and the second buffering means according to the transmission clock. An apparatus comprising encoding means for encoding an NRZ signal inputted from an output signal to the line matching means, the apparatus comprising: pseudo random signal generation means for receiving a pseudo oscillation clock from an external source and generating a pseudo random signal; First selecting means for selecting one of a transmit pseudo random signal input from said pseudo random signal generating means and a received NRZ signal input from said decoding means by a central processing unit selection control signal and outputting it to said first buffering means; Second selection means for selecting one of a reception clock input from the line matching means and an independent oscillation clock input from the outside by a selection control signal of the central processing unit to provide a write clock to the first buffering means; Third selecting means for selecting one of a received NRZ signal input from said decoding means and a transmitted NRZ signal input from said second buffering means by a loop selection signal of said CPU; Fourth selecting means for selecting one of a reception clock input from said line matching means and a transmission clock input from said transmission clock generating means by a loop selection signal of said central processing unit; And receiving a pseudo random signal from the third selecting means according to a clock input from the fourth selecting means, and comparing the result with the pseudo random signal outputted from the pseudo random signal generating means, and comparing the result with the central processing apparatus. And pseudo pseudo signal detection means initialized by the reset signal of the CPU.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a configuration diagram of a virtual container path monitoring apparatus according to the present invention, in which 100 is a pseudorandom binary sequence (PRBS) signal generator, 200 is a line signal decoder, 300 is a line signal encoder, and 410 to 440 are selectors, 500 represents a VC mapping buffer, 600 represents a pseudorandom binary sequence (PRBS) signal detector, 700 represents a buffer in VC history, and 800 represents a transmit clock generator.

The present invention includes a line interface unit, a line signal coder, and an encoder (200, 300) to monitor a path state using an external measuring device as in the prior art.

In the case of testing using an external measuring device as in the prior art, the received bipolar signal inputted from the external measuring device includes a line interface unit, a line signal decoder 200, a selector A 410, and a selector B 420. The looped signal transmitted to the VC mapper through the VC mapping buffer 500 and input from the VC demultiplexer is transferred to an external measuring device through the buffer 700, the line signal encoder 300, and the line interface unit in the VC history. Is entered.

Then, in order to achieve the above object of the present invention, a pseudo-random binary sequence (PRBS) generator 100 and a loopback signal are received through the selectors C and D (430, 440) and compared with the transmitted / received signal. (CPU), the detector 600 is provided.

Now, with reference to Figure 1 will be described in detail the operation of each functional unit that is a component of the present invention.

The pseudorandom binary sequence (PRBS) signal generator 100 receives an external frequent oscillation clock (LO) 1 and generates a pseudorandom binary sequence (PRBS) signal according to the type of the dependent signal to be connected, thereby transmitting a PRBS signal. (7) is supplied to selector A (410).

The line signal decoder 200 receives the receive bipolar signal (PROS) 2 and the receive negative signal (RNEG) 3 from the line interface unit, decodes the applied line code according to the type of the dependent signal, and receives the received NRZ. Supply a (Non Return Zero) signal (RNRZ: 8) to selector A (410).

Here, when the line NRZ (NRZ) 8 signal is looped by the CPU function, the line NRZ (TNRZ) 8 signal is looped by the CPU function. When looped, the PRBS signal detector 600 is the same as the data of the transmission NRZ (TNRZ) 13 and the transmission NRZ (RNRZ) 13 signal contains a pseudorandom binary sequence (PRBS) signal. By detecting the PRBS signal in the CNS), a performance diagnosis function of the virtual container (VC) path by remote loopback is provided.

The selector A 410 is a transmission PRBS 7 signal input from the PRBS signal generator 100 and a reception NRZ signal input from the line signal decoder 200 according to the PRBS insertion 19 signal provided from an external CPU. Select one of (8) to output the payload 15 to the VC mapping buffer 500, the selector B 420 is an external self-oscillating clock (1) in accordance with the PRBS insertion (19) signal provided from an external CPU ) And the payload 15 selected by the selector A 410 according to the selected receive clock RCLK 16 by selecting one of the received clocks RCRC 4 inputted from the line interface unit. To be stored).

The data stored in the VC mapping buffer 500 is provided to the VC map in the form of up data UPDATA so that the data can be mapped to the VC according to an up clock (UPCLK) 22 supplied from an external VC map.

The transmission clock generator 800 generates a transmission clock TCLK 14 based on the reception clock 29 input from the VC demultiplexer.

The VC history buffer 700 stores downlink data 27 input from the VC demultiplexer according to the downlink clock 28 supplied from an external VC demultiplexer, and transmits the clock 14 to the transmit clock generator 800. The stored transmission NRZ (TNRZ) 13 signal is supplied to the line signal encoder 300 and the selector C 430.

The line signal encoder 300 receives the transmission clock 4 from the transmission clock generator 800 and transfers the transmission NRZ 13 signal input from the buffer 700 in the VC history to the encoding scheme determined by the digital level of the dependent signal. By encoding accordingly, the transmission polarity signal (TPOS) 5 and the transmission polarity (TNEG) 6 are supplied to the line interface unit.

The selector C 430 is for transmission received from the received NRZ (RNRZ) 8 signal input from the line signal decoder 200 and the VC history buffer 700 according to the loop selection signal 20 input from an external CPU. One of the NRZ (RNRZ) 13 signals is selected to output the PRBS received signal (PDATA) 17 to the PRBS signal detector 600.

The selector D 440 selects a clock PCRC 18 selected from one of a reception clock RCLK 4 input from the line interface unit and a transmission clock TCLK 14 input from the transmission clock generator 800. Output to PRBS signal detector 600.

The PRBS signal detector 600 has a function unit for generating the same signal as the signal generated by the PRBS signal generator 100 and has a self-generated PRBS received signal (PDATA) 7 input through the selector C 430. The PRBS signal is compared and the comparison result 25 is reported to the CPU, and the CPU outputs the CPU reset 26 to the PRBS signal detector 600 in accordance with the comparison result.

Here, the comparison function may be performed through an exclusive OR gate, and when the transmission signal and the reception signal are the same, a logic value 0 may be output, and when the comparison signal is different, the logic value 1 may be output.

Therefore, the present invention as described above can monitor the function of the switching circuits in the transmission system to quickly respond to the request for the ablation function, it can be utilized for the detection of the failure point through the loopback or remote loopback function of the system itself.

Claims (1)

Line matching means connected to an external device, decoding means for decoding a signal input from the line matching means into a Non Return to Zero (NRZ) signal, first buffering means for buffering transmission data, and a virtual container. Second buffering means for buffering data received from the medium-term unit, transmission clock generating means for receiving a reception clock from the virtual container demultiplexer and generating a transmission clock, and an NRZ input from the second buffering means according to the transmission clock. An apparatus comprising encoding means for encoding a signal and outputting the signal to the line matching means, comprising: pseudo random signal generating means for receiving a pseudo oscillation clock from outside and generating a pseudo random signal; First selection means for selecting one of a transmission pseudorandom signal input from the pseudo random signal generation means and a received NRZ signal input from the decoding means by the selection control signal of the central processing unit and outputting the signal to the first buffering means; Second selection means for selecting one of a reception clock input from the line matching means and an independent oscillation clock input from the outside by a selection control signal of the central processing unit to provide a write clock to the first buffering means; Third selecting means for selecting one of a means NRZ signal input from said decoding means and a transmission NRZ signal input from said second buffering means by a loop selection signal of said CPU; Fourth selecting means for selecting one of a reception clock input from said line matching means and a transmission clock input from said transmission clock generating means by a loop selection signal of said central processing unit; And receiving a pseudo random signal from the third selecting means according to a clock input from the fourth selecting means, and comparing the input signal with the pseudo random signal output from the pseudo random signal generating means, and comparing the result with the center. And a pseudo random signal detection means outputted to the processing unit and initialized by the reset signal of the central processing unit.