RU2263402C1 - Device for measuring bit error coefficients in fiber-optic communication lines - Google Patents

Abstract

FIELD: measuring equipment.

SUBSTANCE: device additionally features microcontrollers, one of which generates gating pulses, guided into controlled fiber-optic line before test pseudo-random series, and second one, while receiving gating pulses, produces synchronization signals.

EFFECT: simplified construction, higher efficiency, broader functional capabilities.

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Description

The invention relates to the field of measurement technology and can be used to measure the parameters of fiber optic information transmission lines.

A device is known for measuring the coefficient of bit errors of transmission lines, including two pseudo-random sequence generators, a comparing device, a sync generator, an error number accumulator [1 (p. 62, Fig. 6.5)].

Pseudo-random sequence generators are located at different ends of the transmission line. Generators are synchronized from one clock generator. The signal generated by the first pseudo-random sequence generator and passed the controlled transmission line is compared bitwise with the output signal of the second generator. In case of mismatch of the transmitted bits, an error signal is generated, which accumulates in the counter. The bit error rate is determined by the ratio of the number of bits affected by errors to the total number of transmitted bits.

The device has the following disadvantages:

- when checking communication lines of large length, it is not always possible to synchronize pseudo-random sequence generators from one source;

- the device does not contain optoelectronic and electro-optical converters for monitoring fiber-optic communication lines.

The disadvantages considered do not allow using this device to control the bit error rate of extended fiber-optic information transmission lines.

Known domestic and foreign devices for measuring the coefficient of bit errors in the transmission channels of information (including fiber optic):

- EDT-135 company Global Headquarters (USA), [2]

- "UKOL-15", CJSC "Technodals" (St. Petersburg, Russia) [3];

- ЕВН 30/120 company "ELECTRONICA" (Hungary) [4];

- OG-3 company "Siemens" [5];

- IKO-2-2 (5) CJSC Supertekhpribor [5];

- ID-2/8/34 company "Radian" [6];

- SM-E1 company "Simos" [7].

All of the listed devices are constructed according to one functional scheme and contain pseudorandom sequence generators at different ends of the line and a sync generator at the transmitting end of the monitored line. For the functioning of all considered devices, channel-forming equipment is needed, which generates a test measuring signal, consisting simultaneously of a pseudo-random sequence and synchronization pulses. Moreover, for mixing clock signals into the transmitted message, all considered devices use three-level linear codes HDB-3 or AMI (negative level, positive level, zero value). Fiber-optic data transmission lines can work only with two-level linear codes (the optical signal is always unipolar - the optical power level is zero or non-zero).

Thus, the devices in question cannot be used to control fiber-optic transmission lines without additional conversion of a three-level linear code into a two-level one. Since complex encoding and decoding devices are needed, the devices have a complex architecture and roads (a bit error meter for a transmission speed of 34 Mbps costs about $ 6000). In addition to the tested transmission channel — the fiber-optic communication line — channel-forming devices and linear code converters are tested simultaneously; therefore, it is difficult to distinguish bits affected by errors directly in the fiber-optic path.

The closest in design features to the proposed device is a device for measuring bit errors described in [8].

The device contains two sections: a generator and an analyzer section. The generator section contains a shift register, a clock generator, an encoder, a comparison device, and the output of the clock generator is connected to the synchronization input of the shift register and one of the encoder inputs, the first input of the comparison device is connected to the output of one of the bits of the shift register, the second to the output of the last register bit shift, and the output is to the input of the shift register data. The analyzer section contains a second shift register, two comparison devices, an error counter (bits affected by errors), a decoder, and the decoder synchronization output is connected to the shift register synchronization input, the first input of the second comparison device is connected to the output of one of the bits of the second shift register, the second one to the output of the last bit of the second shift register, and the output to the data input of the second shift register, the first input of the third comparison device is connected to the output of the second shift register, the second input is given to the output ny decoder, and the output of the third comparison device is connected to the input of the counter of bits affected by errors.

The device operates as follows. The clock generator of the generator section generates periodic pulses (synchronization pulses), shifting the information at the input of data into the register. The input of the shift register data is connected to the output of the EXCLUSIVE OR comparison logic element. The EXCLUSIVE OR comparison element generates a logical unit signal if the information bits at its inputs do not match, and a logical zero signal if the bits match. The inputs of the logic element are connected to the output of the shift register (the output of the last bit) and the output of one of the bits of this register. This switching scheme allows you to organize a generator of a pseudo-random sequence of bits. The length of the pseudo-random sequence (the number of bits of the register) is determined by the recommendations of ITU-T O.51, depending on the speed of digital transmission in the channel. In addition, there is a recommendation for choosing a test sequence configuration. So, for a digital transmission speed in the channel from 64 to 8448 kbit / s, the pseudo-random bit sequence should be described by the polynomial D ¹⁵ + D ^-14 + 1 = 0, and for the speed of 34368 kbit / s - by the polynomial D ²³ + D ^-18 + 1 = 0. In order to simulate the pseudo-random sequence described by the polynomial D ¹⁵ + D ^-14 + 1 = 0, it is necessary in the circuit described above to connect the outputs of the 15th and 14th bits of the shifting 15-bit register to the inputs of the logic element of the “EXCLUSIVE OR” comparison . Similarly, to simulate a pseudo-random sequence described by the polynomial D ²³ + D ^-18 + 1 = 0, it is necessary to connect the outputs of the 23rd and 18th bits of the shifting 23-bit register to the inputs of the logic element of the EXCLUSIVE OR comparison.

The generated pseudo-random sequence is sent to the information input of the encoder. The encoder synchronization input receives a signal from a clock generator. The encoder device depends on the speed of information transmission in the channel.

The synchronization signals from the clock generator and the data from the output of the shift register are fed to the inputs of the encoder (encoder), combining these signals into a code sequence. In the simplest case, a plesiochronous digital hierarchy (PDI or PDH) is used. For a data transfer rate of 2048 kbit / s, eight-bit code combinations are synchronously multiplexed and a primary digital signal is formed, denoted E1. The structure of the primary digital signal, according to the recommendations of G.704 and G.732, is presented in figure 1.

It consists of 32-channel positions with a duration of 3.91 μs each with a total duration of 125 μs. Zero and sixteenth intervals are intended for official purposes:

- zero channel interval (KI0) for transmitting signals: synchronization, control, management and warning of an accident;

- the sixteenth channel interval KI16 is used to transmit signaling messages, over-cycle synchronization and indication of the emergency state.

A pseudo-random test sequence fills the channel information intervals from 1 to 15, from 17 to 29 and 31.

Subsequent stages of the hierarchy (characterized by a higher transmission rate) can be obtained by bit-wise multiplexing of several signals of the first stage, for example, the second stage (E2) is provided by combining four E1 signals with the formation of a cycle with a duration of 100.4 μs (see figure 2).

For digital stream E2, the first ten bits are a clock signal. The whole cycle is divided into four blocks I, II, III, IV by speed matching commands, which are used to notify the receiving side of the presence of inserts that align the flow rates of E1 and are removed at the reception.

Blocks I, II, III, IV contain alternating information bits of four E1 signals with a test pseudo-random sequence.

Similarly, we obtain a cyclic structure of the third degree of E3 multiplexing, in which the transmission rate of 34.368 Mbit / s is provided, however, four E2 streams or sixteen E1 streams are bitwise combined and the cycle duration decreases to 44.7 μs. The fourth degree of multiplexing provides a transmission rate of 139.264 Mb / s (the device considered as a prototype provides exactly this level of hierarchy) and the last fifth degree of the plesiochronous digital hierarchy provides a speed of 564.992 Mb / s.

The device in question can also work with virtual containers of information transmission systems with a synchronous digital hierarchy (SDH or SDH). In this case, the device encoder fills the entire information strip of the container with a test sequence.

The decoder of the analyzer section performs the inverse function of the encoder; it extracts synchronization signals and a test pseudorandom sequence from a structured digital stream. The synchronization signals are fed to the synchronization input of the second generator of the pseudo-random sequence, similar to that located in the generator section and consisting of the second shift register and the second exclusive logic gate “EXCLUSIVE OR”. The test pseudo-random sequence allocated by the decoder is fed to one of the inputs of the third EXCLUSIVE OR logic element, the pseudo-random sequence from the output of the second generator of the pseudorandom sequence (the output of the second shift register) is fed to the second input of the element. If the sequence bit does not match, the logic element generates a logical unit signal, calculated by the error counter. The bit error rate is determined by the ratio of the number of bits affected by errors to the total number of transmitted bits.

The device has the following disadvantages:

- high cost and manufacturing complexity;

- does not allow to select the bits affected by errors directly in the transmission channel, since these errors are summed with errors in the encoder, decoder, synchronization channels;

- standard linear codes of digital streams from E1 and higher HDB-3 or AMI have a three-level structure and cannot be transmitted via a fiber-optic communication line (for transmission, it is necessary to convert a three-level code into a two-level one, which can introduce additional bit errors into the transmission channel).

Not all digital transmission lines use structured digital streams PDI (PDH) or SDH (SDH). There are local digital data acquisition systems using signals from measuring transducers of physical quantities, telemetry systems using digital transmission channels for monitoring and controlling objects, which have their own structure of digital streams [10]. To control the bit error rate for such transmission lines, it is impractical to use an expensive channel-forming apparatus.

The proposed device solves the problem of simplification and the ability to measure the number of bits affected by errors directly in the fiber optic transmission lines of information.

The essence of the invention lies in the fact that a microcontroller, an electronic switch transmitting an optical module are introduced into the generator section of the device, a second microcontroller, a second electronic switch, a receiving optical module, and a second clock generator are introduced into the device analyzer section, the output of the clock generator of the generator section being connected to the input synchronization of the first microcontroller, one of the output ports of the first microcontroller is connected to the synchronization input of the first shift register, output p shift shear through a switch, the second input of which is connected to one of the output ports of the microcontroller, and the control input is connected to the other output port of the microcontroller, connected to the input of the transmitting optical module, optically connected by a fiber-optic cable to the receiving optical module, the output of which is connected to one of the input ports of the second microcontroller and to one of the inputs of the second comparison device, the output of the comparison device is connected to a bit counter affected by errors through the second electronic comm ator, whose control input is connected to one of the output ports of the second microcontroller, one of the output ports of microcontroller connected to the sections of the shift register synchronizing the input analyzer, the clock output section of the analyzer is connected to the second input synchronization microcontroller.

Figure 3 shows the structural diagram of the meter bit error coefficient in fiber optic transmission lines.

The device consists of a generator section and a section of the analyzer CA. The generator section contains a clock generator 1, a microcontroller 2, a shift register 3, a comparison device 4, an electronic switch 5, a transmitting optical module 6. The analyzer section contains a second microcontroller 7, a second clock 8, a receiving optical module 9, a second comparison device 10, and a second electronic switch 11, second shift register 12, third comparison device 13, counter of bits affected by errors 14. Sections are connected by a fiber-optic cable, which is not part of the device, but is part of the control a fiber optic transmission line.

The device operates as follows.

When the supply voltages are turned on, microcontrollers 2 and 7 begin to execute instructions written in the resident program memory. Plots of processes at various points of the generator section and analyzer section are presented in figure 4.

The program starts with the installation of a signal at the control input of the switch 5 that allows the input of the transmitting optical module to be connected to the output port of the microcontroller 2. After waiting for the execution of N machine cycles, during which the switch 5 is activated, the start pulse is generated at the output of this port. The duration of this pulse is selected based on two conditions:

- the duration of the start pulse must exceed the duration of the data pulses transmitted over the transmission line, and provide an energy reserve sufficient to transmit it without distortion;

- the duration of the start pulse must correspond to the permitted range in duration for the transmitting and receiving modules.

After the start pulse is generated, the microcontroller 2 sets a signal at the control input of the switch 5, allowing the input of the transmitting optical module 6 to be connected to the output of the shift register 3. After waiting, during which the switch 5 is activated, the output of the microcontroller 2 connected to the synchronization input, the shift register 3, a sequence of clock pulses is generated. The duration of the clock is determined by the duration of the machine cycle of the microcontroller 2 and is determined by the frequency of the clock generator 1. The repetition rate should correspond to the data rate at which the communication line is tested. The number of pulses in the sequence of clock pulses must comply with the recommendations of ITU-TO.152 (GOST 26783-85). The shift register 3 along the front of the synchronization pulses generates a pseudo-random sequence of pulses at its output. The structure of the pseudo-random sequence is set by the comparison device 4 in accordance with the recommendations of ITU-TO.152 (GOST 26783-85) and is determined by the number of bits of the register 3, the outputs of which are connected to the inputs of the comparison device 4. The pseudo-random sequence through the switch 5 is sent to the input of the transmitting optical module 6 , then converted into an optical signal and sent to the tested fiber optic transmission line.

The microcontroller 2 proceeds to the formation of the next test sequence, consisting of a start pulse and a pseudo-random sequence of a given duration and structure.

The test sequence generated by the generator section via a fiber-optic data transmission line is fed to the optical input of the receiving optical module of the analyzer section 9. The output of the receiving optical module 9 is connected to the input of the microcontroller 7 and one of the inputs of the comparison device 10. The second microcontroller 7 is used for the decay of the signal at its input begins to execute an external interrupt processing routine. The interrupt routine performs the following actions:

- prohibits externally interrupts;

- generates a signal at the input of the second switch 11, allowing the connection of the output of the comparison device 10 with the input of the bit counter affected by errors 14 (in the initial state, the switch is open);

- through N machine cycles (the frequencies of the generators 1 and 8 must be equal) forms a sequence of clock pulses similar to the sequence generated in the generator section;

- after generating a sequence of clock pulses, it switches off the switch 11 (breaks the connection between the counter of bits affected by errors 14 and the output of the comparison device 10);

- allows external interrupts.

This completes the interrupt routine.

The sequence of synchronization pulses generated by the microcontroller 7 is sent to the synchronization input of the shift register 12 similar to the shift register 3. Register 12 together with the comparison device 13 forms a pseudo-random sequence similar to the sequence generated by the register 3 and the comparison device 4. This sequence is sent to the second input of the comparison device 10, where it is compared with the pseudo-random sequence from the output of the photodetector module 9. If the bits of the last consistently produced error signal which is fed to the input of the counter 14. The ratio of the number of bits affected by errors, the total number of transmitted bits determine bit error rate. Counting the transmitted bits can be carried out by both microcontroller 2 and the second microcontroller 7.

Thus, the goal is achieved - it is possible to measure the bit error coefficient of fiber-optic transmission lines and the device is greatly simplified, since it does not contain complex encoding and decoding devices for transmitting synchronization pulses in conjunction with test bit sequences.

References

1. Baklanov I.G. Testing and diagnostics of communication systems. - M: Eco-Trends, 2001, - 264 p.

2. Information from the Global Headquarters Web server, http://www.acterna.com.

3. Information from the Web server of Energy Telecom, http://www.energy-telecom.ru.

4. Information from the Web server of the company "ELECTRONICS", http://www.elektronika.ru.

5. Information from the Web server of the Internet project "RusCable.ru", http://www.ruscable.ru.

6. Information from the Web server of the company "Radian", http://www.radian.spb.ru.

7. Tester SM-E1. Technical description and operating instructions CM2. 135.000TO, July 2003

8. Information from the Trend Communications Web server, http: // www. trendcomms.corn March 2004

9. Ivanov Yu.P., Levin L.S. and others. The terminal equipment complex of digital transmission systems for BIS // Elektrosvyaz, 1992, No. 3.

10. GOST RV 50899-96. Fiber optic data acquisition networks based on fiber optic sensors. General technical requirements.

Claims (1)

A meter of the coefficient of bit errors in fiber-optic transmission lines, comprising a comparison device installed in the generator sections, a clock and a shift register, the output and additional output of which are connected to the inputs of the comparison device, the output of which is connected to the register data input, the second register installed in the analysis section a shift, the output and additional output of which is connected to the inputs of the second comparison device, the output of which is connected to the data input of the second shift register, bit counter, p erroneous, a third comparison device, the first input of which is connected to the output of the second shift register, characterized in that a microcontroller is inserted into the generator section, an electronic switch transmitting an optical module connected to the fiber-optic transmission line under test, a second microcontroller is introduced into the analysis section, a second clock, a second electronic switch and a receiving optical module connected to the second end of the tested fiber-optic transmission line, and the clock output the generator section of the generator is connected to the synchronization input of the first microcontroller, the outputs of which are connected to the synchronization input of the first shift register, the first commutated and control inputs of the electronic switch, the output of the first shift register is connected to the second switched input of the electronic switch, the output of which is connected to the input of the transmitting optical module, the output the clock of the analysis section is connected to the synchronization input of the second microcontroller, the outputs of which are connected to the sync input the second shift register, the control input of the second electronic switch, the output of the receiving optical module is connected to the input of the second microcontroller and the second input of the third comparison device, the output of which is connected to the input of the bit counter affected by errors through the second electronic switch.

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