KR0174601B1 - Noise Reduction Circuit of Electronic Switching System - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

An electronic exchange system.

2. The technical problem to be solved by the invention

The digital pattern error caused by the noise flowing from the outside to the transmission line between the switch unit and the digital telephone in the electronic switching system is eliminated.

3. Summary of Solution to Invention

A circuit for removing noise between the digital telephone and the digital interface port in an electronic switching system comprising a digital telephone and a switch interface and a digital interface port for interfacing between the digital telephone and the switch means. The digital interface port which outputs a sync signal when a start bit indicating the start of a data frame is detected within a window pulse signal section according to the detection period of the start bit, and generates a sync error signal when it is not compressed within the section. Generating means for generating a buffer enable signal when outputting the sync signal, and generating a buffer disable signal when the sync error signal is generated, and transmitting data between the digital interface port and the switch means; Buffer Enable When the signal is generated, buffering the data between the two to transfer the data of the frame, and when the buffer disable signal is generated buffer means for stopping the data transmission of the frame.

4. Important uses of the invention

The digital pattern error caused by the noise flowing from the outside to the transmission line between the switch unit and the digital telephone in the electronic switching system is eliminated.

Description

Noise Reduction Circuit of Electronic Switching System

1 is a block diagram of a transmission circuit in a conventional electronic switching system.

2 is a block diagram of a noise canceling circuit in the electronic switching system according to the present invention.

3 is a detailed block diagram of the digital interface port shown in FIG.

4 is an operational waveform diagram of each part of the noise canceling circuit according to the present invention;

* Explanation of symbols for main parts of the drawings

10: digital telephone 20: digital interface port

21: buffer 22: flip-flop

30: switch unit 46: clock generator

47: window pulse generator 48: start bit detector

49: error detector

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise canceling circuit of an electronic switching system, and more particularly, to a noise canceling circuit for removing a digital pattern error caused by noise introduced from outside between a switch unit and a digital telephone.

1 is a block diagram of a transmission circuit between a switch unit and a digital telephone in a general electronic switching system. The digital interface port 20 and the digital telephone 10 are connected to each other by a two-wire twisted pair. The digital signal output from 10) is input to the digital interface port 20 through the two-wire twist gear (A). The digital interface port 20 inputs the digital signal and converts the signal into a pulse code modulation (PCM) signal. The digital interface port 20 is a single chip. TP4301, TP3402, TP3403, and the like. The switch unit 30 controls call connection and data transmission operations of the digital telephone and the digital telephone 10 corresponding to the digital signal input from the digital interface port 20 through the digital transmission line B. FIG.

However, due to an unexpected inflow of external noise into the two-wire twist gear A, a digital pattern error occurs in the digital signal, so that the user hears a disgusting noise during a call, and incorrectly controls the noise to connect a call during a call. This disconnected problem occurred.

Accordingly, an object of the present invention is to provide a noise removing circuit for removing a digital pattern error caused by noise introduced from the outside between the switch unit and the digital telephone of the electronic switching system.

In order to achieve the above object, the present invention provides a circuit for removing noise between the digital telephone and the digital interface port in an electronic switching system comprising a digital interface port for interfacing between the digital telephone and the switch means. If a start bit indicating the start of a data frame is detected in the window pulse signal section according to the detection period of the start bit when converting the transmission digital signal output from the digital telephone, the sink signal is output. The digital interface port for generating an error signal, a generating means for generating a buffer enable signal when the sink signal is output, and a buffer disable signal for generating a buffer disable signal when the sink error signal is generated, and the digital interface port and the switch means. Between Buffer means for transmitting data and buffering the data between the two frames when the buffer enable signal is generated, and transmitting data of the corresponding frame; and stopping the buffering when the buffer disable signal is generated. It is characterized by the configuration.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a noise canceling circuit in the electronic switching system according to the present invention.

The digital interface port 20 converts a transmission digital signal output from the digital telephone 10 into a transmission PCM signal in synchronization with a system clock CLK of the electronic switching system, or converts a reception PCM signal input from the buffer 21. To convert it into a received digital signal. The transmission digital signal controls the generation of the sync pulse signal SC and the sync error signal SE to remove the digital pattern error generated by the influence of external noise.

The flip-flop 22 generates a buffer control signal in response to the input of the sync pulse signal SC and the sync error pulse signal SE.

The buffer 21 blocks the digital pattern error between the digital interface port 20 and the switch unit 30 according to the buffer control signal.

The switch unit 30 controls call connection and data transmission operations of the digital telephone corresponding to the digital signal and the digital telephone 10.

3 is a detailed block diagram of the digital interface port 20 shown in FIG.

The transmission digital signal processor 45 includes a line interface 40, an AMI formatter 41, a scrambler 42, and a transmission PCM interface 43. The line interface 40 inputs a transmission digital signal output from the digital telephone 10 through the telephone line A, and then inputs it to the Alternate Mark Inversion formatter 41. The AMI formatter 41 inputs the transmission digital signal, converts it into a transmission AMI signal waveform in which logic high, that is, 1 is alternately repeated, is input to the scrambler 42.

The scrambler 42 scrambles the transmission AMI signal and inputs it to the transmission PCM interface 43. The transmission PCM interface 43 converts the scrambled signal input from the scrambler 42 into a transmission PCM signal and transmits the signal to the buffer 21.

On the other hand, the reception digital signal processing unit 54 is composed of a line receiver 50, an AMI deformatter 51, a descrambler 52 and a reception PCM interface 53. The reception PCM interface 53 inputs a reception PCM signal output from the buffer 21 and inputs it to the descrambler 52 as a scrambled reception AMI signal. The descrambler 52 descrambles the scrambled received AMI signal and inputs the descrambled signal to the AMI formatter 51. The AMI formatter 51 converts the received AMI signal into a received digital signal and inputs the received AMI signal to the line receiver 50. The line receiver 50 transmits the digital signal input from the AMI formatter 51 to the digital telephone 10 through the telephone line A. FIG.

The clock generator 46 generates a digital interface clock of the digital interface port 20 in synchronization with the system clock CLK of the electronic switching system.

The start bit detector 48 detects a start bit representing the start of each data frame of the transmitted AMI signal output from the AMI formatter, generates a start bit signal, and inputs it to the clock generator 46 to input a window pulse control signal. To generate.

The window pulse generator 47 generates a window pulse every predetermined time by the window pulse control signal.

The error detector 49 is composed of an AND gate, and performs an AND operation on the start bit signal and the window pulse signal to generate a sync signal when the start bit signal and the window pulse signal coincide with each other. If the signal does not coincide with the window pulse signal, a sync error (SE) signal is generated.

4 is an operational waveform diagram of each part according to the present invention.

Hereinafter, an embodiment of the operation of the noise canceling circuit according to the present invention will be described in detail with reference to FIGS. 2 to 4.

The transmission digital signal output from the digital telephone 10 is input to the digital interface port 20 through the telephone line A of the two-wire twisted pair and converted into a transmission PCM signal. At this time, a digital transmission error may be generated by external noise on the telephone line A. In this case, the transmission PCM signal is recovered to abnormal data by a transmission error, and the caller may receive a large noise during a call. Therefore, in the present invention, by detecting such an error and blocking the error signal, the noise is eliminated by making a no signal.

In more detail, the digital interface port 20 is a master frame signal having a period of 125 μsec as shown in FIG. 4A (4a) in order to check digital pattern errors generated by the transmission digital signal affected by external noise. C, D, E, F, G) (FP). In this case, the transmission interval per frame of the transmission AMI signal is 125μsec. That is, the start bit of the frame is detected between the master frame signals by the start bit detector 48 at a cycle of 125 μsec. Accordingly, the window pulse generator 47 generates a window pulse signal having a cycle of 125 μsec including a range in which the start bit is detected. Therefore, in the normal case, the start bit may be detected within the section where the window pulse signal is generated, but when the digital pattern error occurs, the start bit may not be detected within the section of the window pulse signal.

That is, during the period (125 μsec) of the master frame signal FP, the start bits L, M, N, O recovered by the start bit detector as shown in (4c) of FIG. 4 are equal to (4b) in FIG. When not in the window pulse signals H, I, J, K, i.e., when the start bit M, O shown in (4c) of FIG. 4 is not in the window pulse signals I, K. A digital pattern error due to external noise is generated in the transmission line A between the digital telephone 10 and the digital interface port 20. At this time, the error detector 49 inputs the start bits M and O and the window pulse signals I and K, and performs an AND operation to perform a sync error signal R as shown in FIG. 4E. , S) (SE) is generated and input as a set (SET) signal of the flip-flop 22. Accordingly, the output of the flip-flop 22 is in a logic high state in the section TU as shown in 4f of FIG. 4, and the buffer 21 is in section A of 4g in FIG. In this case, the PCM signal cannot be transmitted. That is, transmission of the digital pattern error is blocked.

On the other hand, when the start bits L and N as shown in Fig. 4C of Fig. 4 are in the window pulse signals H and J of Fig. 4B, the error detector 49 is used as the fourth bit. The sync pulse signals P and Q SC as shown in (40) are generated and input as the reset signal of the flip-flop 22. As a result, the output of the flip-flop 22 goes low, and the buffer 21 transmits the PCM signal to the switch unit 30.

As described above, the present invention has the advantage of eliminating digital pattern errors caused by noise flowing from the outside in the transmission line between the switch unit and the digital telephone 10 in the electronic switching system.

Claims (2)

A circuit for removing noise between the digital telephone and the digital interface port in an electronic switching system comprising a digital telephone and a switch interface and a digital interface port for interfacing between the digital telephone and the switch means. The digital interface port for outputting a sync signal when a start bit indicating the start of a data frame is detected within a window pulse signal section according to a detection period of the start bit, and generating a sync error signal if not detected within the section. Generating means for generating a buffer enable signal when outputting the sync signal, and generating a buffer disable signal when the sync error signal is generated, and transmitting data between the digital interface port and the switch means; Buffer in Buffers the data between the event of the adoption of the signals, and transmit data of the corresponding frame, the noise removing circuit, characterized by constituted by any buffer means to stop the data transmission of the frame to stop in case the buffer of the buffer disable signal. The digital interface port of claim 1, further comprising: a start bit detector for detecting the start bit and generating a start bit signal; a window pulse generator for generating the window pulse signal in synchronization with a system clock; An error detector configured to perform an AND operation on the window pulse signal to generate the sync signal when the start bit signal is within the window pulse signal section, and generate the sync error signal when the start bit signal is not within the window pulse signal section. Noise canceling circuit, characterized in that configured to include.