JP2938594B2 - Transmission signal disturbance absorption circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission signal disturbance circuit. A digital signal transmitted by time division multiplexing may include a monitor signal indicating a state change in addition to data indicating information. For example, a signal on a transmission line connecting a remote concentrator and a switch constituting the switch system corresponds to the signal.

[0002] When an erroneous signal is transmitted to such a signal due to disturbance due to various causes, a serious effect is exerted on a control operation, so that a method for error detection has conventionally been adopted.

[0003]

2. Description of the Related Art FIG. 4 is an explanatory diagram of a conventional switching system, FIG. 5 is a configuration diagram of a conventional example 1, and FIG. In FIG. 4, 40 is a telephone, 41 is a concentrator, 4
2 is a transmission line, 43 is an exchange, and 44 is a frame of a signal on the transmission line. The concentrator 41 concentrates the subscriber lines of many analog telephones 40. The concentrator converts the analog and digital signals to each other, and the digitized voice is allocated to a predetermined number of time slots in the frame, time-division multiplexed, and transmitted through a high-speed transmission line such as an optical cable. The configuration of this frame is shown as a frame configuration on the lower side of FIG. In this frame, in addition to digital signals such as voices of a plurality of (concentrated) subscribers, states of the subscribers and various parts of the concentrator (on-hook / off-hook, on / off of a DC dial signal transmitted by the subscriber).
A plurality of signals (hereinafter, referred to as monitoring signals) representing an OFF state, power supply ON / OFF device failure information of the line concentrator, and the like are transmitted to the exchange side for each frame (or in a multi-frame configuration).

Such a monitoring signal lasts longer (for example, several milliseconds to several milliseconds) than a frame period (for example, 125 microseconds), and is a binary signal (for example, a binary signal) representing the state of each frame. “L” level or “H” level) is sampled and transmitted. Based on such a monitoring signal, the exchange detects the state of each part of the remote concentrator and performs a control operation corresponding thereto. However, such a signal is disturbed due to a change in the physical state of the transmission line (for example, the connection state between the optical cable and each device is instantaneously deteriorated by an impact or the like), and an erroneous signal is transmitted. In some cases.

A method conventionally used to cope with such a signal disturbance will be described. FIG. 5 is a block diagram of the first conventional example. In this configuration, a method of absorbing signal disturbance by majority logic is adopted. When a signal is transmitted from the driver 51 of the transmission side 50 in FIG. 5, the reception side 52 receives the signal at the receiver 53, and the separation circuit (DMPX: demultiplexer) 54 corresponds to the data (each bit) representing the respective states. Majority protection circuit 55-0 provided as
To 55-n. Each majority protection circuit 55-0 to 5
In 5-n, a memory for storing data to be input for each frame is provided, and when data for a plurality of frames (for example, three frames) is input, the data is output using majority logic. For example, data for three frames is “1”,
If "1" or "0", "1" is output by 2/3 majority decision.

According to another method, a parity or CRC (Cyclic Redundancy Check) operation or the like is performed on data of a frame on the transmission side, and if an error is found in the operation, processing such as discarding a signal in the frame is performed. Things. FIG. 6 shows a configuration of the second conventional example, which shows a configuration using a CRC operation.

The operation of FIG. 6 will be described. The CRC code generator (CRCG) performs a CRC operation on an input signal on the transmitting side 60, and the operation result (residue obtained at the end of the operation) is output to the multiplexer MPX as a CRC code. input. A frame composed of a signal and a CRC code (the last part) is output from the MPX as shown in the figure, and transmitted from the driver DR. When it reaches the receiving side 61 via the transmission path, it is received by the receiver RV. The received signal is a delay circuit D
L, while the CRC check unit CHC-CHK
In, a check is performed by a CRC operation. If there is no error in this check, the gate G is driven on to pass the signal output from the delay circuit DL, and if an error is detected, the gate G is driven off to inhibit the signal from passing.

[0008]

The two methods of the prior art are generally employed in a device premised on long-distance transmission. However, a large number of buffers are required, and the circuit configuration becomes complicated. There is a problem that it is necessary to delay the signal. Further, the method of the conventional example 1 is used for intra-station transmission and signal transmission between apparatuses. However, when the number of target signals increases, a protection circuit including a memory needs to be added. there were. Further, in the case of the prior art example 1, it is considered that the disturbance of the signal can be absorbed by taking at most 2/3 majority with respect to the bit error of the transmission line. However,
If a transmission line disconnection or transmission line interface failure / power interruption occurs, the transmission line interface circuit itself is in a transient operation state, so the signal disturbance time involved is long and the signal error state is random. Can be high. In addition, if there are multiple target signals, an independent protection circuit is provided for each signal as protection against signal disturbance in the transmission line, etc. There was a disadvantage that the scale became large.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a disturbance absorption circuit for a signal which has less deterioration in protection characteristics without increasing the amount of hardware for a plurality of signals.

[0010]

FIG. 1 is a basic configuration diagram of the present invention. FIG. , 10 is a receiving circuit, 11
Is a serial-parallel conversion circuit, 12 is an OR circuit, 13 is a continuous monitoring circuit, 14 is a signal extraction unit, and 15 is a gate circuit.

According to the present invention, a plurality of signals to be protected are ORed, and a plurality of extracted signals to be protected are output when the OR output exceeds a threshold set longer than a normal disturbance time. Things.

[0012]

Operation FIG. The receiving circuit 10 shown in FIG.
Is received and input. In this frame configuration, a plurality of (1 bit each) target signals to be protected from signal disturbance are represented by B.I. Is a serial signal (multiplex signal) composed of many bits as shown in FIG. The signal output from the receiving circuit 10 is converted into a parallel signal in the serial-parallel conversion circuit 11. This parallel signal is input to the OR circuit 12 to be ORed, and the output is output to the continuous monitoring circuit 1.
Enter 3 The continuation monitoring circuit 13 determines that the output signal of the OR circuit is shorter than the time during which a significant state such as a fault or a state change continues (duration of a signal that can be detected as meaningful), but is shorter than the general disturbance time. It monitors whether it continues for a long preset time, and if it exceeds the set time, generates an output to drive the gate circuit 15 ON, and the signal at that time held in the signal extracting unit 14 is output. Is displayed.

The set time set in the continuation monitoring circuit 13 is set to a time corresponding to a large number of frame periods, and the OR output of a plurality of target signals set in the serial / parallel conversion circuit 11 for each frame is set. Even if there is a disturbance signal in
Since the disturbance signal disappears within the set time, the disturbance signal
5 is not output.

[0014]

FIG. 2 is a block diagram of an embodiment, and FIG. 3 is an operation example of the embodiment. A. of FIG. In the figure, reference numeral 20 denotes an optical / electrical conversion unit (indicated by O / E), 21 denotes a serial-parallel conversion circuit, 22 denotes a register circuit, 23 denotes an OR circuit, 24 denotes a counting circuit, 25 denotes a comparison circuit, and 26 denotes a threshold setting circuit. , 27 are gate circuits, 2
8 is a timing circuit.

FIG. 2 shows a frame configuration on the transmission path, and bits A to N are arranged at the rear of the frame as a plurality of pieces of failure notification information which are objects of the present invention.

From the transmitting side (not shown) of the opposing device connected via a transmission line (optical line), B.B. The failure information of the opposing device is transmitted in the format shown in FIG. On the receiving side, the transmission path signal is converted into an electric signal by the optical-to-electrical conversion unit 20, and the target failure notification information is sequentially converted into a parallel signal by the serial-to-parallel conversion circuit 21 using the clock signal (extracted from the received signal) as a synchronization input. When the timing circuit 28 generates an output corresponding to the frame signal, the register circuit 22 stores the parallel signal of the serial-parallel conversion circuit 21. The contents of the register circuit 22 are stored and updated for each frame time unit. Each bit output of the register circuit 22 is input to the OR circuit 23, and the output of the OR is counted by the counting circuit 24.
Output to From the OR circuit 23, if there is an "H" signal (a state signal indicating a failure) even if the failure notification information contains at least one bit indicating a failure, the counting circuit 24
Is supplied to the counter circuit 24, and if all outputs of the register circuit 22 are "L", "L" is supplied to the counting circuit 24.

The counting circuit 24 inputs the output signal from the OR circuit 23 to a counting control terminal (indicated by C), makes the counting possible when an "H" signal is inputted, and counts when the "L" signal is inputted. Clear (reset) the value. Counting circuit 24
Inputs the output periodically generated from the timing circuit 28 to a count input terminal (indicated by IN) and counts. The timing circuit 28 receives a frame signal (one pulse generated for each frame) supplied from the optical-electrical conversion unit 20 and generates an output for each frame or for a predetermined number of frames. Therefore, the counting circuit 24 counts the pulses generated at predetermined intervals from the timing circuit 28 during the period when the OR circuit 23 continuously outputs the "H" signal. The count value of the counting circuit 24 is supplied to a comparison circuit 25, and is compared with a threshold value input from a threshold value setting circuit 26.

In the comparison circuit 25, when the numerical value of the counting circuit 24 exceeds the threshold value, an "H" output is generated, and each gate circuit 27 which receives the output of each of a plurality of bits of the register circuit 22 as an input is turned on. . Thereby, each bit signal of the register circuit 22 is output from each gate circuit 27 as a signal display. This threshold is longer than the disturbance duration,
In addition, a value (T) that is shorter than the significant state duration time is selected.

In the operation example shown in FIG. The case (1) indicates that there is no disturbance. Since the significant state continuation time of the signal A is longer than the disturbance continuation time, the state continuation of the signal obtained by taking the logical sum of all the target signals is determined by the counting circuit 2.
4. Since the output of the OR circuit exceeds the threshold value T as monitored by the comparison circuit 25, the significant signal A is output from the gate circuit 27.

In contrast, FIG. Is a case where disturbance occurs due to an instantaneous disconnection of a transmission path, a failure in a transmission path interface part, or the like. In this example, each of the signals A to N is intermittent due to the disturbance, but the output of the logical sum ends in the disturbance duration time (shorter than T). Therefore, in the embodiment of FIG. Without reaching the threshold value T, the gate circuit 27 is kept in the prohibited (off) state, and no disturbance signal is output.

[0021]

According to the present invention, the protection circuit for absorbing the disturbance of a plurality of signals without deteriorating the protection characteristics can be simplified in construction, and the size can be reduced.

[Brief description of the drawings]

FIG. 1 is a basic configuration diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment.

FIG. 3 is an operation example of the embodiment.

FIG. 4 is an explanatory diagram of a conventional switching system.

FIG. 5 is a configuration diagram of Conventional Example 1.

FIG. 6 is a configuration diagram of a second conventional example.

[Description of Signs] 10 receiving circuit 11 serial-parallel conversion circuit 12 OR circuit 13 continuous monitoring circuit 14 signal extraction unit 15 gate circuit

Claims (3)

(57) [Claims] 1. A disturbance absorption circuit for a transmission signal for protecting a signal received via a transmission line, comprising: a logical sum circuit for calculating a logical sum of a plurality of bit signals to be protected consisting of a large number of bits in a frame configuration ; When "1" is input from the OR circuit, the timing signal
+1 is counted by the signal, and "0" is output from the OR circuit.
The ratio of comparing but the counting circuit for clearing the count value is input, and the value with a preset threshold value of the counter circuit
And that the value of the counting circuit exceeds the threshold value.
The output generated from the comparison circuit represents the plurality of bits.
Disturbance absorbing circuit of the transmission signal, characterized in Rukoto a gate circuit which outputs the door signal. 2. The method according to claim 1, wherein The duration of the output of the OR circuit is monitored.
Is longer than the disturbance duration and longer than the significant state duration
Output of the multi-bit signal is prohibited when it is short
A disturbance absorption circuit for a transmission signal. 3. The method according to claim 1, wherein The preset threshold value compared by the comparison circuit is a disturbance threshold.
Longer than the duration and shorter than the significant state duration
Corresponding to the disturbance absorption of the transmission signal.
Road.