KR890004509A - Loopback Circuits for Analog and Digital Signals - Google Patents

Loopback Circuits for Analog and Digital Signals Download PDF

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Publication number
KR890004509A
KR890004509A KR870009186A KR870009186A KR890004509A KR 890004509 A KR890004509 A KR 890004509A KR 870009186 A KR870009186 A KR 870009186A KR 870009186 A KR870009186 A KR 870009186A KR 890004509 A KR890004509 A KR 890004509A
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KR
South Korea
Prior art keywords
signal
loopback
analog
determining unit
state determining
Prior art date
Application number
KR870009186A
Other languages
Korean (ko)
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KR900001820B1 (en
Inventor
백상엽
Original Assignee
강진구
삼성반도체통신 주식회사
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Publication date
Application filed by 강진구, 삼성반도체통신 주식회사 filed Critical 강진구
Priority to KR1019870009186A priority Critical patent/KR900001820B1/en
Publication of KR890004509A publication Critical patent/KR890004509A/en
Application granted granted Critical
Publication of KR900001820B1 publication Critical patent/KR900001820B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Interface Circuits In Exchanges (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

내용 없음.No content.

Description

아날로그와 디지탈 신호의 루프백 회로Loopback Circuits for Analog and Digital Signals

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명의 펄스코드 변조 암호 복호기의 회로 계통도.3 is a circuit diagram of a pulse code modulation crypto decoder of the present invention.

제4도는 제3도의 실시예 기능 블록도.4 is a functional block diagram of the embodiment of FIG.

제5도는 본 발명의 실시예 기능 블록도에서 A블록-F블록 까지의 구체화된 실시예 회로도.5 is a detailed embodiment circuit diagram from the embodiment functional block diagram to the block A-F of the present invention.

Claims (2)

디지탈 신호(⑨), 루프백 신호(⑩), 아날로그 신호(⑪)의 유무를 감지하여 판단하는 제1신호 상태 결정부(A), 제2신호 상태 결정부(B), 제3신호 상태 결정부(C)와, 상기 제1신호 상태 결정부(A)와 제3신호 상태 결정부(C)로부터 판단된 상태에 따라 해당 논리를 발생시키는 제1,2, 출력논리 발생부(D),(E)와, 상기 제1,2 출력 논리 발생부(D),(E)의 출력논리와, 제2신호 상태 결정부(B)의 출력 논리등의 입력상태에 따라 당해 루프백 신호의 종류를 선택하는 루프백 종류 선택부(F)와를 연결 구성하고, 상기 루프백 종류 선택부(F)에 각각의 아날로그 신호를 루프백시키는 아날로그 루프백부(G)와 디지탈 신호를 루프백시키는 디지탈 루프백부(H)와를 연결 구성 하여서 됨을 특징으로 하는 아날로그와 디지탈 신호의 루프백 회로.First signal state determining unit (A), second signal state determining unit (B), and third signal state determining unit for detecting and determining the presence or absence of a digital signal (⑨), a loopback signal (i), and an analog signal (i). (C) and the first and second output logic generating units (D) for generating the logic in accordance with the states determined by the first signal state determining unit (A) and the third signal state determining unit (C), ( The type of the loopback signal is selected according to E), the output logic of the first and second output logic generating units (D) and (E), and the input state of the output logic of the second signal state determining unit (B). A loopback type selector (F), and an analog loopback unit (G) for looping back each analog signal and a digital loopback unit (H) for looping back a digital signal to the loopback type selector (F). Loopback circuit for analog and digital signals, characterized in that the 제1항에 있어서, 송신 여파기(3)의 앞단에 전자스위치(ES)를 연결 구성하여 아날로그 신호를 선택하고, 또한 D/A컨버터(2)의 앞단에 전자스위치(20)로서 디지탈 신호를 선택하도록 하는 아날로그와, 디지탈 신호의 루프백 회로.The electronic switch (ES) is connected to the front end of the transmission filter (3) to select an analog signal, and the digital signal is selected as the electronic switch (20) in front of the D / A converter (2). Loopback circuit of analog and digital signal to let. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019870009186A 1987-08-21 1987-08-21 The loop back circuit of analog and digital signal KR900001820B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019870009186A KR900001820B1 (en) 1987-08-21 1987-08-21 The loop back circuit of analog and digital signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019870009186A KR900001820B1 (en) 1987-08-21 1987-08-21 The loop back circuit of analog and digital signal

Publications (2)

Publication Number Publication Date
KR890004509A true KR890004509A (en) 1989-04-22
KR900001820B1 KR900001820B1 (en) 1990-03-24

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ID=19263909

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870009186A KR900001820B1 (en) 1987-08-21 1987-08-21 The loop back circuit of analog and digital signal

Country Status (1)

Country Link
KR (1) KR900001820B1 (en)

Also Published As

Publication number Publication date
KR900001820B1 (en) 1990-03-24

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