KR890702143A - 고성능 로우핀 카운터버스 인터페이스 - Google Patents

고성능 로우핀 카운터버스 인터페이스

Info

Publication number
KR890702143A
KR890702143A KR1019880701758A KR880701758A KR890702143A KR 890702143 A KR890702143 A KR 890702143A KR 1019880701758 A KR1019880701758 A KR 1019880701758A KR 880701758 A KR880701758 A KR 880701758A KR 890702143 A KR890702143 A KR 890702143A
Authority
KR
South Korea
Prior art keywords
counterbus
pin
interface
performance low
performance
Prior art date
Application number
KR1019880701758A
Other languages
English (en)
Inventor
디.도날드선 다렐
쥬니어 리차드 비.길렛
디.윌리암스 더글라스
Original Assignee
디지탈 이큅먼트 코오포레이숀
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 디지탈 이큅먼트 코오포레이숀 filed Critical 디지탈 이큅먼트 코오포레이숀
Publication of KR890702143A publication Critical patent/KR890702143A/ko

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
KR1019880701758A 1987-05-01 1988-12-29 고성능 로우핀 카운터버스 인터페이스 KR890702143A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/044,467 US4829515A (en) 1987-05-01 1987-05-01 High performance low pin count bus interface
PCT/US1988/001360 WO1988008583A1 (en) 1987-05-01 1988-04-22 High performance low pin count bus interface

Publications (1)

Publication Number Publication Date
KR890702143A true KR890702143A (ko) 1989-12-23

Family

ID=21932546

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880701758A KR890702143A (ko) 1987-05-01 1988-12-29 고성능 로우핀 카운터버스 인터페이스

Country Status (8)

Country Link
US (1) US4829515A (ko)
EP (1) EP0312575B1 (ko)
JP (1) JPH0677248B2 (ko)
KR (1) KR890702143A (ko)
AU (1) AU597492B2 (ko)
CA (1) CA1297991C (ko)
DE (1) DE3883693T2 (ko)
WO (1) WO1988008583A1 (ko)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5418935A (en) * 1990-04-30 1995-05-23 Unisys Corporation Apparatus for preventing double drive occurrences on a common bus by delaying enablement of one driver after indication of disablement to other driver is received
KR940000377B1 (ko) * 1990-05-10 1994-01-19 캐논 가부시끼가이샤 Cpu를 사용한 데이타 처리장치
US5305319A (en) * 1991-01-31 1994-04-19 Chips And Technologies, Inc. FIFO for coupling asynchronous channels
US5608883A (en) * 1993-02-01 1997-03-04 Digital Equipment Corporation Adapter for interconnecting single-ended and differential SCSI buses to prevent `busy` or `wired-or` glitches from being passed from one bus to the other
US6493407B1 (en) * 1997-05-27 2002-12-10 Fusion Micromedia Corporation Synchronous latching bus arrangement for interfacing discrete and/or integrated modules in a digital system and associated method
US6222413B1 (en) * 1999-03-16 2001-04-24 International Business Machines Corporation Receiver assisted net driver circuit
DE19961727A1 (de) * 1999-12-21 2001-07-05 Micronas Gmbh Schaltungsanordnung mit einer Datenübertragungsvorrichtung
US6977979B1 (en) 2000-08-31 2005-12-20 Hewlett-Packard Development Company, L.P. Enhanced clock forwarding data recovery
US20040268143A1 (en) * 2003-06-30 2004-12-30 Poisner David I. Trusted input for mobile platform transactions
US20050044408A1 (en) * 2003-08-18 2005-02-24 Bajikar Sundeep M. Low pin count docking architecture for a trusted platform
US7697444B2 (en) * 2007-09-07 2010-04-13 Fujitsu Limited Testing a circuit using a shared bandwidth test bus
US20090313404A1 (en) * 2008-06-16 2009-12-17 Meng-Nan Tsou Apparatus for accessing conditional access device by utilizing specific communication interface and method thereof
US11497320B2 (en) 2020-08-01 2022-11-15 Layla Sleep, Inc. Dual firmness spring mattress

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3585399A (en) * 1968-10-28 1971-06-15 Honeywell Inc A two impedance branch termination network for interconnecting two systems for bidirectional transmission
US4409671A (en) * 1978-09-05 1983-10-11 Motorola, Inc. Data processor having single clock pin
JPS6037996B2 (ja) * 1980-02-20 1985-08-29 沖電気工業株式会社 バツフア回路
US4347600A (en) * 1980-06-03 1982-08-31 Rockwell International Corporation Monitored muldem with self test of the monitor
US4376998A (en) * 1980-06-03 1983-03-15 Rockwell International Corporation Muldem with monitor comparing means which accepts different data rates
JPS6347105Y2 (ko) * 1981-01-13 1988-12-06
JPS5833739A (ja) * 1981-08-21 1983-02-28 Toshiba Corp バスライン駆動回路
US4414480A (en) * 1981-12-17 1983-11-08 Storage Technology Partners CMOS Circuit using transmission line interconnections
US4567561A (en) * 1981-12-24 1986-01-28 International Business Machines Corp. Large scale integration data processor signal transfer mechanism
US4471243A (en) * 1982-07-26 1984-09-11 Rca Corporation Bidirectional interface
IT1210945B (it) * 1982-10-22 1989-09-29 Ates Componenti Elettron Circuito di interfaccia per generatori di segnali di sincronismo a due fasi nonsovrapposte.
JPS59133624A (ja) * 1983-01-20 1984-08-01 Sharp Corp インタ−フエイス方式
US4623886A (en) * 1983-01-21 1986-11-18 E-Systems, Inc. Prioritized data packet communication
US4542305A (en) * 1983-02-22 1985-09-17 Signetics Corporation Impedance buffer with reduced settling time
US4558237A (en) * 1984-03-30 1985-12-10 Honeywell Inc. Logic families interface circuit and having a CMOS latch for controlling hysteresis
JPS60252979A (ja) * 1984-05-30 1985-12-13 Oki Electric Ind Co Ltd Ｃｍｏｓ入出力回路
US4625126A (en) * 1984-06-29 1986-11-25 Zilog, Inc. Clock generator for providing non-overlapping clock signals
JPS60215266A (ja) * 1984-11-21 1985-10-28 Nec Corp 情報処理装置
JPS61195450A (ja) * 1985-02-25 1986-08-29 Fujitsu Ltd 共有レジスタのインタフエ−ス方式
JPS61239350A (ja) * 1985-04-16 1986-10-24 Nec Corp バス制御方式
US4719621A (en) * 1985-07-15 1988-01-12 Raytheon Company Packet fastbus
US4645947A (en) * 1985-12-17 1987-02-24 Intel Corporation Clock driver circuit
US4737953A (en) * 1986-08-04 1988-04-12 General Electric Company Local area network bridge

Also Published As

Publication number Publication date
AU597492B2 (en) 1990-05-31
EP0312575A1 (en) 1989-04-26
JPH0677248B2 (ja) 1994-09-28
DE3883693T2 (de) 1994-02-03
CA1297991C (en) 1992-03-24
EP0312575B1 (en) 1993-09-01
JPH02500549A (ja) 1990-02-22
DE3883693D1 (de) 1993-10-07
AU1713488A (en) 1988-12-02
US4829515A (en) 1989-05-09
WO1988008583A1 (en) 1988-11-03

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Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
LAPS Lapse due to unpaid annual fee