KR890702115A - How to avoid resistor interference - Google Patents

How to avoid resistor interference

Info

Publication number
KR890702115A
KR890702115A KR1019890701233A KR890701233A KR890702115A KR 890702115 A KR890702115 A KR 890702115A KR 1019890701233 A KR1019890701233 A KR 1019890701233A KR 890701233 A KR890701233 A KR 890701233A KR 890702115 A KR890702115 A KR 890702115A
Authority
KR
South Korea
Prior art keywords
code
interference
execution
execution code
internal
Prior art date
Application number
KR1019890701233A
Other languages
Korean (ko)
Other versions
KR920003495B1 (en
Inventor
다디시 오까모도
유우지 다니가와
야스히로 나까구라
Original Assignee
다니이 아끼오
마쓰시다 덴기 산교오 가부시기가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 다니이 아끼오, 마쓰시다 덴기 산교오 가부시기가이샤 filed Critical 다니이 아끼오
Publication of KR890702115A publication Critical patent/KR890702115A/en
Application granted granted Critical
Publication of KR920003495B1 publication Critical patent/KR920003495B1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution

Abstract

내용 없음No content

Description

레지스터 간섭 방지방법How to avoid resistor interference

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 종전의 5단인 파이프라인 처리기의 구성 개략도, 제2도 및 제3도는 동 처리기의 동작 타이밍 챠아트도.1 is a schematic view of the structure of a conventional five stage pipeline processor, and FIGS. 2 and 3 are operation timing charts of the processor.

Claims (1)

적어도 실행코오드페치, 실행코오드데코오드 및 레니스터간섭을 수반하는 복수의 연산단계로 구성되어 있는 파이프라인 방식의 처리기에 있어서, 실행되는 실행코오드상에 상기한 복수의 연산단계에서의 레지스터 간섭을 보여주는 특정피일드를 마련하고, 상기한 실행코오드데코오드단계는, 상기한 레지스터간섭피일드를 참조하며, 그 패턴에 따라, 상기한 복수의 연산단계에 대하여, 해당하는 실행코오드에 대응하는 내부코오드이건, 또는 해당하는 실행코오드에 대응하는 내부코오드이건 또는 해당하는 실행코오드에 대응하는 내부코오드에 인계되어서 하나 또는 복수의 노오페레이숀의 내부코오드를 발생하는 것을 특징으로 하는 레지스터 간섭 방지방법.In a pipelined processor consisting of at least an execution code fetch, an execution code decoder, and a plurality of operation steps involving the interference of the canisters, the processor exhibiting register interference at the execution codes described above is executed. The specific code is provided, and the execution code decoding step refers to the register interference feed, and according to the pattern, the internal code corresponding to the execution code corresponding to the corresponding execution code may be Or an internal code corresponding to the corresponding execution code or inherited by an internal code corresponding to the corresponding execution code to generate one or more internal codes of no persistence. ※참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is to be disclosed based on the initial application.
KR1019890701233A 1987-11-02 1988-10-31 Register inteference preventing method KR920003495B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP62277623A JPH01119829A (en) 1987-11-02 1987-11-02 Register interference preventing method
JP87-277623 1987-11-02
PCT/JP1988/001111 WO1989004518A1 (en) 1987-11-02 1988-10-31 Register interference preventing method

Publications (2)

Publication Number Publication Date
KR890702115A true KR890702115A (en) 1989-12-22
KR920003495B1 KR920003495B1 (en) 1992-05-01

Family

ID=17586001

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890701233A KR920003495B1 (en) 1987-11-02 1988-10-31 Register inteference preventing method

Country Status (3)

Country Link
JP (1) JPH01119829A (en)
KR (1) KR920003495B1 (en)
WO (1) WO1989004518A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5915083A (en) * 1997-02-28 1999-06-22 Vlsi Technology, Inc. Smart debug interface circuit for efficiently for debugging a software application for a programmable digital processor device
US6370638B1 (en) 1997-11-21 2002-04-09 Matsushita Electric Industrial Co., Ltd. Apparatus and method of computer program control in computer systems using pipeline processing

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53108254A (en) * 1977-03-02 1978-09-20 Nec Corp Information processor
JPS5466048A (en) * 1977-11-07 1979-05-28 Hitachi Ltd Information processor

Also Published As

Publication number Publication date
KR920003495B1 (en) 1992-05-01
WO1989004518A1 (en) 1989-05-18
JPH01119829A (en) 1989-05-11

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