JPS6488854A - Data processor - Google Patents

Abstract

PURPOSE:To extend an address space without dividing a superviser area and a user area and to attain address designation directly with the address of a small bit length even for the superviser area by executing the extension of the address space in two directions. CONSTITUTION:The instruction of an address value, which is expressed in a binary number with a code by the complement expression of two, is fetched from a memory 10 in an instruction fetch part 1 and decoded in a decode part 2. Then, a decode result is delivered to an instruction execution control part 3. The control part 3 stores a literal value, which is obtained from the decode result, to a literal register 15. Then, the entry address of a microprogram routine, which is stored in a micro-ROM 7 and outputs a value to code-extend the literal value to an address bus 8 as the address, is set to a microprogram counter 6 and a micro-instruction is read. When a ring value is '1', a user mode is shown and when the MSB of an address output register 13 is '1' and a negative address value is obtained, it is judged that the task of the user mode tries to access the memory area of a superviser mode.