JPH03194621A - Data processor - Google Patents

Abstract

PURPOSE:To freely set the address designation value and immediate data of an arbitrary length without enlarging an instruction decoder by giving an instruction with a bit field showing continuity with the other instruction code in an instruction code. CONSTITUTION:The instruction code consists of an operation code field OP in which an operation code is incorporated the bit field C showing the continuity of the instruction and a designation field DI in which a displacement value or immediate data is incorporated. When the displacement value and immediate data are small and they are incorporated in the designation field D, the bit field C is set to zero. When they are unable to be incorporated in the designation field, the bit field C is set to '1', high-order 16 bits of the displacement value and immediate data are incorporated in the designation field DI. Then, the bit field is set to '0' by the subsequent instruction and low-order 16 bits are incorporated in the designation field.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a technique that is particularly effective when applied to program control techniques, instruction formats for computers or microprocessors, and methods for configuring instruction systems.
For example, it relates to a technique that is effective when used in the instruction format of a RISC type processor.

[Prior Art] In recent years, a RISC type processor that supports only simple instructions by hardware has been proposed, in contrast to the conventional Cl5C type processor which has a complicated instruction system.

Conventionally proposed RISC processors generally have 3
Adopts a 2-bit fixed length instruction format (Cypres
s Semlconductor, RISCFam
ily Users Guide (1988) p.
p2-18 to 2-20).

[Problems to be Solved by the Invention] In the case of a processor with a 32-bit fixed-length instruction format, not only data but also addresses handled are 32-bits long. However, since the instruction code requires a field containing at least several bits of operation code,
A RISC processor with a fixed-length instruction format has a problem in that a 32-bit immediate value set instruction or a branch instruction with a 32-bit branch destination address cannot be expressed in one instruction.

Therefore, in a RISC processor such as the conventional 5PARC chip, the branch destination address of a subroutine call instruction (Call instruction) is 30 bits, and the branch destination address of a conditional branch instruction (B
The branch destination address of the RANCH instruction is 22 bits, and the immediate value data of the immediate value set instruction is divided into two parts.
The lower 13 bits are entered in the ad lmm1diate command to set immediate value data.

As described above, in the conventional fixed-length instruction format RISC processor, a branch destination address cannot be freely set in a branch instruction or a subroutine call instruction, and two types of instructions must be used for immediate value sets. Therefore,
There was a problem in that the instruction decoder was also complicated.

An object of the present invention is to enable a fixed-length instruction format RISC processor to freely set an address specification value (displacement amount) or immediate value data of any length using only one type of instruction without increasing the scale of the instruction decoder. The purpose is to do so.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

In other words, in fixed-length instruction format processors, there is a bit in an instruction that sets an address or immediate data, such as a branch instruction, subroutine call instruction, or immediate value set instruction, that specifies that multiple consecutive instructions are treated as a single instruction. A field is provided, and the processor controls a multiplexer or the like based on the contents of this bit field to set the bit string in the instruction in the upper or lower part of the pre-buffer register connected to the program counter and the general-purpose register.

[Operation] According to the above-mentioned means, branch addresses and immediate data that cannot fit into one instruction are divided into two and placed into two instructions of the same type, and a bit field indicating continuity is set. By keeping the commands of the same type,
Addresses and immediate data of arbitrary length can be freely set, and there is no need to change the instruction decoder.

[Embodiment] FIG. 1 shows an example of an instruction format of a fixed-length instruction format RISC processor according to the present invention.

That is, the instruction of this embodiment includes an operation code field OP in which an operation code is entered, a bit field C (hereinafter referred to as C bit) indicating continuity of the instruction,
It is composed of a designated field DI into which displacement or immediate value data (immediate value) is entered.

The length of the opcode field OP varies depending on the number of instructions prepared for the processor, etc. Further, the operation code field OP may contain the number of a register serving as a destination and the setting conditions of a conditional instruction.

Next, an example of the configuration of a processor that decodes and executes instructions in the above format will be described with reference to FIG.

In FIG. 2, l is an instruction register from which instructions are fetched from the program memory via a data bus, and 2 is an arithmetic logic unit ALU and a register group REG in an execution unit 3 that decodes the instructions fetched into the instruction register l. An instruction decoder that forms control signals for the

Further, 4 is a program counter into which an instruction fetch address is entered, and 5 is a data buffer that temporarily holds data when data is exchanged between the external data bus and the execution unit 3.

In this embodiment, a pre-buffer register 6 that can temporarily hold the displacement value or immediate value in the specified field DI of the instruction code fetched into the instruction register l, and a multiplexer 7 are connected to the instruction register l and the program. It is provided between the counter 4 and the execution unit 3. The pre-buffer register 6 has a width twice (for example, 32 bits) as the designated field DI, and is designed to transfer the set displacement value to the program counter 4 and the immediate value to the register in the execution unit 3. It is composed of Further, the multiplexer 7 transfers the value in the specified field DI according to the contents of the C bit in the instruction code to the upper side of the pre-buffer register 6 when the C bit is [l], and to the upper side of the pre-buffer register 6 when the C bit is [0]. ”, the configuration is such that the signal is supplied to the lower side of the pre-buffer register 6.

Therefore, if the number of bits in the displacement value or immediate eight value is small and the length is such that it can be entered in the designated field DI in the instruction at once, the C bit is set to "Use the OJ instruction. On the other hand, the displacement value If the number of bits in the or immediate value is too large to fit in the specified field DI in one instruction, first use an instruction with the C bit rlJ to write the displacement value or immediate value in the specified field DI. Top 16 immediate values
bit, and then use the same type of instruction to input only the C bit.
Using the OJ command, the lower 16 bits of the displacement value and immediate value are placed in the designated field DI.

In this way, the formats of 32-bit instructions and 16-bit instructions can be unified, and the structure of the decoder does not become complicated.

In the above embodiment, the length of the pre-buffer register 6 is twice the number of bits of the specified field DI in the instruction, but it is also possible to make the pre-buffer register 6 four times as long as the specified field. You can also leave it there. In that case, for example, while the displacement value or immediate value continues, the C bit is "0" when using the "lJ" instruction and inputting the lowest (or highest) value. It is sufficient to use the same command.

Furthermore, when the length of the pre-buffer register 6 is three times or more the designated field DI in the instruction code, two or more C bits may be provided. In that case, it is preferable to control the multiplexer 7 with a signal obtained by decoding the C bit by the instruction decoder 2 so as to input the displacement value or immediate value into the pre-buffer register 6 in order from the top.

In addition, in the above embodiment, instructions with displacement and immediate value set instructions were explained as examples, but in addition to displacement and immediate value data, in indirect addressing instructions and direct addressing instructions, an address value is stored in the instruction (designated field DI). It can also be applied to inputting register numbers.

Furthermore, the instruction code is not limited to a fixed length of 32 bits,
It may be 16 bits. In that case, the size of the designated field DI will be about half, about 8 bits.

As explained above, in the fixed-length instruction format processor, the above embodiment combines multiple consecutive instructions into a single instruction in an instruction that sets an address or immediate data, such as a branch instruction, subroutine call instruction, or immediate value set instruction. A bit field is provided that specifies that it should be treated as an instruction, and the processor controls a multiplexer etc. based on the contents of this bit field to convert the bit string in the instruction code,
Since it is set in the upper or lower part of the pre-buffer register connected to the program counter and general-purpose registers, branch addresses and immediate data that cannot fit into an instruction can be divided into two and stored in two identical types. By putting it in an instruction and setting a bit field that indicates continuity, you can freely set addresses and immediate data of any length using only instructions of the same type, and the instruction decoder also This has the effect that there is no need to change it.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. Displacement values and immediate values are stored in the program counter and general-purpose registers via a pre-buffer, but the pre-buffer is omitted and they are directly specified and stored in the upper or lower part of the program counter or general-purpose register. Good too.

The above explanation will mainly focus on the fixed-length instruction format R
Although the present invention has been described as being applied to an ISC type processor, the present invention is not limited thereto, and can be used in general program control type computers such as a C15C type processor.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, in a fixed-length instruction format RISC processor, address designation values (displacement amounts) and immediate data of any length can be freely set using only one type of instruction without increasing the scale of the instruction decoder.

[Brief explanation of drawings]

FIG. 1 is a format configuration diagram showing an example of the instruction format of a fixed-length instruction format RISC processor according to the present invention, and FIG. 2 is a block diagram showing an embodiment of the fixed-length instruction format RISC processor according to the present invention. be. 1...Instruction register, 2...Instruction decoder, 3
...Execution unit, 7...Multiplexer (transfer switching means).

Claims (1)

[Scope of Claims] 1. A data processing device in a fixed-length instruction format, characterized in that the instruction code has an instruction having a bit field indicating continuity with other instruction codes. 2. The data processing device according to claim 1, wherein the instruction code is composed of the bit feed, a field containing an operation code, and a designation field containing address displacement amount or immediate value data. 3. The data processing apparatus according to claim 2, further comprising transfer switching means for transferring the bit string in the designated field to a predetermined position in a transfer destination register according to the contents of the bit field.