KR890015392A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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Publication number
KR890015392A
KR890015392A KR1019880002296A KR880002296A KR890015392A KR 890015392 A KR890015392 A KR 890015392A KR 1019880002296 A KR1019880002296 A KR 1019880002296A KR 880002296 A KR880002296 A KR 880002296A KR 890015392 A KR890015392 A KR 890015392A
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KR
South Korea
Prior art keywords
metal film
semiconductor substrate
semiconductor device
arc discharge
voltage
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Application number
KR1019880002296A
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Korean (ko)
Inventor
고지로오 스가네
미끼오 다까기
Original Assignee
다기 미끼오
가부시끼가이샤 후렌드 딕크 겐뀨우쇼
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Application filed by 다기 미끼오, 가부시끼가이샤 후렌드 딕크 겐뀨우쇼 filed Critical 다기 미끼오
Publication of KR890015392A publication Critical patent/KR890015392A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

내용 없음No content

Description

반도체장치 제조방법Semiconductor device manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 2 도는 본 발명에 따라 용융된 후의 알루미늄막의 단면도, 제 3 도는 알루미늄의 리플로우를 실행하는 아크방전 장치의 단면도, 제 4 도는 제 3 도의 장치에 사용되는 전극배열의 각예의 측면도.2 is a sectional view of an aluminum film after melting in accordance with the present invention, FIG. 3 is a sectional view of an arc discharge device for performing reflow of aluminum, and FIG. 4 is a side view of each example of an electrode array used in the device of FIG.

Claims (4)

반도체 기판의 표면에 피복하며 접촉창을 갖는 절연막을 갖춘 반도체 기판을 예비 가열하는 단계 ; 상기 절연막을 피복하기 위하여 금속막을 형성하는 단계 ; 비활성 가스의 분위기에서 상기 금속막의 적어도 표면부를 용융하기 위하여 상기 금속막을 아크방전에 노출하는 단계 ; 및 상기 반도체 장치의 배선층을 형성하기 위하여 상기 금속막을 패터닝하는 단계로 구성되는 것을 특징으로 하는 반도체 장치 제조방법.Preheating the semiconductor substrate having an insulating film covering the surface of the semiconductor substrate and having a contact window; Forming a metal film to cover the insulating film; Exposing the metal film to arc discharge to melt at least a surface portion of the metal film in an atmosphere of inert gas; And patterning the metal film to form a wiring layer of the semiconductor device. 제 1 항에 있어서, 상기 금속막이 접지 전위에 접속되는 것을 특징으로 하는 반도체 장치 제조방법.A method according to claim 1, wherein the metal film is connected to a ground potential. 반도체 기판의 표면을 피복하며 접촉창을 갖춘 반도체기판을 예비 가열하는 단계 ; 상기 절연막의 표면을 피복하기 위하여 금속막을 형성하는 단계 ; 비활성 가스로 채워진 엔클로우저 내에 상기 반도체 기판을 놓는 단계 ; 상기 기판의 상기 금속막위에 상기 금속막의 물질로 구성되는 전극을 놓는 단계 ; 상기 금속막의 적어도 표면부를 용융하기 위하여 상기 전극와 상기 금속막 사이에 아크 방전을 만들도록 고전압을 인가하는 단계 ; 및 상기 반도체 장치의 배선층을 형성하기 위하여 상기 금속막을 패터닝하는 단계로 구성되는 것을 특징으로 하는 반도체 장치 제조방법.Preheating the semiconductor substrate having a contact window covering the surface of the semiconductor substrate; Forming a metal film to cover the surface of the insulating film; Placing the semiconductor substrate in an enclosure filled with an inert gas; Placing an electrode made of a material of the metal film on the metal film of the substrate; Applying a high voltage to create an arc discharge between the electrode and the metal film to melt at least a surface portion of the metal film; And patterning the metal film to form a wiring layer of the semiconductor device. 제 3 항에 있어서, 상기 고접압이 상기 아크방전을 안정화하기 위하여 교류 펄스 전압이 가해진 직류 전압인 것을 특징으로 하는 반도체 장치 제조방법.4. A method according to claim 3, wherein the high contact voltage is a direct current voltage to which an alternating pulse voltage is applied to stabilize the arc discharge. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019880002296A 1987-03-06 1988-03-05 Semiconductor device manufacturing method KR890015392A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP62050099A JPS63216972A (en) 1987-03-06 1987-03-06 Method for reflowing thin aluminum film
JP?62-050099 1987-03-06

Publications (1)

Publication Number Publication Date
KR890015392A true KR890015392A (en) 1989-10-30

Family

ID=12849625

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880002296A KR890015392A (en) 1987-03-06 1988-03-05 Semiconductor device manufacturing method

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JP (1) JPS63216972A (en)
KR (1) KR890015392A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2660040B2 (en) * 1989-02-01 1997-10-08 日本真空技術株式会社 Vacuum deposition method
EP0735577A3 (en) * 1994-12-14 1997-04-02 Applied Materials Inc Deposition process and apparatus therefor

Also Published As

Publication number Publication date
JPS63216972A (en) 1988-09-09

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