KR890006114A - 회로기판 - Google Patents

회로기판 Download PDF

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Publication number
KR890006114A
KR890006114A KR1019880010943A KR880010943A KR890006114A KR 890006114 A KR890006114 A KR 890006114A KR 1019880010943 A KR1019880010943 A KR 1019880010943A KR 880010943 A KR880010943 A KR 880010943A KR 890006114 A KR890006114 A KR 890006114A
Authority
KR
South Korea
Prior art keywords
circuit pattern
exposed
circuit board
electroless plating
metal lead
Prior art date
Application number
KR1019880010943A
Other languages
English (en)
Other versions
KR910007059B1 (ko
Inventor
다께시 사또
가쓰야 후까세
기요다까 시마다
히로후미 우찌다
Original Assignee
가와다니 유끼마로
신고오 덴기 고오교오 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가와다니 유끼마로, 신고오 덴기 고오교오 가부시끼가이샤 filed Critical 가와다니 유끼마로
Publication of KR890006114A publication Critical patent/KR890006114A/ko
Application granted granted Critical
Publication of KR910007059B1 publication Critical patent/KR910007059B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Chemically Coating (AREA)

Abstract

내용 없음

Description

회로기판
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 회로기판의 일예로서의 반도체 장치용 패키지의 단면도
제2도는 수지기체와 회로패턴부의 밀착상태를 나타낸 모식도
제3도는 전해동박의 단면의 모식도

Claims (1)

  1. 금속리드부의 일부가 노출되어 일체적으로 인서트성형 되어있는 수지기체의 표면이 물리적으로 거칠게 되어서 이 수지기체 표면에 입구측이 좁고 안쪽이 넓은 다수의 미세부가 형성되고, 이 미세부가 형성되어 있는 수지기체 표면상에 미세에 무전해 도금금속이 끼어들어가게 하여 회로패턴부가 형성되고, 이 회로패턴부가 상기 금속리드의 노출되어 있는 부분에 상기 무전해 도금에 의해서 전기적으로 도통되어 접속되어 있는 것을 특징으로 하는 회로기판.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880010943A 1987-09-04 1988-08-27 회로기판 KR910007059B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP87-222393 1987-09-04
JP62-222393 1987-09-04
JP62222393A JPS6464390A (en) 1987-09-04 1987-09-04 Circuit board

Publications (2)

Publication Number Publication Date
KR890006114A true KR890006114A (ko) 1989-05-18
KR910007059B1 KR910007059B1 (ko) 1991-09-16

Family

ID=16781664

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880010943A KR910007059B1 (ko) 1987-09-04 1988-08-27 회로기판

Country Status (2)

Country Link
JP (1) JPS6464390A (ko)
KR (1) KR910007059B1 (ko)

Also Published As

Publication number Publication date
JPS6464390A (en) 1989-03-10
KR910007059B1 (ko) 1991-09-16

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