KR880702004A - 타이밍신호 지연회로장치 - Google Patents

타이밍신호 지연회로장치

Info

Publication number
KR880702004A
KR880702004A KR1019880700135A KR880700135A KR880702004A KR 880702004 A KR880702004 A KR 880702004A KR 1019880700135 A KR1019880700135 A KR 1019880700135A KR 880700135 A KR880700135 A KR 880700135A KR 880702004 A KR880702004 A KR 880702004A
Authority
KR
South Korea
Prior art keywords
delay circuit
circuit device
timing signal
signal delay
timing
Prior art date
Application number
KR1019880700135A
Other languages
English (en)
Other versions
KR900008048B1 (ko
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of KR880702004A publication Critical patent/KR880702004A/ko
Application granted granted Critical
Publication of KR900008048B1 publication Critical patent/KR900008048B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/14—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31922—Timing generation or clock distribution
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00026—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
    • H03K2005/00045—Dc voltage control of a capacitor or of the coupling of a capacitor as a load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00234—Layout of the delay element using circuits having two logic levels
    • H03K2005/00267—Layout of the delay element using circuits having two logic levels using D/A or A/D converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/0028—Layout of the delay element using varicaps, e.g. gate capacity of a FET with specially defined threshold, as delaying capacitors

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Pulse Circuits (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
KR1019880700135A 1986-10-03 1987-10-02 타이밍신호 지연회로장치 KR900008048B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP61236716A JP2582250B2 (ja) 1986-10-03 1986-10-03 タイミング信号遅延回路装置
JP61-236716 1986-10-03
PCT/JP1987/000734 WO1988002577A1 (en) 1986-10-03 1987-10-02 Timing signal delay circuit

Publications (2)

Publication Number Publication Date
KR880702004A true KR880702004A (ko) 1988-11-07
KR900008048B1 KR900008048B1 (ko) 1990-10-31

Family

ID=17004714

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880700135A KR900008048B1 (ko) 1986-10-03 1987-10-02 타이밍신호 지연회로장치

Country Status (4)

Country Link
US (1) US4939677A (ko)
JP (1) JP2582250B2 (ko)
KR (1) KR900008048B1 (ko)
WO (1) WO1988002577A1 (ko)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5192886A (en) * 1990-03-15 1993-03-09 Hewlett-Packard Company Sub-nanosecond calibrated delay line structure
JPH06141333A (ja) * 1992-10-26 1994-05-20 Sanyo Electric Co Ltd 遅延回路
US5422891A (en) * 1993-07-23 1995-06-06 Rutgers University Robust delay fault built-in self-testing method and apparatus
EP0639003A1 (en) * 1993-08-11 1995-02-15 Advanced Micro Devices, Inc. Digitally adjustable and calibrated delay line and method
EP0703663B1 (en) * 1994-09-21 1997-12-29 STMicroelectronics S.r.l. Programmable digital delay unit
EP0897614B1 (de) * 1996-05-06 2000-11-08 Siemens Aktiengesellschaft Taktsignalgenerator
JPH1032474A (ja) * 1996-07-18 1998-02-03 Mitsubishi Electric Corp 可変遅延回路，及び可変遅延回路の校正方法
JP3280921B2 (ja) 1998-10-30 2002-05-13 株式会社東芝 可変遅延回路
JP4146965B2 (ja) 1999-05-17 2008-09-10 株式会社アドバンテスト 遅延信号生成装置および半導体試験装置
US6316944B1 (en) * 2000-04-29 2001-11-13 Hewlett Packard Company Effective netlength calculation
DE10027703B4 (de) * 2000-06-03 2005-03-03 Sms Demag Ag Verfahren und Vorrichtung zum Umformen, insbesondere Fließpressen eines metallischen Werkstücks
US7595673B2 (en) * 2006-02-17 2009-09-29 Zoran Corporation Clock signal generator
US8134396B2 (en) * 2009-02-24 2012-03-13 Infineon Technologies Ag Dynamic element matching for delay lines

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3763317A (en) * 1970-04-01 1973-10-02 Ampex System for correcting time-base errors in a repetitive signal
JPS5538710A (en) * 1978-09-11 1980-03-18 Hitachi Ltd Phase lock loop circuit
DE2855724A1 (de) * 1978-12-22 1980-07-03 Ibm Deutschland Verfahren und vorrichtung zur angleichung der unterschiedlichen signalverzoegerungszeiten von halbleiterchips
US4541100A (en) * 1981-05-15 1985-09-10 Tektronix, Inc. Apparatus including a programmable set-up and hold feature
JPS5832178A (ja) * 1981-08-19 1983-02-25 Advantest Corp Ｉｃテスタ
US4495628A (en) * 1982-06-17 1985-01-22 Storage Technology Partners CMOS LSI and VLSI chips having internal delay testing capability
JPS595736A (ja) * 1982-06-30 1984-01-12 Fujitsu Ltd タイミング作成回路
US4656632A (en) * 1983-11-25 1987-04-07 Giordano Associates, Inc. System for automatic testing of circuits and systems
FR2564613B1 (fr) * 1984-05-17 1987-04-30 Commissariat Energie Atomique Systeme de chronometrie electronique de haute resolution
US4737670A (en) * 1984-11-09 1988-04-12 Lsi Logic Corporation Delay control circuit
JPS6279379A (ja) * 1985-10-02 1987-04-11 Ando Electric Co Ltd タイミング信号発生装置
US4701920A (en) * 1985-11-08 1987-10-20 Eta Systems, Inc. Built-in self-test system for VLSI circuit chips
US4672307A (en) * 1985-12-20 1987-06-09 University Of Southern California Simplified delay testing for LSI circuit faults
US4783606A (en) * 1987-04-14 1988-11-08 Erich Goetting Programming circuit for programmable logic array I/O cell

Also Published As

Publication number Publication date
KR900008048B1 (ko) 1990-10-31
WO1988002577A1 (en) 1988-04-07
US4939677A (en) 1990-07-03
JP2582250B2 (ja) 1997-02-19
JPS6390912A (ja) 1988-04-21

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Legal Events

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A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20060913

Year of fee payment: 17

EXPY Expiration of term