KR890700287A - 셀프-타이밍 회로 - Google Patents

셀프-타이밍 회로

Info

Publication number
KR890700287A
KR890700287A KR1019880701006A KR880701006A KR890700287A KR 890700287 A KR890700287 A KR 890700287A KR 1019880701006 A KR1019880701006 A KR 1019880701006A KR 880701006 A KR880701006 A KR 880701006A KR 890700287 A KR890700287 A KR 890700287A
Authority
KR
South Korea
Prior art keywords
self
timing circuit
timing
circuit
Prior art date
Application number
KR1019880701006A
Other languages
English (en)
Other versions
KR910006479B1 (ko
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of KR890700287A publication Critical patent/KR890700287A/ko
Application granted granted Critical
Publication of KR910006479B1 publication Critical patent/KR910006479B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
    • H03K19/1772—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register with synchronous operation of at least one of the logical matrixes

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)
KR1019880701006A 1986-12-19 1987-10-26 셀프-타이밍 회로 KR910006479B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US06/943,353 US4751407A (en) 1986-12-19 1986-12-19 Self-timing circuit
PCT/US1987/002798 WO1988004864A1 (en) 1986-12-19 1987-10-26 Self-timing circuit
US943353 1992-09-10

Publications (2)

Publication Number Publication Date
KR890700287A true KR890700287A (ko) 1989-03-11
KR910006479B1 KR910006479B1 (ko) 1991-08-26

Family

ID=25479506

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880701006A KR910006479B1 (ko) 1986-12-19 1987-10-26 셀프-타이밍 회로

Country Status (6)

Country Link
US (1) US4751407A (ko)
EP (1) EP0293410B1 (ko)
JP (1) JPH01501749A (ko)
KR (1) KR910006479B1 (ko)
DE (1) DE3768005D1 (ko)
WO (1) WO1988004864A1 (ko)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR900004191B1 (ko) * 1987-03-18 1990-06-18 삼성전자 주식회사 Rc시정수를 이용한 가변 클럭 지연회로
JPH07120225B2 (ja) * 1988-04-15 1995-12-20 富士通株式会社 半導体回路装置
JPH03283182A (ja) * 1990-03-30 1991-12-13 Nec Corp 半導体昇圧回路
DE69231912T2 (de) * 1991-12-17 2002-04-04 St Microelectronics Inc Ausgangstreiberschaltung mit Vorladung
JP3467286B2 (ja) * 1992-05-19 2003-11-17 ヒューレット・パッカード・カンパニー 論理評価システム
US5488319A (en) * 1994-08-18 1996-01-30 International Business Machines Corporation Latch interface for self-reset logic
GB9426335D0 (en) * 1994-12-29 1995-03-01 Sgs Thomson Microelectronics A fast nor-nor pla operating from a single phase clock
KR100272672B1 (ko) 1997-12-31 2000-11-15 윤종용 다이나믹 씨모오스 회로
US6169422B1 (en) 1998-07-20 2001-01-02 Sun Microsystems, Inc. Apparatus and methods for high throughput self-timed domino circuits
US6265897B1 (en) * 1999-12-17 2001-07-24 Hewlett-Packard Company Contention based logic gate driving a latch and driven by pulsed clock
US7668029B2 (en) * 2006-08-11 2010-02-23 Freescale Semiconductor, Inc Memory having sense time of variable duration

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3962686A (en) * 1972-05-16 1976-06-08 Nippon Electric Company Limited Memory circuit
US4040015A (en) * 1974-04-16 1977-08-02 Hitachi, Ltd. Complementary mos logic circuit
US4060794A (en) * 1976-03-31 1977-11-29 Honeywell Information Systems Inc. Apparatus and method for generating timing signals for latched type memories
JPS58121195A (ja) * 1982-01-13 1983-07-19 Nec Corp プリチヤ−ジ信号発生回路
US4558435A (en) * 1983-05-31 1985-12-10 Rca Corporation Memory system
US4569032A (en) * 1983-12-23 1986-02-04 At&T Bell Laboratories Dynamic CMOS logic circuits for implementing multiple AND-functions
US4617480A (en) * 1984-10-22 1986-10-14 Motorola, Inc. High speed data synchronizer which minimizes circuitry
FR2592539B1 (fr) * 1985-12-31 1988-02-12 Philips Ind Commerciale Reseau programmable en logique dynamique et son application.

Also Published As

Publication number Publication date
EP0293410B1 (en) 1991-02-06
JPH01501749A (ja) 1989-06-15
US4751407A (en) 1988-06-14
KR910006479B1 (ko) 1991-08-26
EP0293410A1 (en) 1988-12-07
WO1988004864A1 (en) 1988-06-30
DE3768005D1 (de) 1991-03-14

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Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 19940818

Year of fee payment: 4

LAPS Lapse due to unpaid annual fee