KR880009482A - 고체촬상장치에 있어서의 출력회로 - Google Patents

고체촬상장치에 있어서의 출력회로 Download PDF

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Publication number
KR880009482A
KR880009482A KR870013429A KR870013429A KR880009482A KR 880009482 A KR880009482 A KR 880009482A KR 870013429 A KR870013429 A KR 870013429A KR 870013429 A KR870013429 A KR 870013429A KR 880009482 A KR880009482 A KR 880009482A
Authority
KR
South Korea
Prior art keywords
imaging device
state imaging
output circuit
solid state
circuit
Prior art date
Application number
KR870013429A
Other languages
English (en)
Other versions
KR0148997B1 (ko
Inventor
다다쿠니 나라부
데츠야 곤도
야스히토 마키
Original Assignee
오가 노리오
소니 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 오가 노리오, 소니 가부시키가이샤 filed Critical 오가 노리오
Publication of KR880009482A publication Critical patent/KR880009482A/ko
Priority to KR1019960030212A priority Critical patent/KR0150401B1/ko
Application granted granted Critical
Publication of KR0148997B1 publication Critical patent/KR0148997B1/ko

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Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C27/00Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/02Sample-and-hold arrangements
    • G11C27/024Sample-and-hold arrangements using a capacitive memory element
    • G11C27/026Sample-and-hold arrangements using a capacitive memory element associated with an amplifier
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C27/00Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/04Shift registers
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof

Abstract

내용 없음.

Description

고체촬상장치에 있어서의 출력회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음

Claims (1)

  1. 증폭회로와, 이 증폭회로의 입출력측의 최소한 한쪽에 접속되어 DC레벨이 일정하고 이득이 대략 1이 되는 버퍼 회로를 구비하여 이루어지는 고체촬상장치에 있어서의 출력회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019870013429A 1987-01-22 1987-11-27 전하전송장치에 있어서의 출력회로 KR0148997B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960030212A KR0150401B1 (en) 1987-01-22 1996-07-25 Output circuit of ccd

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP87-11356 1987-01-22
JP62-11356 1987-01-22
JP62011356A JP2812939B2 (ja) 1987-01-22 1987-01-22 電荷転送装置における出力回路

Publications (2)

Publication Number Publication Date
KR880009482A true KR880009482A (ko) 1988-09-15
KR0148997B1 KR0148997B1 (ko) 1998-12-15

Family

ID=11775749

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870013429A KR0148997B1 (ko) 1987-01-22 1987-11-27 전하전송장치에 있어서의 출력회로

Country Status (2)

Country Link
JP (1) JP2812939B2 (ko)
KR (1) KR0148997B1 (ko)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0533098Y2 (ko) * 1987-06-30 1993-08-24

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6134798A (ja) * 1984-07-25 1986-02-19 Sharp Corp 電荷転送素子の出力信号処理回路

Also Published As

Publication number Publication date
KR0148997B1 (ko) 1998-12-15
JP2812939B2 (ja) 1998-10-22
JPS63180277A (ja) 1988-07-25

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