KR880006905A - Integrated circuit for composite synchronous signal separation and high frequency digital information signal separation - Google Patents

Integrated circuit for composite synchronous signal separation and high frequency digital information signal separation Download PDF

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Publication number
KR880006905A
KR880006905A KR860009459A KR860009459A KR880006905A KR 880006905 A KR880006905 A KR 880006905A KR 860009459 A KR860009459 A KR 860009459A KR 860009459 A KR860009459 A KR 860009459A KR 880006905 A KR880006905 A KR 880006905A
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KR
South Korea
Prior art keywords
circuit
signal
signal separation
voltage
integrated circuit
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Application number
KR860009459A
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Korean (ko)
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KR890004060B1 (en
Inventor
신명철
김영생
Original Assignee
강진구
삼성반도체통신 주식회사
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Application filed by 강진구, 삼성반도체통신 주식회사 filed Critical 강진구
Priority to KR1019860009459A priority Critical patent/KR890004060B1/en
Publication of KR880006905A publication Critical patent/KR880006905A/en
Application granted granted Critical
Publication of KR890004060B1 publication Critical patent/KR890004060B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/08—Separation of synchronising signals from picture signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H04N5/20—Circuitry for controlling amplitude response
    • H04N5/205—Circuitry for controlling amplitude response for correcting amplitude versus frequency characteristic

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Synchronizing For Television (AREA)

Abstract

내용 없음No content

Description

합성동기 신호분리 및 고주파 디지탈 정보 신호 분리용 집적회로Integrated circuit for composite synchronous signal separation and high frequency digital information signal separation

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 집적회로의 블럭도.1 is a block diagram of an integrated circuit of the present invention.

제2도는 본 발명에 따른 제1도의 블럭도의 구체회로도.2 is a detailed circuit diagram of the block diagram of FIG. 1 according to the present invention;

제3도는 제2도의 구체회로도의 각부의 동작 파형도.3 is an operational waveform diagram of each part of the concrete circuit diagram of FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 버퍼 회로 2 : 제1저주파 필터1 buffer circuit 2 first low frequency filter

3 : 샘플링 회로 4 : 기억회로3: sampling circuit 4: memory circuit

5 : 임피던스 버퍼회로 6 : 비교회로5: impedance buffer circuit 6: comparison circuit

7 : 드라이브회로 8 : 정전압 발생회로7: drive circuit 8: constant voltage generating circuit

9 : 제2저주파 필터 10 : 합성동기 분리회로9: second low frequency filter 10: synthetic synchronous separation circuit

Claims (1)

합성 비디오 신호에 포함된 디지탈 정보 신호 및 디지탈 동기 신호를 분리하는 집적회로에 있어서, 입력 신호의 전력증폭을 위한 버퍼회로(1)와, 입력된 신호의 고주파 부분을 제거하는 능동형 제1저주파 필터(2)와, 여파된 신호중 굴곡으로 나타나는 저주파의 동기 신호 부분을 제거하는 샘플링 회로(3)와, 상기 샘플링 회로(3)에서 출력하는 전압을 비교전압으로 기억하는 기억회로(4)와, 상기 기억된 비교 전압을 적절한 레벨의 전압으로 변환하고 샘플링 기간동안 상기 비교전압을 유지하기 위한 임피던스 버퍼회로(5)가 상기 기억회로로부터 입력하는 상기비교전압과 비디오 신호의 데이터와 비교하는 비교회로(6)와, 비교된 신호를 적당한 레벨의 데이타로 출력하는 제1드라이브회로(7)와, 디지탈 동기 신호분리를 일정한 전압을 비교회로(6)와 드라이브 회로(7)에 공급하는 정전압 발생회로(8)와, 합성비디오신호중 수평동기 신호만 통과시키는 제2저주파 필터(9)와, 상기 수평동기 신호에서만 오프동작을 하며 소정 레벨의 펄스를 출력하는 스위칭회로로된 합성동기 분리회로(10)로 구성됨을 특징으로 하는 회로.An integrated circuit for separating a digital information signal and a digital sync signal included in a composite video signal, the integrated circuit comprising: a buffer circuit for power amplification of an input signal and an active first low frequency filter for removing a high frequency portion of an input signal ( 2), a sampling circuit 3 for removing a portion of the low frequency synchronization signal appearing in the bent signal, a memory circuit 4 for storing the voltage output from the sampling circuit 3 as a comparison voltage, and the storage A comparison circuit 6 for comparing the comparison voltage input from the storage circuit with the data of the video signal by an impedance buffer circuit 5 for converting the comparison voltage into a voltage having an appropriate level and maintaining the comparison voltage for a sampling period. And a first drive circuit (7) for outputting the compared signal as an appropriate level of data; A constant voltage generator circuit (8) supplied to the circuit (7), a second low frequency filter (9) for passing only a horizontal synchronizing signal out of the composite video signal, and a switching for outputting a pulse of a predetermined level by turning off only the horizontal synchronizing signal Circuit characterized in that composed of a synthetic synchronous separation circuit (10) as a circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019860009459A 1986-11-08 1986-11-08 Integral circuit for separating digital signals from complete video signals KR890004060B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019860009459A KR890004060B1 (en) 1986-11-08 1986-11-08 Integral circuit for separating digital signals from complete video signals

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019860009459A KR890004060B1 (en) 1986-11-08 1986-11-08 Integral circuit for separating digital signals from complete video signals

Publications (2)

Publication Number Publication Date
KR880006905A true KR880006905A (en) 1988-07-25
KR890004060B1 KR890004060B1 (en) 1989-10-18

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860009459A KR890004060B1 (en) 1986-11-08 1986-11-08 Integral circuit for separating digital signals from complete video signals

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KR (1) KR890004060B1 (en)

Also Published As

Publication number Publication date
KR890004060B1 (en) 1989-10-18

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