KR890004060B1 - Integral circuit for separating digital signals from complete video signals - Google Patents

Abstract

The integrated circuit separates the digital signal and the synchronous signal in a data line of teletext system to prevent from the leakage of the information. The integrated circuit includes a buffer circuit (1) for amplifying a power of input, the first low frequency filter (2) eliminating high frequency components of input signal, a sampling circuit (3), a memory circuit (4) memorizing output voltage of the sampling circuit, an impedance buffer circuit (5) converting the output voltage to adequate level, a comparator (6) , a driving circuit (7), a reguration voltage generator (8), and the second low frequency filter (9).

Description

Integrated circuit for composite synchronous signal separation and high frequency digital information signal separation

1 is a block diagram of an integrated circuit of the present invention.

2 is a detailed circuit diagram of the block diagram of FIG. 1 according to the present invention;

3 is an operational waveform diagram of each part of the concrete circuit diagram of FIG.

* Explanation of symbols for main parts of the drawings

1 buffer circuit 2 first low frequency filter

3: sampling circuit 4: memory circuit

5: impedance buffer circuit 6: comparison circuit

7: drive circuit 8: constant voltage generating circuit

9: second low frequency filter 10: synthetic synchronous separation circuit

The present invention relates to an improvement in integrated circuits for composite synchronization signal separation and digital information signal separation of composite video signals.

In general, when receiving text broadcasting information using a television receiver such as teletext, digital information is included for special information processing among received video signals, and digital information signal and basic clock signal for processing the information are included. For synchronization, a digital synchronization signal and a synthetic synchronization signal of a specific frequency are loaded.

Composite video signal that is being used is a character or graphics information carried in telrek text is composed of a third FIG period the horizontal synchronizing signal, as shown at T ₁ and the collar burr host signal period T ₂ and the data line T ₅ data line T ₅ Is composed of a synchronization period consisting of a synchronization clock and a framing code and a data packet period including various digital information signals.

Therefore, a teletext system of a television receiver receiving text multicasting needs a circuit that separates all digital information signals and synchronization signals on the data line and separates one information signal without loss in a highly stable manner. Done.

According to the conventional method, as the transmission frequency increases, the accurate data information signal cannot be separated, the consumption current is large, the margin of voltage margin and the distortion of the signal become large.

In addition, power supply noise such as power spike or hum affects the output of the comparator, and an error in current occurs due to temperature change, which may cause the output transistor switching operation to malfunction.

In addition, since the discharge root of the accumulated charge of the output transistor of the drive circuit is composed of a resistor, it is difficult to obtain the rise time and the fall time of the output transistor.

Accordingly, an object of the present invention is to separate the digital information signal and the synthesized synchronous signal contained in the text broadcasting data packet, to minimize the influence of the power supply voltage and temperature, and to speed up the switching speed of the output to accurately output the digital information signal. It is to provide an integrated circuit to separate.

Accordingly, an exemplary embodiment of the present invention provides an integrated circuit that separates a digital information signal and a digital synchronization signal included in a composite video signal, the buffer circuit for power amplification of an input signal, and a high frequency portion of an input signal. An active first low frequency filter, a sampling circuit for removing a portion of the low frequency registered signal that appears as a bend in the filtered signal, a memory circuit for storing the voltage output from the sampling circuit as a comparison voltage, and the stored comparison voltage An impedance buffer circuit for converting the voltage to an appropriate level and maintaining the comparison voltage for a sampling period; a comparison circuit for comparing the comparison voltage input from the memory circuit with data of a video signal; Drive circuit outputting data and constant voltage with comparator And a second low frequency filter for passing only a horizontal synchronizing signal of the composite video signal, and a switching circuit for outputting a pulse of a predetermined level by turning off only the horizontal synchronizing signal. It is done.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of an integrated circuit of the present invention, including a buffer circuit 1 for power amplification of an input signal, an active first low frequency filter 2 for removing a high frequency portion of an input signal, and A sampling circuit 3 for removing a portion of the low frequency synchronization signal that appears as a bend, a memory circuit 4 for storing a voltage output from the sampling circuit 3 as a comparison voltage, and a stored level of the comparison voltage at an appropriate level. An impedance buffer circuit 5 for converting to a voltage and maintaining the comparison voltage for a sampling period, and a comparison circuit 6 for comparing data of the video signal with the comparison voltage input from the storage circuit 4, The drive circuit 7 for outputting signals as appropriate level data, the constant voltage generating circuit 8 for supplying a constant voltage to the comparator and the drive circuit 7, and the horizontal synchronization signal of the composite video signal only pass. The key is comprised of a second low pass filter (9) and the horizontal synchronizing signal only in the off operation, and a switching circuit for outputting a pulse of a predetermined level only synthetic sync separation circuit (10).

Therefore, in the embodiment of the present invention having the above-described configuration, the composite video signal a is input to the buffer circuit 1.

The signal output passing through the buffer circuit 1 is input to the comparison circuit 6 while being input to the active first low frequency filter 2.

The composite video signal inputted to the active first low frequency filter 2 is filtered out of the active first low frequency filter 2 and input to the sampling circuit 3 by filtering the high frequency noise signal contained in the signal.

Although the noise component has been removed from the sampling circuit 3 through the active first low frequency filter 2, the synchronization signal period, which still has a strong output, is maintained during this period by the sampling signal input from the CPU. By preventing input into the memory circuit 4, the memory circuit 4 having a sufficient signal holding time much longer than this period can maintain a substantially constant voltage level until the end of the synchronous time elimination sampling time.

Therefore, this signal is input to the comparison circuit 6 through the impedance buffer circuit 5 to maintain the signal voltage as it is during the sampling time. Therefore, the comparison circuit 6 outputs the digital information signal in accordance with the difference between the signal input from the input buffer circuit 1 and the comparison signal input from the impedance buffer circuit 5.

This digital information signal is output through a high speed drive circuit 7 as a square wave of a digital signal level of a required level.

On the other hand, the horizontal synchronous signal in the data packet of the composite video signal inputted to the input terminal Is is filtered by the second low frequency filter 9, and the synthesized synchronous signal other than the horizontal synchronous signal is synthesized. )).

2 is a detailed circuit diagram of the block diagram of FIG. 1 according to the present invention, wherein Q ₁ -Q ₄₄ is a transistor, R ₁ -R ₂₉ is a resistor, C ₁ -C ₆ is a capacitor, and V _BB is a 5 volt power source.

The double capacitors C ₁ -C ₉ are external devices connected to the outside of the integrated circuit of the present invention.

The buffer circuit 1 in the block diagram of FIG. 1 described above corresponds to the components of the transistors Q ₁ -Q ₂ , resistors R ₁ -R _2, and capacitor C ₁ of FIG. 2, and the active first low frequency filter 2 is a transistor. Q ₃ -Q ₁₀ and resistors R ₃ -R ₅ and capacitors C ₂ -C ₃ , and the sampling circuit 3 corresponds to the parts consisting of transistors Q ₁₁ -Q ₁₈ and resistors R ₆ and R ₁₅ . The memory circuit 4 corresponds to the capacitor C ₄ , the impedance buffer 5 corresponds to the components of the transistors Q ₁₉ = Q ₂₆ and the resistor R ₈ , and the comparison circuit 6 includes the transistors Q ₂₈ '-Q. ₂₇ and a portion consisting of resistors R ₁₂ and R ₁₀ , the drive circuit 7 corresponds to a portion consisting of transistors Q ₂₈ -Q ₃₁ and resistors R ₁₁ -R ₁₅ , and the constant voltage generating circuit 8 comprises a resistor R Corresponds to the portion consisting of _16- R ₂₁ and transistors Q ₃₂ -Q ₄₁ , and the second low frequency filter 9 consists of a resistor R ₂₂ , a coil L ₁ and a capacitor C ₅ . The synthesized synchronous separation circuit 10 corresponds to a portion composed of resistors, R ₂₃ -R ₂₉ , capacitor C _6, and transistors Q ₄₂ -Q ₄₄ .

On the other hand, Figure 3 (a) to Figure 3 (g) is a waveform diagram of each part of Fig. 2 which is a concrete circuit diagram according to the present invention, wherein time T ₁ is a synchronous time, T ₂ is a burst signal period, T ₃ the digital synchronizing signal period, T ₄ is a digital information signal period.

Hereinafter, a detailed circuit diagram according to the present invention of FIG. 2 will be described in detail with reference to the waveform diagram of FIG. 3.

The composite video signal (a) of FIG. 3 (a) inputted through the DC blocking coupling capacitor C ₁ through the composite video signal input terminal Is is combined with the base of the transistor Q ₁ of the buffer circuit 1 and the amplification circuit 8. The capacitors C ₁ are respectively input to the base of the transistor Q ₁ .

The resistors R ₁ and R ₂ of the buffer circuit 1 are resistors for bias setting of the transistor Q ₁ , and the transistor Q ₂ serves as an active load of the emitter of the transistor Q ₁ .

Therefore, the composite video signal a inputted through the composite video signal input terminal Is outputs the voltage waveform in phase by the buffer circuit 1 having the high input impedance. Therefore, the composite video signal carrying the digital signal shown in FIG. 3 (a) is input to the active first low frequency filter 2 through the buffer circuit 1.

The active first low frequency filter 2 becomes a second order active low frequency filter by a lead lag band pass filter with passive low frequency filter resistors R ₃ , R ₄ and capacitors C ₂ , C ₃ .

Here it acts as an automatic amplifier consisting of Q ₃ -Q ₁₀ and resistor R ₅ , and this amplifier compensates for the resonant energy consumption of the _semi- period resistors R ₃ and R ₄ by capacitors C ₂ and C ₃ . .

The output waveform of the active first low frequency filter 2 is the waveform b shown in FIG. 3 (b) and is output from the active first low frequency filter 2 and input to the base of the transistor Q ₁₄ of the sampling circuit 3. do.

On the other hand, the synchronous signal sampling pulse C of FIG. 3 (c), which is input to the output signal input terminal Iu of the CPU, is input from the CPU to the base of the transistor Q ₁₁ through the resistor R ₁₅ of the sampling circuit 3.

Accordingly, the sampling signal C as shown in FIG. 3 (c) is input to the base of the transistor Q _{11 in} the synchronous portion of the waveform b of FIG. 3 (b) with the triangular wave bend, and the transistor Q ₁₁ during this sampling period. is because the "on" state to the traffic transistor Q ₁₃ is "off" all the transistors Q ₁₄ and Q ₁₅ are state are placed in the "off" state, 3 (b) separate signals (b) the sampling signal confidence ( 3) do not enter into the base of the transistor Q _14.

Therefore, since the transistors Q ₁₄ and Q ₁₅ are in the "off" state, the voltage applied to the capacitor C ₄ of the memory circuit 4 discharges through the base emitter and transistor Q ₂₁ of the transistor Q ₁₉ , and the sampling signal from the CPU When the "low" state is not input to the base of the transistor Q ₁₁ transistors Q ₁₁ is "off" state and the Q ₁₃ is "on" state, because the power supply voltage is gaepae capacitors C of the memory circuit 4 through the transistor Q ₁₈ Since the charge is ₄ , the waveform is formed as shown in FIG. 3 (d).

However, the change in the voltage of the capacitor C ₄ of the memory circuit 4 as in the third (d) during this sampling period is not so large a change, and thus does not affect the operation at all.

In addition, in the constant current circuit composed of transistors Q ₂₁ and Q ₂₃ and resistor R ₈ , the amount of source current flowing through the collector of transistor Q ₂₁ is adjusted to a very small value by enlarging resistor R _{8 so} that the sampling period is input from the CPU. Since the amount of current flowing through the base of the transistor Q ₁₉ is extremely small, the voltage change of FIG. 4 (d) can be made extremely small.

On the other hand, the impedance buffer 5 uses the differential transistors Q ₁₉ and Q ₂₀ and uses a constant current source composed of the transistors Q ₂₄ and Q ₂₅ as an active part to sufficiently amplify the voltage and its output is input to the base of the transistor Q ₂₆ .

Transistors Q ₂₆ and Q ₂₂ constitute an emitter power amplifier, and transistor Q ₂₂ is used as an active load of the emitter power amplifier, which together with Q ₂₃ constitute a constant current circuit.

Therefore, a high input impedance and low output impedance constitute a buffer circuit. Therefore, as described above, the impedance buffer circuit 5 is maintained for the sampling period so that the voltage change stored in the memory circuit 4 fluctuates very little, and the comparison circuit 6 stores the comparison voltage stored in the memory circuit 4. To the base of transistor Q ₂₄ '.

The comparison circuit 6 is composed of transistors Q ₂₄ ′ -Q ₂₇ and resistors R ₉ , R ₁₀ , and as described above, the comparison voltage stored in the memory circuit 4 is inputted to the base of the transistor Q ₂₄ ′. The data signal output through the buffer circuit 1 is input to the base of Q ₂₅ ′.

In addition, since the comparison circuit 6 must accurately detect and compare the extremely small voltage change stored in the memory circuit 4, a very stable circuit configuration is required.

Therefore, the comparison circuit 6 prevents the ripple or power supply noise of the power supply voltage Vcc from affecting the output of the comparison circuit 6, and also prevents the operation of the constant current circuit due to temperature change. As the circuit diagram, the reference voltage of the constant voltage generating circuit 8 was used.

The constant voltage generation circuit 8 has resistors R ₁₆ and R ₁₇ connected between the emitters of the transistors Q ₃₈ and Q ₃₉ whose bases are connected to each other and the power supply voltage Vcc, respectively, and between the base and ground of the transistors Q ₃₈ and Q ₃₉ . The emitter and collector of transistor Q ₄₀ are connected to each other, and the base of transistor Q ₄₀ has a constant current circuit connected to the collector of transistor Q ₃₉ and grounded through resistor R ₁₈ .

In the constant current circuit, the ratio of the current flowing through the resistor R ₁₈ and the collector current of the transistor Q ₃₈ is constantly determined by the ratio of the resistors R ₁₆ and R ₁₇ .

In addition, transistor Q ₄₀ is used as a control transistor to keep the current ratio even more constant.

Therefore, the constant current flowing through the collector of transistor Q ₃₈ is classified into a series connection of diode connection transistor Q ₃₂ and zener diode connection transistor Q ₃₃ and diode connection transistor Q ₃₄ -Q ₃₇ .

In addition, the emitter of the transistor Q ₃₂ is connected to the resistor R ₉ of the comparison circuit 6 and the collector of the transistor Q ₂₅ ′, and the collector of the transistor Q ₃₆ of the diode string is the transistor Q which is a constant current source of the comparison circuit 6. _It is connected to the base of ₂₆ 'and Q ₂₇ .

Therefore, the constant current is caused by the constant current by the voltage specification between the base emitters according to the temperature change of the transistors Q ₃₈ and Q ₃₉ and the temperature characteristic between the base emitters of the diode Q ₃₂ (the voltage between the base emitters decreases when the temperature rises). A constant current is supplied to the resistors R ₉ and the collectors of the transistors Q ₂₅ ′ of the comparison circuit 6, and similarly, a constant current is supplied to the bases of the transistors Q ₂₆ ′ and Q ₂₇ to perform stable operation according to temperature changes. The constant voltage is maintained by the operation of the zone diodes Q ₃₃ against the power supply voltage fluctuation so that the comparison circuit 6 can perform a stable operation.

The constant current circuit 8 also includes a constant current circuit composed of resistors R ₁₉ -R ₂₁ and transistor Q ₄₁ to generate constant current flowing through the collector of transistor Q ₄₁ and resistor R ₁₉ .

Therefore, by applying the constant voltage of the voltage drop of the resistor R ₂₁ due to the temperature characteristic between the voltage drop of the resistor R ₂₁ and the base emitter of the transistor Q _{41 to} the base of the transistor Q ₃₀ of the drive circuit 7 according to the voltage state of the emitter side. Accurate on / off operation can be achieved.

Therefore, the transistor Q ₂₆ 'and Q ₂₇ and the resistor R _10, the constant current circuit consisting of R ₁₂ is a transistor Q _26' rather than the collector current of the Q ₂₇ transistors Q ₂₆ 'as a function of the V _BB voltage of Q ₂₇ resistance R _10, and Since it is displayed as the resistance ratio of R ₁₂ , the influence of temperature change can be sufficiently eliminated, and even if a power supply noise occurs, the transistor Q ₂₅ 'collector and the resistor R ₉ are connected to the constant voltage generator circuit 8 so that it can operate stably. have.

As shown in FIG. 3 (e), the data signal e is input to the transistor Q ₂₅ 'base and the comparison signal f is transferred from the memory circuit 4 through the impedance buffer circuit 5 to the transistor Q ₂₄ ' base. Is entered.

When the data signal e is larger than the comparison signal f, the transistor Q ₂₈ is turned off, so the transistor Q ₃₀ of the drive circuit 7 configured as the TTL input terminal is turned on, so that the output terminal Op has a voltage of V _BB. Will appear.

On the contrary, when the data signal e is smaller than the comparison signal f, the transistor Q ₂₈ is "on" and the base current of the transistor Q ₃₀ turns on the output transistor Q ₃₁ , so that a low voltage appears at the output terminal Op. do.

This output waveform is the same as the third (f).

Transistor Q ₃₀ discharges the charge accumulated on the base very quickly when transistor Q ₃₁ is turned off, thereby shortening the rise time of the output to obtain an accurate pulse width output.

The constant voltage generation circuit 8 was used for stable and accurate operation of the comparison circuit 6 and the drive circuit 7.

Transistor Q ₄₀ is for compensating the base current of transistors Q ₃₈ and Q ₃₉ , and the constant voltage circuits of the comparison circuit 6 and the drive circuit 7 are separately configured to obtain accurate voltages.

Therefore, as shown in FIG. 3 (f), the data g is outputted, and the output of the drive circuit 7 can output the data at a normal TTL commercial voltage (maximum 5 volts).

On the other hand, when a data packet carrying a composite video signal, i.e., deletex data, is input through an input terminal Is, a color base having a high frequency by a second low frequency filter 9 composed of a resistor R ₂₂ , a coil L _1, and a capacitor C ₅ is input. The signal and the data synchronizing signal and the data signal are cut off, and only the horizontal synchronizing signal passes through the second low frequency filter 9 to be input to the synthesis synchronizing separation circuit 10.

Therefore, since the horizontal synchronization signal is input to the base of the transistor Q _{42 in} the 'low' state, the transistor Q ₄₂ is brought into a conductive state and the transistor Q ₄₃ is brought into a conductive state by the voltage applied to the resistor R ₂₂ .

Therefore, the voltage caused by the resistor R ₂₅ conducts the transistor Q _{44 so} that the output terminal Q of the synchronizing isolation circuit 10 is output in a low state, and the transistor Q ₄₂ is out of the period other than the horizontal synchronization period. Since it is turned off, transistors Q ₄₃ and Q ₄₄ are turned off and output.

Therefore, the waveform as shown in FIG. 3 (g) is output from the output terminal Q. FIG.

As described above, by using the constant voltage generator circuit, the output of the comparator is not affected by power voltage noise or hum, such as power spike or ripple. It is configured to be.

In addition, by using the reference voltage and the transistor Q ₃₀ of the constant voltage generation circuit diagram, the switching operation of the output transistor Q ₃₁ can be accelerated to output an accurate and stable digital information signal.

In addition, by integrating both digital information signal separation and composite synchronous separation, the PCB area can be reduced, and the cost and air consumption can be reduced.

Claims (1)

An integrated circuit for separating a digital information signal and a digital sync signal included in a composite video signal, the integrated circuit comprising: a buffer circuit for power amplification of an input signal and an active first low frequency filter for removing a high frequency portion of an input signal ( 2), a sampling circuit 3 for removing a portion of the low frequency synchronization signal appearing in the bent signal, a memory circuit 4 for storing the voltage output from the sampling circuit 3 as a comparison voltage, and the storage A comparison circuit 6 for converting the compared comparison voltage into a voltage of an appropriate level and comparing the comparison voltage input from the storage circuit with data of a video signal by an impedance buffer circuit 5 for maintaining the comparison voltage for a sampling period. And a drive circuit (7) for outputting the compared signal as data of a suitable level, and a comparison voltage (6) and a drive circuit (a constant voltage for digital synchronous signal separation). 7) a constant voltage generator circuit (8) for supplying it, a second low frequency filter (9) for passing only a horizontal synchronizing signal out of the composite video signal, and a switching circuit for outputting a pulse of a predetermined level with an off operation only in the horizontal synchronizing signal. Circuit characterized in that composed of a synthetic synchronous separation circuit (10).

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