KR900004134B1 - Sync signal separating and digital information separating ic of composite video signal - Google Patents

Abstract

An integrated circuit for separating a digital information signal and a digital synchronization signal from a synthesized video signal includes a first buffer circuit (1) for amplifying an input signal, an active type low pass filter (2) for eliminating the high frequency component, a second buffer circuit (3) for amplifying the power, a sampling circuit (4), a memory circuit (5) for memorizing the compared voltage, a high frequency impedance buffer circuit for maintaining the compared voltage, and a dividing circuit (15) for dividing the synthesized synchronization signal.

Description

Integrated Synchronization Signal Separation and Digital Information Separation Integrated Circuit of Composite Video Signal

1 is a diagram showing a data line in teletext.

2 is a block diagram of an integrated circuit according to the present invention.

3 is a detailed circuit diagram of FIG. 2 according to the present invention.

4 is an angular waveform diagram of the concrete circuit diagram of FIG. 3 according to the present invention.

5 is an explanatory diagram of the differential amplifier of FIG. 3 in accordance with the present invention.

6 is an operating characteristic diagram of FIG. 5 in accordance with the present invention.

* Explanation of symbols for main parts of the drawings

1: first buffer circuit 2: second low frequency filter

3: second buffer circuit 4: sampling circuit

5: memory circuit 6: high impedance buffer circuit

7: comparison circuit 8: first drive circuit

9 amplifier 10 resonant circuit

11: Comparative voltage generating circuit 12: Comparator

13 second drive circuit 14 second low frequency filter

15: Synthetic Synchronous Separator

The present invention relates to a composite synchronization signal separation and digital information separation integrated circuit of a composite video signal in a system for receiving a character broadcast of a television receiver.

In general, when receiving a TELETEXT using a television receiver, a digital information signal is loaded for special information processing among the received video signals, and at a specific frequency for synchronization of the digital information signal and the basic clock signal. The digital sync signal and the synthesized sync signal are loaded together.

Therefore, a teletext system of a television receiver for receiving character multicasting needs a circuit for separating all digital information signals and synchronization signals carried on the data line of the composite video signal as in the first diagram.

In the conventional method (Patent Application No. 86-7140), as the transmission frequency is increased, accurate data information signal separation and digital synchronization signal cannot be separated. Since the transmission frequency is high frequency, the signal distortion rate of the high frequency buffer is large. Because of the poor buffer operation and transfer characteristics due to the voltage difference across the buffer, oscillation occurs in the digital output signal and the digital synchronization signal, which are the final output of the drive circuit, resulting in an error in actually detecting the data.

Accordingly, an object of the present invention is to improve the characteristics of a high frequency buffer for accurately separating digital information signals and synchronization signals contained in a character multicast data packet without oscillation, and to accurately separate synthesized synchronization signals. An integrated circuit capable of doing so is provided.

Accordingly, an embodiment of the present invention provides an integrated circuit for accurately separating a digital information signal and a digital synchronization signal included in a composite video signal, comprising: a first buffer circuit for power amplifying an input signal of a first input terminal; An active first low frequency filter that removes a high frequency portion of a signal input from an output signal of the first buffer circuit, a second buffer circuit that amplifies the low frequency synchronization signal which appears as a bend among the signals filtered by the first low frequency filter again; And a sampling circuit for removing the low frequency synchronization signal portion of the second buffer circuit again amplified in accordance with the sampling signal supplied from the central processing unit to the second input terminal, and storing the voltage output from the sampling circuit as a comparison voltage. The circuit and the stored comparison voltage of the memory circuit to a voltage of an appropriate level and A high impedance buffer circuit for holding the comparison voltage, a comparison circuit for comparing the comparison voltage of the memory circuit held in the high impedance buffer circuit with data of a composite video signal which is an output of the first buffer circuit, and the comparison A first drive circuit for outputting the signals compared in the circuit as TTL level data, an amplifier for amplifying the power-amplified input signal of the first buffer circuit 1 for digital synchronization signal separation, and an amplification in the amplifier. A resonance circuit for selecting a synchronization signal having a specific frequency among the synthesized video signals, a comparison voltage generation circuit for generating a comparison voltage for comparing the output of the resonance circuit, and an output of the resonance circuit and an output of the comparison voltage generation circuit. A second drive circuit for outputting the comparator and the compared output of the comparator with a square wave having a TTL level, and the first input And a second low frequency filter for passing only a horizontal synchronizing signal among the input synthesized video signals, and a synthetic synchronous separation circuit for outputting a TTL level pulse by performing an off operation only to the horizontal synchronizing signal output from the second low frequency filter. .

Hereinafter, with reference to the accompanying drawings of the present invention will be described in detail.

2 is a block diagram of an integrated circuit according to the present invention, in which a first buffer circuit 1 for power amplifying an input signal of a first input terminal IS and an input signal from an output signal of the first buffer circuit 1 are illustrated in FIG. An active first low frequency filter 2 which removes the high frequency portion of the signal, and a second buffer circuit 3 which amplifies the low frequency synchronization signal which appears as a bend among the signals filtered by the first low frequency filter 2 again; And a sampling circuit (4) for removing the low frequency synchronization signal portion of the second buffer circuit (3) amplified again according to the sampling signal supplied from the central processing unit to the second input terminal (Iu), and the sampling circuit (4). The memory circuit 5 for storing the voltage outputted by the reference voltage as a comparison voltage, and a high impedance buffer for converting the stored comparison voltage of the memory circuit 5 into a voltage having an appropriate level and holding the comparison voltage during the sampling period. Circuit 6 and the high impedance A comparison circuit 7 for comparing the comparison voltage of the memory circuit 5 held by the Dunce buffer circuit 6 with data of a composite video signal which is an output of the first buffer circuit 1, and the comparison circuit ( A first drive circuit 8 for outputting the signals compared in step 7) as data having a TTL level, an amplifier 9 for amplifying the power-amplified input signal of the first buffer circuit into a digital synchronization signal; A comparison voltage generating circuit for generating a comparison voltage for comparing an output of the resonance circuit 10 with a resonant circuit 10 for selecting a synchronization signal having a specific frequency among the synthesized video signals amplified by the amplifier 9; 11), a comparator 12 for comparing the output of the resonant circuit 1 and the output of the comparison voltage generating circuit 11, and a second outputting the compared output of the comparator 12 as a TTL level square wave. Input synthesis ratio of the drive circuit 13 and the first input terminal Iu A second low frequency filter 14 which passes only a horizontal synchronizing signal among false signals, and a synthesized synchronous separation circuit 15 which outputs a TTL level pulse by performing an off operation only on a horizontal synchronizing signal output from the second low frequency filter. .

Therefore, according to the embodiment of the present invention having the above-described configuration, the composite video signal is input to the first buffer circuit 1 and the second low frequency filter 14, respectively, and amplified and filtered to the first input terminal IS.

The output signal amplified by the first buffer circuit 1 is input to the comparison circuit 7 and, on the other hand, is amplified by the amplifier 9 and filtered by the active first low frequency filter 2. For example, in the active first low frequency filter 2, a high frequency noise signal carried in the composite video signal amplified by the first buffer circuit 1 is filtered and amplified and output through the second buffer circuit 3, and the amplification is performed. The output is input to the sampling circuit 4.

In the sampling circuit 4, the noise component of the signal output through the active first low frequency filter 2 and the second buffer circuit 3 has been removed, but the curvature is still strong. The sampling signal input from the CPU via Iu prevents the output of the second buffer circuit 3 from being input into the memory circuit 5 during this period. At this time, in order to have a sufficient signal holding period much longer than the above period, the memory circuit 5 can maintain a substantially constant voltage level until the synchronous period elimination sampling time is over.

The sampling signal is configured to supply a horizontal synchronizing signal separated from the composite video signal from the CPU.

Therefore, the signal is input to the comparison circuit 7 while maintaining the signal voltage as it is during the sampling time through the high impedance buffer circuit 6.

The comparison circuit 7 outputs a digital information signal in accordance with the difference between the signal output from the first buffer circuit 1 and the comparison signal input from the high impedance buffer circuit 6.

The digital information signal is output as a square wave of the required digital signal level through the high speed first drive circuit 8.

In addition, the composite video signal output from the first buffer circuit 1 and input to the amplifier 9 undergoes a voltage amplification, and the amplified voltage is a load of the amplifier 9. The signal is inputted to and amplified by resonating at the frequency of the digital synchronization signal in the composite video signal a.

The output voltage resonated from the resonant circuit 10 and the comparison voltage which is the output voltage of the comparison voltage generating circuit 11 are inputted to the comparator 12 to compare voltages, so that only the digital synchronization signal is output from the comparator 12. The comparison signal is input to the second drive circuit 13 to output a digital synchronization signal at a voltage value of a required digital signal level.

On the other hand, the horizontal synchronous signal in the data packet of the composite video signal inputted to the first input terminal Is is filtered by the second low frequency filter 14, and the portions other than the horizontal synchronous are separated from the synthesized synchronous separation circuit 15. )).

The third turn is the Q1-Q5 in the figure as a specific circuit diagram of a second-degree block diagram according to the present invention, the transistor, R1-R40 are resistors, C1-C8 capacitor is, Vcc is the power source voltage V _BB is a 5 volt power supply.

The double capacitors C1-C8 and inductance L1-L2 are external devices connected to the outside of the integrated circuit of the present invention.

In the block diagram of FIG. 2 described above, the first butter circuit 1 corresponds to the components of transistors Q1-Q6, resistors R1-R4, and capacitor C1 in FIG. 3, and the active first low-frequency filter 2 includes resistors R5-R6. And a capacitor C2-C3, the second buffer circuit 3 corresponds to transistors Q7-Q14 and resistors R7-R9, and the sampling circuit 4 has a second so that a sampling frequency is supplied from the central processing unit. The input terminal Iu is connected to the resistor R10, and corresponds to the portion composed of the transistors Q15-Q20 and the resistors R10-R11, the memory circuit 5 corresponds to the capacitor C4, and the high impedance buffer circuit 6 is a transistor. The comparison circuit 7 corresponds to the portion composed of Q21-Q27 and the resistor R12, and the comparison circuit 7 corresponds to the portion composed of the transistors Q28-Q32 and the resistors R13-R14, and the first drive circuit 8 includes the transistors Q33-Q35 and the resistor R15. Corresponds to the portion consisting of -R18, the amplifier 9 having a resistor R40 and transistor Q Corresponding to the portion consisting of 36-Q40, the resonant circuit 10 corresponds to the portion consisting of capacitor C5 and inductance L1.

The comparison voltage generating circuit 11 corresponds to the resistors R23-R24, the comparator 12 corresponds to the portion consisting of the capacitors C6, the resistors R21-R22, R25-R26 and the transistors Q41-Q45, and the second drive circuit 13 ) Corresponds to the portion composed of resistors R27-R30 and transistors Q46-Q48, and the second low frequency filter 14 corresponds to the portion composed of resistors R31, R32, inductance L2 and capacitor C7, and the synthesized synchronous separation circuit 15 Corresponds to the portion consisting of resistors R34-R39, capacitor C8 and transistors Q49-Q51.

4 (a)-(j) are operational waveform diagrams of the respective parts of FIG. 3, which are concrete circuit diagrams according to the present invention, wherein time T1 is a synchronization time, T2 is a burst signal period, and T3 is a digital synchronization signal period. , T4 is a digital information signal period, and T5 is a data line.

Hereinafter, a detailed circuit diagram according to the present invention of FIG. 3 will be described in detail with reference to the waveform diagram of FIG. 4. The composite video signal a of FIG. 4 (a) input through the DC blocking coupling capacitor C1 is input to the base of the transistor Q2 of the first buffer circuit 1.

The resistors R1 and R2 of the first buffer circuit 1 are the bias setting resistors of the transistor Q2, and the negative input of the first buffer circuit 1 is connected to the output terminal of the buffer to operate as a positive buffer that is 100% fed back to the transistor. The base voltage of Q3 becomes equal to the base voltage of transistor Q2.

Transistors Q5 and Q6 become current sources. The main cause of the distortion of the first and second buffer circuits 1 and 3 is a common emitter drive, and the emitters of the transistors Q2, Q3, Q9 and Q10 of the first and second buffer circuits 1 and 3 are the same. The linearity of the drive transfer characteristics of the first and second buffer circuits (1, 3) by the voltage reduction caused by the resistors R3 and R4, and the resistors R7 and R8 by adding the resistors R3 and R4 and the resistors R7 and R8. And the first and second buffer circuits 1 and 3 have a constant current source of transistor Q1, so that the emitters of the transistors Q2, Q3, Q9 and Q10 are R3, R4, R7, By raising the emitter current by R8), the in-phase noise removal rate (CMRR) is increased, and the transmission frequency of the high frequency is transmitted more accurately and stably.

FIG. 5 shows an explanatory circuit diagram of the differential amplifier used in the first buffer circuit 1 of FIG. 3, wherein a portion composed of the transistors Q101 and Q102 and the power supply voltage VCC is a constant current source circuit. If the input voltages of the bases of the transistors Q100 and Q103 are referred to as V1 and V2, respectively, and the difference between these input voltages is ΔVin, it is expressed as follows.

ΔVin = V1-V2 = V _BE1 -V _BE2 + R _E (I1-I2) ....... (1)

Where V _BE1 is the voltage between base emitters of transistor Q100, V _BE2 is the voltage of base emitter of transistor Q103 and I1 and I2 are collector currents of transistors Q100 and Q103, respectively.

Meanwhile, the voltages V _BE1 and V _BE2 between the base emitters of the transistors Q100 and Q103 formed on the same semiconductor substrate with the same geometry can be written as follows.

로써 절대온도 T가 주어지면 볼츠만 상수 K와 전하량 q에 의해 값이 주어지는 상수이며, Is는 역포화 전류를 나타낸 것이다.here

Given the absolute temperature T, the value is given by the Boltzmann constant K and the charge q. Is represents the reverse saturation current.

The output voltage difference ΔVo

And I1 + I2 = I, so get I1 and I2 by

Becomes Therefore, ΔVin can be written as follows by equations (1) and (4).

Therefore, the expression (5) can be written as follows for -Vo <

This can be represented as a sixth graph by showing the characteristic graph in a table.

That is, by adding the emitter resistors R _E of the transistors Q100 and Q103, the transmission characteristics of the differential amplifier become more linear when the input voltage difference ΔVin is increased, thereby reducing the cause of distortion.

In addition, the in-phase noise removal rate (CMRR) can be written as shown in the following Equation (7).

Where I _E is the emitter current of transistors Q100 and Q103.

Therefore, the in-phase noise removal rate can be increased by the resistor R _E to eliminate the cause of the oscillation phenomenon appearing at the output stage.

Meanwhile, in the differential mode, the differential input resistance is increased by increasing the resistance R _E.

The composite video signal passed through the first buffer circuit 1 is input to the second-order active low frequency filter 2 composed of resistors R5-R6 and capacitors C2-C3.

The portion composed of transistors Q7-Q14 and resistors R7-R9 serves to compensate for the resonance energy consumption of the low frequency filter by the second buffer circuit 3.

The output waveforms of the active first low frequency filter 2 and the second buffer circuit 3 are output to the base of the transistor Q19 of the sampling circuit 4 as the waveform (b) shown in FIG.

On the other hand, the output signal of the central processing unit (CPU), that is, the synchronous signal sampling pulse (c) of FIG. 4 (c) input to the second input terminal (Iu) of the transistor Q15 through the resistor R10 of the sampling circuit (4). It is entered into the base.

Accordingly, the sampling circuit c as shown in FIG. 4 (c) is input to the base of the transistor Q15 in the synchronization portion having the triangular wave in the waveform b of FIG. 4 (b). The transistor Q17 is in the " off " state, and the transistors Q19 and Q20 are both in the " off " state, so that the signal b in FIG. 4 (b) is the base of the transistor Q19 of the sampling circuit 4; Transistor Q19 does not operate even when is input.

Therefore, since the transistors Q19 and Q20 are in the " off " state, they are discharged through the base-emitter and the transistor Q22 of the transistor Q24 charged in the capacitor C4 of the memory circuit 5, and the sampling inputted from the second input terminal Iu. When there is no signal and the "low" signal is input to the base of the transistor Q15, the transistor Q15 is in the "off" state, and the transistor Q17 is in the "on" state, so that the power supply voltage is supplied to the memory circuit 5 through the transistor Q18. Since the capacitor C4 is charged, a waveform as shown in FIG. 4 (d) is achieved. The transistor Q18 is a two collector, which is a multi-collector PNP transistor.

However, it is to be noted that, due to the voltage change of the capacitor C4 of the memory circuit 4 as shown in FIG. 4 (d) in the sampling period, it is configured to have a change small enough to not affect the operation of the function at all. .

In addition, in the constant current circuit composed of the transistors Q21, Q22 and the resistor R12, the amount of current flowing through the collector of the transistor Q21 is increased by adjusting the resistance R12, so that the sampling signal input from the central processing unit through the second input terminal Iu is Since the amount of current flowing through the base of the transistor Q24 during the sampling period is extremely small, the voltage change in FIG. 4 (d) can be made extremely small.

On the other hand, the high impedance buffer circuit 6 uses the differential transistors Q24 and Q25, and uses a constant current source composed of the transistor Q26 as the active load to provide sufficient voltage amplification, and its output is input to the base of the transistor Q27.

Transistors Q27 and Q23 use an emitter follower amplifier and transistor Q23 together with Q21 is used as the active load of the emitter power amplifier which constitutes a constant current circuit.

Therefore, a buffer circuit with high input impedance and low output impedance is constructed. Therefore, the high impedance buffer circuit 6 maintains the sampling voltage so that the voltage change stored in the memory circuit 5 fluctuates very little as described above, and stores the comparison voltage stored in the memory circuit 5 in the comparison circuit ( 7 is input to the base of transistor Q29, and the data signal output through the first buffer circuit 1 is input to the base of transistor Q28.

Therefore, as shown in FIG. 4E, the data signal e is input to the base of the transistor Q28, that is, the high impedance buffer circuit 6 is removed from the memory circuit 5 to the base of the transistor Q28. When the comparison voltage f input through the high impedance buffer circuit 6 is set to be lower than the data signal e amplified by the first buffer circuit 1 applied to the base of the transistor Q29, the comparison circuit ( 7) is changed by the data signal e as shown in the comparison signal f. This allows data to be separated without storage even in the event of sudden changes in the reference offset potential of the data.

Therefore, when the data signal e is present, the current flowing through the collector of the transistor Q29 becomes large, so that the transistor Q33 is in the "off" state, and the transistor Q35 is also in the "off" state, so that the output terminal OP has almost the same voltage as VBB. do.

On the other hand, in the absence of the data signal e, the collector of transistor Q29 is much smaller than the current flowing in the collector of transistor Q28, so that Q33 is in the "on" state, and transistor Q35 is also in the "on" state and is output to the output terminal OP. There is no voltage.

Therefore, the data g is output as shown in FIG. 4 (f), and the output of the first drive circuit 8 can output the data at a normal TTL voltage (5 volts).

The input signal of the amplifying circuit 9 is inputted to the base of the transistor Q37 in phase when the composite video signal a passed through the first buffer circuit 1 is input to the base of the transistor Q36 of the amplifier 9, and is amplified. It is input to the furnace 10.

Here, the transistors Q38, Q39, and Q40 are constant current circuits, and the transistors Q38 and Q39 serve as active loads of the transistors Q36 and Q37, respectively.

The resonant circuit 10 may also be a load of the amplifier 9. Therefore, the composite video signal a is resonated and amplified in the resonant circuit 10 composed of the capacitor C5 and the inductance L1 so as to resonate at the frequency of the digital synchronization signal, so that a signal such as (h) in FIG. It is printed on (K). At this time, the intermediate voltage K becomes the power supply voltage VCC / 2.

As such, the signal h of FIG. 4G, known as the frequency of the digital synchronization signal, is input as the inverted signal of the signal h to the base of the transistor Q41 through the coupling capacitor C6 of the comparator 12. At this time, since the resistors R21 to R24 have the same resistance value, the intermediate voltage K becomes VCC / 2 at the bases of the transistors Q41 and Q42.

In addition, since the resistors R23 and R24 of the comparison voltage generating circuit 11 have the same values, the voltage input to the base of the transistor Q42 of the comparator 12 becomes a constant value of VCC / 2. At this time, when the base voltage of the transistor Q46 of the second drive circuit 13 is at the maximum, the zener voltage of the transistor Q47 and the two base emitter voltages of the transistors Q46 and Q48 are added together, and the transistor Q48 becomes "on" and the output is performed. Terminal Q is in the "low" state.

Therefore, at this time, the resistor R28 is used as a protection resistor to prevent the overcurrent from flowing through the transistor Q46, and the resistor R25 is used to make the base voltage of the transistor Q46 equal to i in FIG. 4 (h) using the transistor Q45 current source. Flow the current through. The inverted signal of the h signal in FIG. 4 (g) input to the base of the transistor Q46 is such that the base input voltage of the transistor Q41 is smaller than the base input voltage of the transistor Q42 by the operation of the transistors Q41 and Q42 of the comparator 12. In this case, the base voltage of the transistor Q46 is set to the t voltage of FIG. 4 (h). In the opposite case, the waveform of (h) appears at the base of the transistor Q46.

Therefore, in the waveform of the synchronization signal input to the base of the transistor Q46, the upper signal is removed more than t voltage and only the lower part comes out as shown in i of FIG. That is, when the i signal is the t signal, the transistors Q46, Q47 and Q48 are "on", and when less than t hours, the transistors Q46, Q47 and Q48 are "off" to obtain the signal j of FIG. 4 (i), which is a digital signal. It is a synchronization signal. At this time, the resistors R28 and R29 are for discharging the electric charges generated by the switching operation to speed up the switching operation.

In addition, the transistors Q43, Q44 and Q45 become constant current circuits. On the other hand, when input to the composite video signal, i.e., the data packet carrying the teletext data, via the first input terminal Is, the high frequency color burr is performed by the second low frequency filter 14 composed of the resistor R31, the inductance L2 and the capacitor C7. The test signal and the data synchronizing signal and the data signal are cut off, and only the horizontal synchronizing signal is passed through the second low frequency filter 14 to be input to the synthesis synchronizing separation circuit 15.

Therefore, the horizontal synchronizing signal is inputted to the base of transistor Q49 in the "low" state, so it is input to the base of transistor Q49, so transistor Q49 is turned on and transistor Q50 is also turned on by the voltage across resistor R35. Therefore, the voltage caused by the resistor R37 conducts the transistor Q51 so that the output terminal Q of the synchronizing isolation circuit 15 outputs a "low" voltage, and the transistor Q49 is "off" in a period other than the horizontal synchronization period. Transistors Q50 and Q51 are in the " off " state. A voltage substantially equal to V _BB is output to the output terminal Q, but a waveform as shown in FIG. 4 (j) is output from the output terminal Q.

As described above, the present invention provides a more linear operation characteristic of the buffer due to the addition of the emitter resistors R3, R4, R7, and R8 of the first and second buffer circuits 1 and 3 to the change of the video signal. High frostbite noise elimination removes the oscillation of digital information signal and high frequency digital sync signal as well as the interference between digital information signal and digital sync signal by transmitting accurate and stable signal even for external factors with high fluctuation. Clear signals can be separated, resulting in a significant reduction in data detection errors. Also, high frequency sync signals can be input without distortion and phase difference to separate them.

In addition, by integrating digital information signal separation, digital synchronization signal separation, and synthetic synchronous branching function, PCB area reduction cost and airborne saving can be obtained.

Claims (1)

An integrated circuit that separates the digital information signal and the digital synchronization signal included in the composite video signal, the constant current source and the transistor connected to the collector side of the differential amplifying transistors Q2 and Q3 and Q2 and Q3. A first buffer circuit (1) for power amplification of an input signal connected to a constant current source through resistors (R3) and (R4) respectively connected to the emitters of the transistors (Q1) and (Q3); The active first low frequency filter 2 for removing the high frequency component of the amplified signal of the first buffer circuit 1 and the signal for which the high frequency component of the active first low frequency filter 2 is removed are differential amplifier Q9. A second buffer circuit (2) capable of linearly amplifying power even when a large signal is input by connecting to input to the base of Q10 and connecting resistors R7 and R8 to the emitter, respectively; The filtered and incremental of the first low frequency filter 2 active in a second buffer circuit 3 Sampling circuit (4) for removing the low-frequency synchronization signal portion of the signal is shown according to the sampling signal input through the second input terminal (Iu) and the voltage output from the sampling circuit (4) as a comparison voltage A high-impedance buffer circuit 6 for storing the memory circuit 5, the stored comparison voltage of the memory circuit 5 into a voltage of an appropriate level, and maintaining the comparison voltage for a sampling period; A comparison circuit 7 for comparing the comparison voltage input from (5) with data of the video signal, a first drive circuit 8 for outputting the signal compared in the comparison circuit 7 as TTL level data; And an amplifier 9 for amplifying a composite video signal for separating the digital synchronization signal from the output of the first buffer circuit 1, and a synchronization signal having a specific frequency among the output synthesized video signals of the amplifier 9. According to the comparison voltage of the resonant circuit 10 for discrimination, the comparison voltage generation circuit 11 for generating a comparison voltage for comparing the output of the resonance circuit 10, and the comparison voltage generation circuit 11 A comparator 12 for comparing the resonant output, a second drive circuit 13 for outputting the compared output of the comparator 12 with a square wave of an appropriate level, and horizontal synchronization of the composite video signal of the first input terminal Is. A second low frequency filter 14 which passes only a signal, and a synthetic synchronous separation circuit 15 which switches to output at a digital pulse level by turning off only the horizontal synchronous signal which is an output of the second low frequency filter 14. And a digital information separation integrated circuit for composite synchronous signal separation and composite video signal.

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