KR900006470B1 - Composition video signal processing intergrate circuit - Google Patents

Abstract

The IC for separating the high freq. digital information and synch. signals contained in the synthesised video signal includes a buffer (10), a first low freq. filter (12) filtering the horizontal synch. signal, a sample and hold circuit (14) sampling the synch. signal, a first comparator (16) separating the digital information signal and adding it with certain DC level, a first driver (20) providing output of the comparator with a certain level, a second comparator (18) driving the first driver with the DC level digital signal, s second driver (38) reproducing synch. clock pulse, and a synthesised synch. signal separator (44) switching off only with the horizontal synch. signal.

Description

Composite video signal processing integrated circuit

1 is a view showing a data line in teletext.

2 is a block diagram of the present invention.

3 is a detailed circuit diagram of FIG. 2 in accordance with the present invention.

4 is an operational waveform diagram of each part of FIG. 3 according to the present invention.

5 is an explanatory diagram of a differential amplifier according to the present invention.

6 is a relationship between the differential input voltage and the output voltage of FIG. 5 according to the present invention.

The present invention relates to an integrated circuit for processing composite video signals, and more particularly, to an integrated circuit for separating high frequency digital information and synchronization signals included in a composite video signal.

In general, a composite video signal containing character or graphic information used in teletext includes a horizontal synchronization signal period T1, a color burst signal period T2, and a data line T5, as shown in FIG. Is composed of a synchronization signal period T3 composed of a synchronous clock and a framing code, and a data packet period T4 containing various digital information signals.

The teletext system of a television receiver for receiving the character multicast must separate all digital information signals and synchronization signals on the data line, which requires a circuit for separating the information signals in a highly stable manner. do.

In the conventional method (Patent Application No. 86-7139), as the transmission frequency increases, the purified data information signal separation and digital synchronization signal cannot be separated, and the margin of voltage margin and signal distortion become large. There was a flaw.

Accordingly, an object of the present invention is to input digital information signals of high frequency without distortion and phase difference, to accurately separate digital information and synchronization signals from digital information signals carried in a composite video signal, and to separate and integrate synthetic synchronous signals as well. It is to provide an integrated circuit that can reduce the current consumption in the circuit and have a margin for power margin.

Accordingly, the present invention for achieving the above object is a high frequency buffer circuit having a high impedance outputting a digital information signal of a high frequency of the input composite video signal without phase difference and distortion, and a horizontal synchronous signal of the composite video signal output from the high frequency buffer circuit Sampling and maintaining the first low frequency filter for filtering out the high frequency information signal and the low frequency synchronizing signal of the horizontal synchronizing signal output from the first low frequency filter by the sampling signal output from the CPU. And a reference voltage by inputting a comparison voltage between the sample and hold circuit to be outputted, the sampling signal output from the sample and hold circuit and the signal output from the high frequency buffer circuit, and the comparison voltage to the first comparison circuit. A second non-reciprocal furnace for determining the driving saturation DC level by comparing with the second and the second A first drive circuit which performs an "on" or "off" operation according to an output signal of the comparison circuit and generates a pulse of a predetermined level, an amplifying circuit which resonates and amplifies only a digital synchronization signal from the output signal of the high frequency buffer circuit; A first comparator for comparing the digital synchronization signal amplified by the medium width circuit with a reference voltage and outputting the digital synchronization signal at a predetermined desired DC level; and a lower signal of the DC level of the output signal from the output signal of the first comparator. A second comparator for outputting only a second comparator, a second drive circuit for outputting a digital sync signal having a predetermined level according to the output of the second comparator, a second low frequency filter for inputting a composite video signal and passing a horizontal sync signal through the second comparator 2 Synchronous Synchronization for Separating Synchronizer and Data from Synthetic Video Signal by Horizontal Synchronization Signal Filtered by Low Frequency Filter Characterized by consisting of a circuit.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a digital information signal separation integrated circuit of a data line included in a composite video signal of a character multicasting according to the present invention, wherein a phase difference of a high frequency digital information signal among the composite video signals input to the input terminal 22 is shown. And a high frequency buffer circuit 10 having a high input impedance output without distortion and a horizontal synchronous signal from the composite video signal outputted from the high frequency buffer circuit 10 to output and block the high frequency information signal. The first low frequency filter 12 and the horizontal synchronous signal output from the first low frequency filter 12 are sampled by an output sampling frequency signal of a CPU which is input through the sampling frequency input terminal 24. A sample-and-hold circuit 14 for holding the sample, a sampled signal of the horizontal synchronization signal output from the sample-and-hold circuit 14, and the high frequency buffer A second non-conductor 16 for comparing the signals output from the circuit 10 and a second voltage for determining the drive saturation DC level by comparing the output voltage of the first non-conductor 16 with the reference voltage; A first drive circuit 20 for outputting a pulse of a predetermined level by operating " on " or " off " in accordance with the comparison circuit 18, the output signal of the second non-intersection 18, and the high frequency buffer circuit. An amplifying circuit 32 which resonates and amplifies only the digital synchronizing signal from the output signal of (10), and compares the digital synchronizing signal amplified by the amplifying circuit 32 with a comparison voltage to obtain a digital synchronizing signal at a predetermined DC level. A second comparator 36 which inputs a first comparator 34 to output and an output signal of the first comparator 34 to output only a lower signal of a DC level of an output signal output from the first comparator 34; And a digital synchronization signal having a predetermined level according to the output of the second comparator 36. A second drive circuit 38 for outputting, a second low frequency filter 42 for inputting a composite video signal through the input terminal 22 to pass a horizontal synchronization signal, and a second low frequency filter 42 And a synchronizing separation circuit 44 for separating the synthesizing video signal into the synchronizing section and the data portion by the horizontal synchronizing signal to be output.

Briefly describing an embodiment of the present invention with reference to FIG. 2, when a composite video signal carrying data is input through the input terminal 22, the high frequency buffer circuit 10 transmits high frequency digital information in the composite video signal. The signal is output without distortion and phase difference.

An output signal having the same waveform as the signal input to the input terminal 22 is buffered in the high frequency buffer circuit 10 and input to the first low frequency filter 12 and simultaneously input to the first non-converting channel 16. . The first low frequency filter 12 passes only a horizontal synchronous signal that becomes a low frequency of the composite video signal input through the high frequency buffer circuit 10 and blocks other high frequency components. The sample and hold circuit 14 inputs a pulse only to a horizontal synchronous signal of the composite video signal of the output of the first low frequency filter l2, which is generated and supplied to a CPU (not shown). Is inputted to the sampling frequency input terminal 24, is sampled by the switching action by the input sampling pulse, and is maintained as a predetermined signal.

The first non-converter 16 inputs an output signal from the sample and hold circuit 14 and a composite video output from the high frequency buffer circuit 10 and compares the two signals. A signal larger than the output signal of the sample and hold circuit 14, that is, a digital information signal is output. In addition, the second non-crossing path 18 compares the digital information output from the first non-crossing path 16 with a predetermined level and compares it according to an input DC level. If the DC level is higher than the DC level, the first drive circuit 20 is turned on. If the DC level is lower than the DC level, the first drive circuit 20 is turned off. Can be separated.

Accordingly, the first drive circuit 20 performs on / off operation according to the digital information signal output from the second non-intersection 18 to separate and output the digital information shaped into pulses of a predetermined level.

On the other hand, the composite video signal passing through the high frequency buffer circuit 10 resonates the digital synchronization signal in the data packet of the composite video signal by the amplifying circuit 32 having the resonance circuit, and amplifies and outputs only the digital synchronization signal.

The detected digital synchronous signal is input to the first comparator 34 to output the amplified digital synchronous signal by comparison with a predetermined DC level, and the output signal of the first comparator 34 is output to the second comparator 34. The output of the second comparator 36 conducts by saturating the second drive circuit 38 by comparison to the comparator 36 and based on the DC level so as to obtain an output voltage of " 0 " level. When the voltage is smaller than the DC level, the second drive circuit 38 is turned off to obtain an output voltage of the " 1 " level, so that the digital synchronization signal can be output separately.

On the other hand, the horizontal synchronous signal in the data packet of the composite video signal input to the input terminal 22 is filtered by the second low frequency filter 42, and the synthesized synchronous signal other than the horizontal synchronous signal is synthesized. )

3 is a circuit diagram of an embodiment of a circuit diagram of a circuit for separating digital information signal separation and digital synchronization signals included in the composite video signal according to the present invention of FIG. 2, wherein R1-R45 is a resistor, and C1 C9 is a capacitor, Q1-Q58 is a transistor, D1 is a diode, ZD1-ZD4 is a zener diode, VCC is the supply voltage, and VBB is a 5-volt supply.

Capacitor C1, resistors R1, R2, R34 and R35 and transistors Q1-Q7 in the figure correspond to the high frequency buffer circuit 10 of FIG. 2, and resistors R3, R4, R6, R36 and R37 and capacitors C2 and C3. And a portion composed of transistors Q8-Q15 correspond to the first low frequency filter 12, and resistors R5, R7, R8 and R10-R12, capacitors C4, transistors Q16-Q30 and the sampling frequency input terminal 24 The portion connected to the base of the transistor Q16 through the sample and hold circuit 14 corresponds to the sample and hold circuit 14, and the portion composed of the resistors R9 and R13-R15, the diode D1 and the transistors Q31-Q34 corresponds to the first non-intersection 16, A portion composed of resistors R16, R17, transistors Q35-Q39, zener diodes ZD1, and ZD2 corresponds to the second comparison circuit 18, and a portion composed of resistors R18-R20, transistors Q40, Q41 is the first drive circuit 20 Corresponds to.

A portion composed of capacitors C5-C7 and coils L1 and transistors Q42-Q44 correspond to the amplifier circuit 32, and a portion composed of resistors R22-R28 and transistors Q45-Q48 correspond to the first comparator 34, and resistor R29 And a portion composed of R30 and transistors Q49-Q53 and zener diodes ZD3 and ZD4 correspond to the second comparator 36, and a portion composed of transistors Q54 and Q55 and resistors R31-R33 correspond to the second drive circuit 38. , The portion composed of the resistor R38, the coil L2 and the capacitor C8 corresponds to the second low frequency filter 42, and the portion composed of the resistors R39-R45, the capacitor C9 and the transistors Q56-Q58 correspond to the synthesized synchronous separation circuit 44. .

4 is a view showing an operation waveform of each part of FIG. 3 which is an embodiment of the present invention.

Hereinafter, an embodiment according to the present invention of FIG. 3 will be described in detail with reference to the waveform diagram of FIG. 4.

As shown in FIG. 4, when the composite video signal is input through the input terminal 22, the DC component is blocked through the DC blocking capacitor C1 of the high frequency buffer circuit 10, and only the signal component is input to the base of the transistor Q1. do.

The high frequency buffer circuit 10 has a differential amplifier composed of transistors Q1 and Q2 and resistors R34 and R35, transistors Q4 and Q5 as constant current active loads, transistors Q6 and Q7 as current sources and emitter-powered output transistors Q3. It is configured to be fed back to the base of Q2.

Accordingly, the differential amplifiers of the transistors Q1 and Q2 have high input impedance by the feedback action, and output up to 4MHZ of input signals without distortion. If the common emitter drive method is applied to the input signal above (about 5MHZ), distortion of the signal is generated. Therefore, buffer the voltage by the voltage reduction generated by emitter resistors R34 and R35 of the transistors Q1 and Q2. Extend the linearity of the drive transfer characteristics of the circuit.

In addition, since the high frequency buffer circuit 10 has a constant current source by the transistors Q4 and Q5, the emitter current is increased by the emitter resistors R34 and R35, thereby increasing the in-phase noise cancellation curve (CMRR), The transmission frequency of is transmitted accurately and stably.

FIG. 5 shows an explanatory circuit diagram of the differential amplifier used in the high frequency buffer circuit 10 of FIG. 3 according to the present invention, wherein a portion composed of transistors Q101 and Q102 and a power supply voltage VCC is a constant current source circuit.

If the input voltages of the bases of the transistors Q100 and Q103 are referred to as V1 and V2, respectively, and the difference between the input voltages is ΔVin, it is expressed as in the following formula (1).

△ Vin = V1-V2 = V _BE1 -V _BE1 + RE (I1-I2) ..................... ......... (One)

Where VBE1 is the base-emitter voltage of transistor Q100, VBE2 is the base-emitter voltage of transistor Q103, and I1 and I2 are collector currents of transistors Q100 and Q103, respectively. On the other hand, the base-emitter voltage VBE1-VBE2 of the transistors Q100 and Q103 formed on the same semiconductor substrate and the same geometry can be written as follows.

로써 KT는 절대온도 T가 주어지면 볼츠만 상수 K와 전하량 q에 의해 값이 주어지는 상수이며, IS는 역포화전류를 나타낸 것이다.here

KT is the constant given by the Boltzmann constant K and the amount of charge q given the absolute temperature T, and IS represents the reverse saturation current.

The output voltage difference ΔV0

And I1 + I2 = I, so if I1 and I2 are obtained by the formula (3),

Becomes Therefore, according to the formulas (1) and (4),? Vin can be written as follows.

Therefore, the expression (5) can be written as below for -V0 <ΔV0 <V0.

When it shows by these application | coating, it can show like FIG. That is, by adding the emitter resistor RE, it becomes more linear when the input voltage difference ΔVin becomes larger due to the change in the transfer characteristics of the differential amplifier, and it is possible to reduce the cause of distortion.

In addition, the in-phase noise removal rate (CMRR) can be written as the following equation.

Where I is transistors Q100 and Q103 emitter currents.

Therefore, the resistance in-phase noise removal rate can be increased by the resistor RE to eliminate the cause of the oscillation phenomenon appearing at the output stage. On the other hand, since the feedback is caused by the resistor RE in the differential mode, the differential input resistance becomes large due to the increase in the resistance RE.

The composite video signal output from the high frequency buffer circuit 10 is input to the first low frequency filter 12 and to the first non-conducting channel 16 and the amplifying circuit 32.

The first low frequency filter 12 connects a passive low frequency filter composed of a capacitor C3 to a resistor R3, a capacitor C2, and a resistor R4 to a differential amplifier composed of transistors Q8 and Q9, thereby returning an input terminal and an output terminal through a capacitor C2. It becomes an active low frequency filter

Here, the high frequency signal except the horizontal synchronous signal is cut off by setting the values of the resistor R4 and the capacitor C3, and the horizontal synchronous signal is output so that the waveform shown in FIG. 4 (b) is output from the active low frequency filter.

In the active low frequency filter, the portion composed of the transistors Q12-Q14 serves as a constant current source, and the output of the differential amplifier composed of the transistors Q8 and Q9 outputs the output of the emitter follower using the transistor Q15 of the differential amplifier transistor Q9. By returning to the base, the input impedance of the active low frequency filter is increased, and the transistor Q14 acts as an active load of the transistor Q15.

In addition to the emitter resistor R36 of the transistor Q8 and the emitter resistor R37 of the transistor Q9, transistors Q8 and Q9 functioning as differential amplifiers in the same manner as the high frequency buffer circuit 10 shown in FIGS. The linearity of the motion transmission characteristic of the signal is increased and the in-phase noise cancellation rate is increased, so that a more accurate signal is transmitted to the sample and hold circuit 14.

Accordingly, the sample and hold circuit 14, which receives the waveform of the horizontal synchronization signal as shown in FIG. 4 (b), buffers the output of the differential amplifier composed of the transistors Q19 and Q20 to the base of the transistor Q20, and the transistors Q17 and Q18. And a constant current circuit composed of a resistor R10 is sampled by a sampling signal input to the sampling frequency input terminal 24, the sampling signal being applied to the base of the transistor Q16 to "turn on" the buffer by the switching action of the transistor Q16. Or " off " to output the buffer by charging or discharging capacitor C4. And buffered through a buffer circuit consisting of transistors Q23-Q30 and resistors R11 and R12.

On the other hand, the sampling frequency input terminal 24 receives a sampling signal as shown in FIG. 4C output from the CPU in the horizontal synchronization signal period through the resistor R5 to the base of the transistor Q16.

Therefore, when the sampling signal of FIG. 4C is " high ", the transistor Q16 is turned on, and the collector of the transistor Q16 is brought into the " 0 " state.

Thus, the transistor Q18 constituting the constant current source is in the " off " state, and the buffer constituted by the transistors Q18-Q22 is in the " off " state in which it is not operated, and the voltage layered on the capacitor C4 is transferred through the base of the transistor Q26. The discharge is conducted through the path of the transistor Q24 and the resistor R11 of the constant current circuit composed of Q23 and Q24 and the resistor R11. At this time, however, the discharged current is adjusted very little by adjusting the resistors R8 and R11, so that the voltage change of the capacitor C4 is not large when the sampling signal is in the period of " 1 " as shown in FIG. Do not.

On the other hand, when the sampling signal is in the " o " state, the transistor Q16 is in the " off " state so that the constant current circuit composed of the transistors Q17 and Q18 and the resistor R10 is operated. Done.

Therefore, at this time, the same voltage as the input voltage is output, and the capacitor C4 is charged. The voltage is rapidly charged by setting the value of the capacitor C4 to be large.

Therefore, a waveform as shown in FIG. 4 (d) appears at the base of the transistor Q20.

Therefore, the waveform of FIG. 4 (d) is output to the emitter of transistor Q30 on the output side through the buffer circuit composed of transistors Q23-Q30, and is input to the non-inverting terminal which is the base of transistor Q34 of the first non-crosspass 16. . At the same time, the composite video signal output from the high frequency buffer circuit 10 is input to the base of the transistor Q33 serving as the inverting terminal of the first non-converting channel 16.

The non-inverting / inverting terminals are the same as for the non-inverting (+) and inverting terminals (-) when the operational amplifier is configured as a comparator.

FIG. 4E shows the digital information signal contained in the data line corresponding to the time T5 of FIG. 4A output from the high frequency buffer circuit 10 as described above to invert the first non-converting path 16. The waveform of (a) input to the base of transistor Q33, which is a terminal, and the signal output from the sample-and-hold circuit 14 at the time T5 and input to the transistor Q34, which is a non-inverting input terminal of the first non-crosspass 16 ( Figure b is an enlarged view.

이 되므로 상기 트랜지스터 Q33의 콜렉터 직류레벨은

으로 되고, 따라서 저항 R13을 조정하여 상기 트랜지스터 Q36의 베이스직류 레벨을 조정할 수 있게 된다. 트랜지스터 Q35측도 마찬가지이다.Therefore, the waveform (e) of FIG. 4 (e) input to the base of transistor Q33 and the waveform (f) of FIG. 4e (e) input to the base of transistor Q34 are compared with each other, and the (f) The waveform (e) at the top of the waveform is inverted and outputted to be input to the base of the transistor Q36 constituting the second non-intersection 18. The DC level applied to the base of the transistor Q36 constituting the second non-intersection 18 is set to be equal to the threshold voltage between the base-emitters of the transistors Q36, Q40 and Q41 and the zener voltage of the zener diode ZD2. It is set by the values of the constant current I1 and the resistor R13 flowing through the collector of the transistor Q32 serving as the constant current source of the one non-intersection 16. That is, the direct current flowing through the collector of transistor Q33

Therefore, the collector DC level of the transistor Q33 is

Therefore, the base DC level of the transistor Q36 can be adjusted by adjusting the resistor R13. The same applies to the transistor Q35 side.

Therefore, the second non-integrating furnace 18 is connected to a walter constant current circuit composed of transistors Q37-Q39 through the zener diode ZD1 and the resistor R16 and the zener diode ZD2 and the resistor R17 to the emitters of the differential amplification transistors Q35 and Q36, respectively. At the DC level input to the base of the transistor Q36, the transistors Q40 and Q41 constituting the first drive circuit 20 are conducted so that the output signal of the output terminal 26 is " 0 " By turning off the transistor Q40 and the transistor Q41 for the low pulse, i.e., the upper digital information signal e which is larger than the signal (f) in FIG. 4 (e), the output terminal 26 has a voltage of VBB, The status "1" will be output.

Therefore, a waveform as shown in FIG. 4 (f) is output from the output terminal 26. In addition, the resistor R19 of the first drive circuit 20 is a protection resistor for preventing overcurrent from flowing through the transistor Q40.

On the other hand, the composite video signal input through the input terminal 22 is output to the emitter of the transistor Q3 through the high frequency buffer circuit 10 without distortion and phase difference to the base of the transistor Q44 composed of the amplifying circuit 32. Will enter.

The amplification circuit 32 is composed of a resonant circuit in which capacitor C5 and coil L1 are connected in parallel, a constant current circuit for biasing by transistor Q42, a capacitor C7 for high frequency bypass, and a capacitor C6 for DC blocking.

Therefore, the composite video signal input to the base of transistor Q44 is amplified by transistor Q44, but is resonated by only a resonant circuit composed of capacitor C5 and coil L1 to resonate only the synchronous clock information in FIG. 4A and time T3. Is output to the collector of transistor Q44. That is, a signal resonated and amplified by the resonant circuit has a waveform such as a sine wave having the same frequency as that of the digital synchronous clock, and a power supply voltage is loaded at the DC level of VCC. Will print.

이 되는 VCC/2의 기준전압이 트랜지스터 Q45와 Q46의 베이스에 공급되며, 상기 트랜지스터 Q45, Q46는 차동증폭기로 구성되어 에미터에는 트랜지스터 Q47와 Q48로 구성되는 정전류원이 접속된다.Therefore, the waveform of FIG. 4 (g) cuts off the DC component through the DC blocking capacitor C6 and inputs only the AC component to the base of the transistor Q45 constituting the first comparator 34. The first comparator 34 uses a reference voltage supply circuit composed of resistors R22 and R23 and resistors R24 and R25 having the same resistance value to determine the power supply voltage VCC.

The reference voltage of VCC / 2 is supplied to the bases of the transistors Q45 and Q46, and the transistors Q45 and Q46 are composed of differential amplifiers, and the emitter is connected to a constant current source composed of transistors Q47 and Q48.

Accordingly, the difference signal of the signal input to the bases of the transistors Q45 and Q46 is amplified and outputted. As a result, the inverted source amplification signal of the AC signal inputted to the base of the transistor Q45 is outputted to the collector of the transistor Q45, and the signal is output to the second. It is input to the base of the transistor Q50 constituting the comparator 36. The second comparator 36 connects the zener diodes ZD3 and ZD4 to the emitters of the transistors Q49 and Q50, respectively, the resistors R29 and R30, respectively, and is connected to a Wilson constant current source consisting of transistors Q51-Q53. When the base voltage of Q50 is maximum, the bias voltage is set by adjusting the value of the resistor R26 such that the zener voltage of the zener diode ZD4 and the threshold voltage between the base-emitters of the transistors Q50, Q54, and Q55 are summed. In other words, if the constant current of the collector of transistor Q47 is IO, the DC bias current flowing through the collector of transistor Q45 is IO / 2, and the base DC voltage of transistor Q50 is VCC-IO / 2 x R26.

Therefore, the value of the resistor R26 can be set equal to the predetermined voltage value described above.

Therefore, when the DC voltage as described above is applied to the base of the transistor Q50, the transistors Q54 and Q55 become saturated at the DC voltage.

Therefore, a voltage having a level higher than the base voltage of the transistor Q50 set as described above flows through the base and emitter of the transistor Q50, the zener diode ZD4, the resistor R30, the base and emitter of the transistor Q54, and the base and emitter of the transistor Q55. do.

Accordingly, the base waveform of the transistor Q50 becomes as shown in FIG. 4 (h).

Here, V0 is a DC voltage value equal to the sum of the zener voltage of the zener diode ZD4 and the threshold voltage between each base-actuator of the transistors Q50, Q54 and Q55 by setting the resistance value R26 as described above.

Therefore, as shown in FIG. 4 (h), when the base voltage of the transistor Q50 is lower than the voltage V0, the output transistor Q54 of the second drive circuit 38 is turned off, so that the voltage of the VBB at the output terminal 40 is reduced. When the base voltage of the transistor Q50 reaches V0, the transistors Q54 and Q55 become conductive, so the voltage "0" is output to the output terminal 40 by the pull-up resistor R33.

Here, the resistor R32 is a resistor that prevents overcurrent flowing through the transistor Q54.

Thus, a spherical pulse as shown in Fig. 4 (i) is obtained, which is a synchronous clock which is a digital sync signal in time T3 of Fig. 4 (a).

On the other hand, a composite video signal, i.e., teletext data, is loaded through the input terminal 22. When the packet is input, the second low frequency pulser 42 composed of the resistor R38, the coil L2, and the capacitor C8 is a high frequency color burst. Signal and data synchronizing signal and data signals are cut off, and only the horizontal synchronizing signal passes through the second low frequency filter 42 and is input to the synchronizing separation circuit 44.

Therefore, since the horizontal synchronizing signal is input to the base of the transistor Q56 through the capacitor C9 in the "low" state, the transistor Q56 is brought into a conductive state, and the transistor Q57 is also brought into a conductive state by the voltage applied to the resistor R41.

Therefore, the voltage caused by the resistor R43 conducts the transistor Q58 so that the voltage of the low state is output to the output terminal 46 of the synthetic synchronous separation circuit 44, and the transistor " off " Since the transistors Q57 and Q58 also become " off " state, the voltage of VBB is output to the output terminal 46.

Therefore, the waveform as shown in FIG. 4 (j) is output from the output terminal 46.

As described above, in the present invention, the resistors R34 and R35 are added to the high frequency buffer circuit 10 including the resistors R1 and R2 and the transistors Q1 to Q7 at the input terminal, thereby extending the linearity of the drive transmission characteristics of the buffer circuit and removing the common phase noise. It is possible to deliver a stable signal without phase difference and distortion with respect to the input composite video signal.

In addition, the resistors R36 and R37 are added to the emitters of the transistors Q8 and Q9 of the first low frequency filter 12, and the signal output from the high frequency buffer circuit 10 passes through the low frequency filter composed of the resistors R4 and capacitor C3. For the signal output from the emitter of Q15 and fed back through the Caterpillar C2, the linearity of the drive transmission characteristics of the transistors Q8 and Q9 and the in-phase noise rejection ratio are increased, like the transfer characteristics of the high frequency buffer circuit 10, and the sample and hold are increased. The signal input to the circuit 14 can be accurately transmitted without distortion.

In addition, by using the transistors Q37-Q39 which are the constant current circuits with the zener diodes ZD1 and ZD2 of the second non-intersection 18, the power consumption can be reduced by reducing the current consumption for driving the first drive circuit 20. Stabilization against off-set fluctuations can be achieved.

In addition, the synchronous clock can be separated by inputting the high frequency digital synchronous signal without distortion and phase difference, increasing the base DC level of the transistor Q50, and improving the supply voltage supply margin by applying a constant current circuit composed of the transistors Q51-Q53. In addition, cost and labor savings can be achieved by integrating digital information signal separation, digital synchronization signal separation, and composite synchronization signal separation.

Claims (1)

In a digital information signal processing integrated circuit of character multicasting, a differential amplifier transistor (Q3) consisting of differential amplifiers (Q1) (Q2) and resistors (R34) (R35) connected to emitters of these transistors, respectively. The output signal is fed back to the base of the transistor Q2, the high frequency buffer circuit 10, the resistors connected to the differential amplifying transistors Q8 and Q9 and emitters of the transistors Q8 and Q9. R36) A first low frequency filter 12 that sequentially amplifies the signal input to the differential amplifier composed of (R37) and filters only the horizontal synchronization signal, and inputs at the same timing as the signal output from the first low frequency filter 12 A sample and hold circuit 14 for sampling and outputting a horizontal synchronous signal output from the first low frequency filter 12 by inputting a sampling pulse and switching the sampling pulse, and an output of the sample and hold circuit 14. Signal and remind A first non-conducting path 16 which compares the composite video signal that is the output signal of the high frequency buffer circuit 10 and outputs the digital information in the composite video signal differently and simultaneously loads the digital information signal at a predetermined DC level and outputs the digital information signal; And a first drive circuit 20 for outputting the digital information signal at a predetermined level according to the output of the comparator, and a first drive circuit according to the DC level and the digital information signal outputted from the first non-intersection 16. 20 is configured to drive differential transistors Q35 and Q36 so that the emitters of the transistors Q35 and Q36 have a zener diode ZD1, a resistor R16, a zener diode ZD2, and a resistor, respectively. A second comparison circuit 18 connected to R17, an amplification circuit 32 for resonating and amplifying only a digital synchronization signal of the composite video signal, and the amplified digital synchronization signal to be output at a predetermined DC level. Is a first comparator 34, a second comparator 36 which removes a signal above the predetermined DC level and outputs only a signal below a predetermined DC level, and a predetermined output from the second comparator 36. A second drive circuit 38 which is conducted at a DC level, is " off " at a voltage below the predetermined DC level, and reproduces a synchronous clock pulse of a predetermined level, and a second low frequency filter which passes only a horizontal synchronous signal of the composite video signal; (42), and a synchronizing separation circuit (44) only as a switching circuit for outputting a pulse of a predetermined level by "turning off" only the horizontal synchronization signal.

Images