KR900003076B1 - Dividing circuit for television composite video signal - Google Patents

Abstract

The circuit includes a first and a second high frequency buffers (10,20) having high input impedance for transmitting high frequency imput video signal with no phase difference and no distortion, a first low pass filter (12) for passing the horizontal synchronous signal and for blocking high frequency information signal, a first drive circuit (20) driven by output signal of a second comparator (18) for modulating digital information siggnal into a pulse with a certain level, a second driving circuit (38) driven by a certain AC level of fourth comparator (36) for regenerating a synchronous clock pulse, and a second low pass filter (42) for passing the houizontal synchronous signal of the synthesized video signal.

Description

Integrated circuit for separating high frequency digital information signal and synchronizing high frequency digital signal included in composite video signal

1 is a block diagram of composite video data in teletext broadcasting.

2 is a block diagram of the present invention.

3 is a circuit diagram of an embodiment incorporating the block diagram of FIG. 2 in accordance with the present invention.

4 is an operational waveform diagram of each part of the embodiment according to the invention of FIG. 3;

* Explanation of symbols for main parts of the drawings

10: first high frequency buffer circuit 12: first low frequency filter

14: sample and hold circuit 16: first comparison circuit

18: second comparison circuit 20: first drive circuit

30: second high frequency buffer circuit 32: amplification circuit

34: third comparison circuit 36: fourth comparison circuit

38: second drive circuit 42: second low frequency filter

44: synthetic synchronous separation circuit

The present invention relates to an integrated circuit for high frequency digital information signal separation, composite synchronous signal separation, and high frequency digital synchronization signal separation included in a composite video signal.

In general, when receiving text broadcasting information using a television receiver such as teletext, digital information is included for special information processing among received video signals, and digital information signal and basic clock signal for processing the information. For synchronization, digital synchronization signal and composite synchronization signal of specific frequency are loaded.

The composite video signal containing the character or figure information used in the teletext includes a horizontal synchronization period T1, a color burst signal period T2, and a data line T5 as shown in FIG. It consists of a synchronization signal period T3 consisting of a synchronous clock and a framing code and a data packet period T4 containing various digital information signals. Therefore, a teletex system of a television receiver receiving text multicasting needs a circuit that separates all digital information signals and synchronization signals on the data line and separates one information signal without loss in a highly stable manner. Done.

However, in the conventional method, as the transmission frequency is increased, accurate data information signal separation and digital synchronization signal cannot be separated, and there is a drawback in that the current consumption is large, the margin of voltage margin and the signal external rate are large.

Accordingly, an object of the present invention is to accurately separate the digital information signal separation and the digital synchronization signal contained in the text broadcasting data packet, to simultaneously separate the synthetic synchronization signal, and to reduce the current consumption of the integrated circuit. The present invention provides an integrated circuit having a margin for power margin.

A first high frequency buffer circuit having a high input impedance for outputting the composite video signal of the high frequency input in phase without phase difference and outer coefficient; and filtering a horizontal synchronization signal from an output of the first high frequency buffer circuit, A sample end for generating a DC-type signal from which the horizontal synchronous signal is removed by a first low frequency filter to cut off and a horizontal synchronous signal output from the first low frequency filter to a sampling signal supplied from a CPU. A first comparison circuit for separating the digital information signal by comparing a hold circuit, an output of the sample and hold circuit, and an output of the first high frequency buffer circuit, and a first drive circuit by inputting an output to the first non-converter; A second comparison circuit for determining a drive saturation DC level of the digital signal; A first drive circuit for outputting a complementary signal as a pulse of a predetermined level, a high impedance second high frequency buffer circuit for outputting the composite video signal of a high frequency input without an external rate and a phase difference, and an output of the second high frequency buffer circuit An amplification circuit for resonating and amplifying only a digital synchronizing signal, a third comparison circuit carrying the amplification circuit output at a predetermined DC level, and outputting the output of the third comparison circuit to remove a signal higher than the DC level; A fourth comparison circuit for outputting only a signal of a DC level or less, a second drive circuit driven at a DC level of the fourth comparison circuit to reproduce a synchronous clock pulse, and the composite video signal being input to pass only a horizontal synchronization signal. The horizontal low frequency signal is separated from the output of the second low frequency filter and the second low frequency filter and output as a pulse signal. Characterized by consisting of a sync separation circuit.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a digital information signal separation integrated circuit of a data line included in a composite video signal of a character multiplexing broadcasting according to the present invention. A first high frequency buffer circuit 10 having a high input impedance to be output, and a first low frequency filter 12 filtering horizontal synchronization signals at the output of the first high frequency buffer circuit 10 and blocking high frequency information signals And a sample-and-hold circuit 14 for generating a DC-type signal from which the horizontal synchronization signal is removed by a sampling signal supplied from a central processing unit (CPU) to the horizontal synchronization signal output from the first low frequency filter 12. ) And a first comparison circuit 1 for separating the digital information signal by comparing the output of the sample and hold circuit 14 with the output of the first high frequency buffer circuit 10. 6) and a second comparison circuit 18 for inputting the output of the first comparison circuit 16 to determine the drive saturation DC level of the first drive circuit and an output signal of the second comparison circuit 18. And a first drive circuit 20 for outputting the separated digital information signal as a pulse of a predetermined level, and a high impedance second high frequency buffer circuit 30 for outputting the synthesized video signal of a high frequency input without an external rate and a phase difference. ), A third comparison circuit which outputs the amplification circuit 32 by resonating and outputting only the digital synchronization signal at the output of the second high frequency buffer circuit 30, and outputs the output of the amplifier circuit 32 at a predetermined DC level. A fourth comparison circuit 36 for inputting the circuit 34 and the output of the third comparison circuit 34 to remove the signal above the DC level and outputting only the signal below the DC level; and the fourth comparison circuit. Synchronous clock driven at DC level of 36 A second drive circuit 38 for reproducing lump pulses, a second low frequency filter 42 for inputting the composite video signal only to pass a horizontal synchronization signal, and a horizontal synchronization signal at the output of the second low frequency filter 42 It is characterized by consisting of a synthetic synchronous separation circuit 44 for separating and outputting a pulse signal.

Accordingly, in the present invention, when a composite video signal carrying data is input through the input terminal 22, the first high frequency buffer circuit 10 outputs a high frequency digital information signal in the composite video signal without an external factor and a phase difference. A buffer circuit having Accordingly, the first high frequency buffer circuit 10 outputs a signal having the same waveform as the composite video signal input to the input terminal 22 to the first low frequency filter 12 and simultaneously to the first comparison circuit 16. do.

The first low frequency filter 12 passes only a horizontal synchronous signal that becomes a low frequency of the composite video signal input through the first high frequency buffer circuit 10 and blocks other high frequency components. Then, the sample and hold circuit 14 inputs a sampling pulse to the input terminal 24 from a central processing unit (CPU) which outputs a pulse only during the horizontal synchronizing time of the composite video signal, and the switching operation is performed by the sampling pulse. The horizontal synchronization signal outputted from the first low frequency filter 12 is received and output as an appropriate type of signal.

Accordingly, the first comparison circuit 16 inputs the output signal to the sample and hold circuit 14 and the composite video signal output from the first high frequency buffer circuit 10 to compare the two signals. A signal larger than the output signal of the hold circuit 14, that is, a digital information signal is output. In addition, the second comparison circuit 18 inputs a signal in which the digital information signal output from the second comparison circuit 18 is negatively input to the input direct current level set by the first comparison circuit 16, and then at the DC level. The first drive circuit 20 is turned on and turned off for an input signal lower than the DC level so as to separate only the digital information signal having a predetermined level. Therefore, the first drive circuit 20 outputs the digital information signal shaped by a pulse of a predetermined level by performing an on / off operation according to the digital information signal output from the second comparator 18.

In addition, when the composite video signal is input through the input terminal 22, the second high frequency buffer circuit 30 having a high input impedance performs a function of accurately reproducing the input composite video signal in magnitude and phase. The reproduced composite video signal is resonated by a digital synchronizing signal in a data packet of the composite video signal by an amplifying circuit 32 having a resonant circuit so that only the digital synchronizing signal is amplified and output.

The detected digital synchronization signal is input to the third comparison circuit 34 to output the amplified digital synchronization signal on a predetermined DC level. The output signal is input to the fourth comparison circuit 36. It is used as a bias voltage to saturate the second drive circuit 38 at a DC level. Accordingly, the second drive circuit 38 is saturated and conducting to a voltage higher than the DC level, thereby obtaining an output voltage of "0" level, and the second drive circuit 38 to a voltage smaller than the DC level. By turning off, the output voltage of " 1 " level is obtained, so that the digital synchronization signal can be output separately.

On the other hand, the horizontal synchronous signal in the data packet of the composite video signal input to the input terminal 22 is filtered by the second low frequency filter 42, and the synthesized synchronous signal other than the horizontal synchronous signal is synthesized. Isolate from 3 is a circuit diagram of an embodiment of a circuit diagram of a circuit for separating digital information signals and digital synchronization signals included in the composite video signal according to the present invention of FIG. 2, wherein R1-R35 is a resistor, and C1- C10 is a capacitor, Q1-Q65 is a transistor, D1 is a diode, ZD1-ZD4 is a zener diode, and VCC and VBB are power supply voltages.

In the figure, a portion composed of capacitor C1, resistors R1, R2 and transistors Q1-Q7 corresponds to the first low frequency buffer circuit 10, and a portion composed of resistors R3, R4, R6, capacitors C2, C3, and transistors Q16-Q15 A portion corresponding to the first low frequency filter 12 and composed of resistors R5, R7, R8, R10-R12, capacitors C4 and transistors Q16-Q30 correspond to the sample-and-hold circuit 14, and resistors R9, capacitors C4 and The portion composed of R13-R15, diode D1, and transistors Q31-Q34 corresponds to the first comparison circuit 16, and the portion composed of resistors R16, R17 transistor Q35-Q39 and zener diodes ZD1, ZD2 is the second comparison circuit 18. ) And a portion composed of resistors R18-R20 and transistors Q40 and Q41 correspond to the first drive circuit 20.

In the figure, the portion composed of the capacitors C5 resistors R21-R23 and the transistors Q42-Q49 corresponds to the second high frequency buffer circuit 30, and the portion composed of the capacitors C6-C8, the coil L1, and the transistors Q50, Q51 is an amplification circuit (32). The portion composed of resistors R24-R30 and transistors Q52-Q55 corresponds to the third comparison circuit 34, and the portion composed of resistors R31, R32 zener diodes ZD3-ZD4 and transistors Q56-Q60 compares to the third. The portion composed of the resistors R33-R35 and the transistors Q61, Q62 corresponds to the second drive circuit 38, and the portion composed of the resistor R36, the coil L2 and the capacitor C9 corresponds to the circuit 34, and the second low frequency filter 42 ) And a portion composed of resistors R37-R43, capacitor C10, and transistors Q63-Q65 correspond to the synthetic synchronous separation circuit 44.

4 is a view showing an operation waveform of each part of FIG. 3 according to an embodiment of the present invention.

Hereinafter, an embodiment according to the present invention of FIG. 3 will be described in detail with reference to the waveform diagram of FIG. When the composite video signal as shown in FIG. 4 (a) is input to the input terminal 22, it is input to the base of the transistor Q1 through the DC blocking capacitor C1 of the first high frequency buffer circuit 10. FIG. Transistors Q1 and Q2 of the first high frequency buffer circuit 10 perform the function of an automatic amplifier, and transistors Q6, Q7, Q4 and Q5 each have the function of a constant current circuit, and the transistor Q5 constitutes a transistor Q2. Transistor Q7 acts as the active load of transistor Q3. Therefore, the first high frequency buffer circuit 10 is composed of a feedback circuit in which the output of the differential amplifier composed of the transistors Q1 and Q2 is input to the base of the transistor Q3, and the output thereof is again input to the base of the transistor Q2. Therefore, the differential amplifier of the first high frequency buffer circuit 10 has a high input impedance by the feedback action, and thus outputs the input signal as it is up to 4MHZ without an external rate or phase difference even when the frequency of the input composite video signal is high, and even at 5MHZ. Outputs a composite video signal loaded with a digital information signal without any problem in separating the digital information signal.

The composite video signal output from the first high frequency buffer circuit 10 is input to the first low frequency filter 12 and simultaneously to the first comparator 16. The first low frequency filter 12 connects a passive low frequency filter composed of a capacitor C3 to a resistor R3, a capacitor C2, and a resistor R4 to a differential amplifier composed of transistors Q8 and Q9 to feed back an input terminal and an output terminal through a capacitor C2. It becomes the active low frequency filter of the difference. Here, the high frequency signal except the horizontal synchronous signal is cut off by setting the value of the resistor R4 or the capacitor C3, and the horizontal synchronous signal is output so that the waveform of the fourth (b) degree is output from the first low frequency filter 12.

In the first low frequency filter 12, a portion composed of transistors Q12-Q14 serves as a constant current source, and an output of the differential amplifier composed of transistors Q8 and Q9 is output through an emitter follower transistor Q15. By simultaneously feeding back the transistor Q9 of the differential amplifier, the input impedance of the first low frequency filter 12 is increased, and the transistor Q14 acts as an active load of the transistor Q15.

Accordingly, the waveform of the horizontal synchronous signal such as the fourth (b) diagram outputting the first low frequency filter 12 is input to the sample and hold circuit 14, and the sample and hold circuit 14 is connected to the transistors Q19 and Q20. A differential amplifier, a buffer of transistors Q21 and Q22 for returning the output of the differential amplifier to the base of transistor Q20, a constant current circuit composed of transistors Q17, Q18 and resistor R10, and switching of the constant current circuit to transistor Q16. A capacitor C4 which controls by action to turn the buffer on or off to charge or discharge the output of the buffer, and a buffer circuit composed of transistors Q23-Q30 and resistors R11 and R12. On the other hand, a sampling signal such as the fourth (c) diagram outputted in the horizontal synchronous signal period output from the central processing unit is input to the input terminal 24 through the resistor R5 to the base of the transistor Q16. Therefore, when the sampling signal of Fig. 4 (c) is " high, " the transistor Q16 is in the conduction state and the collector of the transistor Q16 is in the " 0 " state. As a result, the transistor Q18 constituting the constant current source is turned off, the buffer composed of the transistors Q18-Q22 is turned off, and the voltage charged in the capacitor C4 is transferred to the transistors Q23 and Q24 through the base of the transistor Q26. And a transistor Q24 and a resistor R11 in the constant current circuit constituted of the resistor R11. However, at this time, the discharged current is adjusted very weakly by adjusting the resistors R8 and R11, so that the voltage variation of the capacitor C4 is not increased when the sampling signal is in the period of " 1 " .

On the other hand, when the sampling signal as in the fourth (c) is in the " 0 " state, the transistor Q16 is turned off, so that the constant current circuit composed of the transistors Q17 and Q18 and the resistor R10 operates, and thus, the transistors Q18-Q22. The buffer that is configured will also work. Therefore, at this time, the same voltage as the input voltage is output, and the capacitor C4 is charged. The voltage is rapidly charged by setting a large value of the capacitor C4. Therefore, the same waveform as that of the fourth diagram (d) appears at the base of the transistor Q20.

)으로 되고, 따라서 저항 R13을 조정하여 상기 트랜지스터 Q36의 베이스 직류레벨을 조절할 수 있게 된다. 트랜지스터 Q35측도 마찬가지이다. 따라서 제 2 비교회로(18)는 차동증폭용 트랜지스터 Q35와 Q36의 에미터에 각각 제어다이오드 ZD1과 저항 R16 및 제너다이오드 ZD2와 저항 R17을 통해 트랜지스터 Q37-Q39로 구성되는 윌슨정전류 회로에 접속한 구성으로 되며, 트랜지스터 Q36의 베이스에 입력하는 직류레벨에서 제 1 드라이브회로(20)를 구성하는 트랜지스터 Q40과 Q41를 도통시켜 출력단자(26)의 출력신호를 "0"으로 하고, 상기 직류레벨 보다 낮은 펄스 즉, 제 4(e) 도의 b신보다 큰 상부의 디지탈정보신호 a에 대해서는 트랜지스터 Q40과 트랜지스터 Q41을 오프시킴으로서 출력단자(26)에는 R20을 통해 VBB의 전압 즉 "1" 상태가 출력하게 된다. 따라서 제 4(f) 도와 같은 파형이 출력단자(26)에서 출력한다. 또한 제 1 드라이브회로(20)의 저항 R19는 트랜지스터 Q40에 과전류가 흐르는 것을 방지하기 위한 보호저항이다.The waveform of FIG. 4 (d) is output to the emitter of the transistor Q30 which is the output through the buffer circuit composed of the transistors Q23 to Q30, and this signal is the ratio of the base of the transistor Q33 constituting the first comparison circuit 16. It is input to reverse terminal. At the same time, the composite video signal output from the first high frequency buffer circuit 10 is input to the base of transistor Q34, which is an inverting terminal of the first comparison circuit 16. The inversion of the first comparison circuit 16 outputted from the first high frequency buffer circuit 10 by the digital information signal carried on the data line corresponding to the time T5 in FIG. 4 (e) or 4 (a). The waveform of a input to the base of transistor Q34, which is an input terminal, and the signal b output from the sample and hold circuit 14 at the time T5 and input to the transistor Q33, which is a non-inverting input terminal of the first comparison circuit 16, at time T5. Is a drawing shown by expanding. Thus, the waveform of b of FIG. 4 (e) input to the base of transistor Q33 and the waveform of a of FIG. 4 (e) input to the base of transistor Q34 are compared with each other and the collector of transistor Q33 is on top of the b waveform. The a waveform is inverted and output, and is input to the base of the transistor Q36 constituting the second comparison circuit 18. The DC level applied to the base of the transistor Q36 constituting the second comparison circuit 18 is set to be equal to the threshold voltage between the base emitters of the transistors Q36, Q40 and Q41 and the zener voltage of the zener diode ZD2. It is set by the values of the constant current I1 and the resistor R13 flowing through the collector of the transistor Q32 serving as the constant current source of (16). That is, since the DC current flowing through the collector of transistor Q33 becomes I1 / 2, the collector DC level of transistor Q33 is (

Therefore, the base DC level of the transistor Q36 can be adjusted by adjusting the resistor R13. The same applies to the transistor Q35 side. Therefore, the second comparison circuit 18 is connected to the Wilson constant current circuit composed of transistors Q37-Q39 through the control diode ZD1 and the resistor R16 and the zener diode ZD2 and the resistor R17 to the emitters of the differential amplification transistors Q35 and Q36, respectively. At the DC level input to the base of the transistor Q36, the transistors Q40 and Q41 constituting the first drive circuit 20 are turned on so that the output signal of the output terminal 26 is " 0 " In other words, the transistor Q40 and the transistor Q41 are turned off for the upper digital information signal a larger than b in FIG. 4 (e), so that the output terminal 26 outputs a voltage of VBB, that is, a "1" state through R20. . Therefore, the same waveform as that of the fourth diagram (f) is output from the output terminal 26. In addition, the resistor R19 of the first drive circuit 20 is a protective resistor for preventing overcurrent from flowing through the transistor Q40.

In addition, when the composite video signal such as the fourth (a) diagram is input through the input terminal 22, DC is blocked by the capacitor C5, and only the AC component is input to the second high frequency buffer circuit 30.

The second high frequency buffer circuit 30 is a differential amplifier composed of transistors Q42 and Q43 and constitutes a constant current source with transistors Q44 and Q45, and the transistor Q45 acts as a dynamic load of the transistor Q43. In addition, a portion consisting of transistors Q47, Q48, and Q49 also becomes a constant current source, transistor Q47 becomes a current source of a differential amplifier consisting of transistors Q42 and Q43, and transistor Q46 sets the output of the differential amplifier as an emitter follower. By feedback to the base of transistor Q43, which is the input of the differential amplifier, the second high frequency buffer circuit 30 acts as a buffer amplifier. Accordingly, the second high frequency buffer circuit 30 has a high input impedance and improves the external power phase difference according to the frequency characteristic of the input signal.

Therefore, the composite video signal input through the input terminal 22 is outputted through the second high frequency buffer circuit 30 to the emitter of the transistor Q46 without phase difference and phase difference, and thus the base of the transistor Q50 constituting the amplifying circuit 32. Will be entered. The amplification circuit 32 is composed of a resonant circuit composed of parallel connection of capacitors C6 and L1, a constant current circuit for biasing by transistor Q51, a capacitor C8 for high frequency bypass, and a capacitor C7 for DC blocking. Therefore, the composite video signal input to the base of transistor Q50 is amplified by transistor Q50, but is amplified by resonating only the synchronous clock information at time T3 of FIG. 4 (a) by a resonant circuit composed of capacitor C6 and coil L1. Output to the collector of transistor Q50. At this time, the signal resonated and amplified by the resonant circuit is outputted from the collector of the transistor Q50 as shown in FIG. 4 (g) as a waveform such as a sine wave having the same frequency as the digital synchronous clock is loaded at the DC level of the power supply voltage VCC.

Therefore, the waveform in FIG. 4 (g) is blocked by the DC blocking capacitor C7, and only the AC component is inputted to the base of the transistor Q52 constituting the third comparison circuit 34. FIG. The third comparison circuit 34 uses a reference voltage supply circuit composed of resistors R24 and R25 and resistors R26 and R27 having the same resistance value so that the reference voltage of VCC / 2, which is 1/2 of the power supply voltage VCC, is the transistor Q52. And Q53, these two transistors Q52 and Q53 are composed of differential amplifiers, and the emitter is connected to a constant current source consisting of transistors Q54 and Q55. Accordingly, the difference signal of the signal input to the bases of the transistors Q52 and 53 is amplified and outputted. As a result, the inverted amplified signal of the AC signal inputted to the base of the transistor Q52 is outputted to the collector of the transistor Q52 and the fourth comparison circuit 36 ) Is input to the base of transistor Q57.

The fourth comparison circuit 36 connects the zener diodes ZD3 and ZD4 to the emitters of the transistors Q56 and Q57, connects the resistors R31 and R32 respectively, and is connected to a Wilson constant current source composed of transistors Q58-Q60. When the base voltage of the transistor Q57 is maximum, the bias voltage is set by adjusting the value of the resistor R28 to be the sum of the zener voltage of the zener diode ZD4 and the threshold hold voltage of the transistors Q57, Q61, and Q62. In other words, if the constant current of the collector of transistor Q54 is IO, the DC bias current flowing through the collector of transistor Q52 is IO / 2, and the base DC voltage of transistor Q57 is VCC-IO / 2 · R28. Therefore, the value of the resistor R28 can be set equal to the predetermined voltage value described above. When the DC voltage as described above is applied to the base of the transistor Q57, the transistors Q61 and Q62 are saturated at this DC voltage and are brought into a conductive state. Therefore, a voltage having a level higher than the base voltage of the transistor Q57 set as described above flows through the base and emitter of the transistor Q57, the zener diode ZD4, the resistor R32, the base and emitter of the transistor Q61, and the base and emitter of the transistor Q62. do. Therefore, the waveforms of the base and the emitter of transistor Q57 are the same as in the fourth (h) diagram. Here, VO is a DC voltage value equal to the sum of the Zener voltage of Zener diode ZD4 and the threshold hold voltage between each base emitter of transistors Q57, Q61, and Q62 as described above. At this time, as shown in FIG. 4 (h), when the base voltage of the transistor Q57 is lower than the VO voltage, the output transistor Q62 of the second drive circuit 38 is turned off, and thus the output terminal 40 has a voltage of VBB. When the base voltage of the transistor Q57 becomes VO, the transistors Q61 and Q62 become conductive, so a voltage of zero is output to the output terminal 40 by the pull-up resistor R35. Here, the resistor R34 is a resistor that prevents overcurrent flowing through the transistor Q40. Therefore, the output terminal 40 obtains a rectangular pulse equal to the fourth (i) degree, which becomes a synchronous clock which is a digital synchronization signal in time T3 of the fourth (a) degree.

On the other hand, when a composite video signal, i.e., a data packet carrying teletext data, is input through the input terminal 22, a high frequency color burst signal is generated by a second low frequency filter 42 composed of a resistor R36, a coil L2, and a capacitor C9. And the data synchronizing signal and the data signals are cut off, and only the horizontal synchronizing signal passes through the second low frequency filter 42 to be input to the synthesis synchronizing separation circuit 44. Therefore, since the horizontal synchronization signal is input to the base of the transistor Q63 in the "low" state, the transistor Q63 is brought into a conducting state and is brought into the transistor Q64 or the conducting state by the voltage applied to the resistor R39. At this time, the voltage caused by the resistor R41 becomes the conductive state of the transistor Q64. At this time, the voltage of the resistor R41 conducts the transistor Q65 so that the output terminal 46 of the synthetic synchronous separation circuit 44 outputs a "low" voltage, and the transistor Q63 is turned off in a period other than the horizontal synchronization period. Therefore, the transistors Q64 and Q65 are turned off and the voltage of VBB is output to the output terminal 46. Therefore, the waveform like the fourth (j) diagram is output from the output terminal 46.

As described above, in the present invention, the first drive circuit 20 is formed by using the second comparison circuit 18 and the transistors Q37-Q39 which are constant current circuits with the zener diodes ZD1 and ZD2 as the second comparison circuit 18. This reduces the current consumption for driving, thereby reducing the power consumption and stabilizing the offset variation. In addition, by using a high-frequency buffer amplifier consisting of resistors R1, R2 and transistors Q1-Q7 at the input stage, the input composite video signal can be stably input without phase difference and external coefficient.

In addition, the synchronous clock can be separated by inputting the high frequency digital synchronous signal without external factor and phase difference, and the power supply margin can be improved by increasing the base DC level of transistor Q57 and applying a constant current circuit composed of transistors Q58-Q60. At the same time, the power consumption is reduced by reducing the current consumption. In addition, by integrating digital information signal separation, digital synchronization signal separation function, and synthetic synchronous signal separation function into one system, PCB area reduction, cost, and airborne savings can be obtained.

Claims (1)

An integrated circuit for high frequency digital information signal separation, a composite synchronous signal separation, and a digital synchronous signal separation included in a composite video signal, the integrated circuit having a high input impedance for outputting the synthesized high frequency input video signal in phase without phase difference and outer coefficient. A first low frequency filter 12 for filtering a horizontal synchronous signal from an output of the first high frequency buffer circuit 10, the first high frequency buffer circuit 10, and cutting off a high frequency information signal, and the first low frequency filter A sample-and-hold circuit 14 for generating a DC-type signal from which the horizontal synchronous signal is removed by the sampling signal supplied from the CPU, the horizontal synchronous signal outputted from (12), and the sample and hold; A first comparison circuit 16 for separating the digital information signal by comparing the output of the circuit 14 with the output of the first high frequency buffer circuit 10, and the first comparison circuit 1 The second comparison circuit 13 for inputting the output of 6) to determine the drive saturation DC level of the first drive circuit and the digital information signal driven and separated by the output signal of the second comparison circuit 18 are predetermined. A first drive circuit 20 for outputting a pulse of a level, a high impedance second high frequency buffer circuit 30 for outputting the composite video signal of a high frequency input without an external rate and a phase difference, and the second high frequency buffer circuit An amplifying circuit 32 for resonating and amplifying only the digital synchronizing signal at the output of 30; a third comparing circuit 34 for outputting the amplifying circuit 32 output at a predetermined DC level; A fourth comparison circuit 36 for inputting the output of the comparison circuit 34 to remove signals above the DC level and outputting only signals below the DC level; and driving at the DC level of the fourth comparison circuit 36. Second to reproduce a synchronous clock pulse A drive circuit 38, a second low frequency filter 42 for inputting the composite video signal and passing only a horizontal synchronization signal, and a horizontal synchronization signal separated from an output of the second low frequency filter 42 are output as a pulse signal. Integrated circuit for high frequency digital information separation, composite synchronization signal separation and digital synchronization signal separation included in the composite video signal, characterized in that composed of a composite synchronous separation circuit (44).

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