KR880006909A - Integrated circuit for digital information signal separation and digital synchronization signal separation included in composite video signal - Google Patents

Integrated circuit for digital information signal separation and digital synchronization signal separation included in composite video signal Download PDF

Info

Publication number
KR880006909A
KR880006909A KR860009665A KR860009665A KR880006909A KR 880006909 A KR880006909 A KR 880006909A KR 860009665 A KR860009665 A KR 860009665A KR 860009665 A KR860009665 A KR 860009665A KR 880006909 A KR880006909 A KR 880006909A
Authority
KR
South Korea
Prior art keywords
circuit
voltage
signal
composite video
video signal
Prior art date
Application number
KR860009665A
Other languages
Korean (ko)
Other versions
KR890004062B1 (en
Inventor
신명철
김영생
Original Assignee
강진구
삼성반도체통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 강진구, 삼성반도체통신 주식회사 filed Critical 강진구
Priority to KR1019860009665A priority Critical patent/KR890004062B1/en
Publication of KR880006909A publication Critical patent/KR880006909A/en
Application granted granted Critical
Publication of KR890004062B1 publication Critical patent/KR890004062B1/en

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/04Synchronising

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Amplifiers (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

내용 없음No content

Description

합성 비디오 신호에 포함되어 있는 디지탈 정보 신호 분리 및 디지탈 동기 신호 분리용 집적회로Integrated circuit for digital information signal separation and digital sync signal separation included in composite video signal

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 집적회로의 블럭도.1 is a block diagram of an integrated circuit of the present invention.

제2도는 본 발명에 따른 제1도의 블럭도의 구체회로도.2 is a detailed circuit diagram of the block diagram of FIG. 1 according to the present invention;

제3도는 제2도의 구체회로도의 각부의 동작파형도.3 is an operational waveform diagram of each part of the concrete circuit diagram of FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 버퍼회로 2 : 저주파 필터1: Buffer circuit 2: Low frequency filter

3 : 샘플링회로 4 : 기억회로3: sampling circuit 4: memory circuit

5 : 임피던스 버퍼회로 6 : 비교회로5: impedance buffer circuit 6: comparison circuit

7 : 제1드라이브회로 8 : 증폭기7: first drive circuit 8: amplifier

9 : 공진회로 10 : 비교 전압 발생회로9 resonant circuit 10 comparison voltage generating circuit

11 : 비교기 12 : 제2드라이브회로11: comparator 12: second drive circuit

13 : 정전압 발생회로13: constant voltage generating circuit

Claims (1)

합성 비디오 신호에 포함된 디지탈 정보 신호 및 디지탈 동기 신호를 분리하는 집적회로에 있어서, 입력 신호의 증폭을 위한 버퍼회로(1)와, 입력된 신호의 고주파 부분을 제거하는 능동형 저주파 필터(2)와, 여파된 신호중 굴곡으로 나타나는 저주파의 동기 신호 부분을 제거하는 샘플링회로(3)와, 상기 샘플링회로(3)에서 출력하는 전압을 비교 전압으로 기억하는 기억회로(4)와, 상기 기억된 비교 전압을 적절한 레벨의 전압으로 변환하고 샘플링 기간동안 상기 비교 전압을 유지하기 위한 임피던스 버퍼회로(5)와, 상기 기억회로로부터 입력하는 상기 비교 전압과 비디오 신호의 데이터와 비교하는 비교회로(6)와, 비교된 신호를 정당한 레벨의 데이타로 출력하는 제1드라이브회로(7)와, 디지탈 동기 신호 분리를 위해 합성 비디오 신호를 증폭하기 위한 증폭기(8)와, 합성 비디오 신호중 특정 주파수인 동기 신호를 선별하기 위한 공진회로(9)와, 상기 공진회로 출력을 비교하기 위한 비교 전압을 발생하는 비교 전압 발생회로(10)와, 상기 비교 전압에 따라 공진출력을 비교하는 비교기(11)와, 상기 비교된 출력을 적당한 레벨의 구형파로 출력하는 제2드라이브회로(12)와, 저항(R30)(R31)(R32)와 트랜지스터(Q47)(Q53)(Q54)로 구성된 정전류원과 다이오우드접속 트랜지스터(Q45)(Q46)(Q48-Q52)에 의해 소정의 일정 전압을 상기 비교기(6)(11)에 공급하고 저항(R33-R35)와 트랜지스터 Q55로 구성된 정전류회로의 상기 저항 R35의 전압 강하로 일정전압을 제1,2드라이브회로(7),(12)에 공급하는 정전압 발생회로(13)로 구성됨을 특징으로 하는회로.An integrated circuit that separates a digital information signal and a digital synchronization signal included in a composite video signal, comprising: a buffer circuit for amplifying an input signal, an active low frequency filter 2 for removing a high frequency portion of an input signal, and A sampling circuit (3) for removing a portion of the low frequency synchronizing signal appearing in the filtered signal, a storage circuit (4) for storing the voltage output from the sampling circuit (3) as a comparison voltage, and the stored comparison voltage An impedance buffer circuit 5 for converting the voltage into a voltage of an appropriate level and maintaining the comparison voltage for a sampling period, a comparison circuit 6 for comparing the comparison voltage input from the memory circuit with data of a video signal; A first drive circuit (7) for outputting the compared signals as legitimate levels of data, and an amplification for amplifying a composite video signal for digital synchronization signal separation; 8, a resonant circuit 9 for selecting a synchronization signal of a specific frequency from the composite video signal, a comparison voltage generation circuit 10 for generating a comparison voltage for comparing the output of the resonant circuit, and the comparison voltage Comparator 11 for comparing the resonant output, second drive circuit 12 for outputting the compared output as a square wave of an appropriate level, resistors R 30 , R 31 , R 32 and transistors A predetermined constant voltage is supplied to the comparators 6 and 11 by a constant current source consisting of Q 47 ), Q 53 , and Q 54 , and a diode connected transistor Q 45 , Q 46 , and Q 48 -Q 52 . And a constant voltage generator circuit for supplying a constant voltage to the first and second drive circuits 7 and 12 by the voltage drop of the resistor R 35 of the constant current circuit composed of the resistors R 33 to R 35 and the transistor Q 55 . 13) a circuit, characterized in that consisting of. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019860009665A 1986-11-15 1986-11-15 Integral circuits for separating digital signals from complete video signals KR890004062B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019860009665A KR890004062B1 (en) 1986-11-15 1986-11-15 Integral circuits for separating digital signals from complete video signals

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019860009665A KR890004062B1 (en) 1986-11-15 1986-11-15 Integral circuits for separating digital signals from complete video signals

Publications (2)

Publication Number Publication Date
KR880006909A true KR880006909A (en) 1988-07-25
KR890004062B1 KR890004062B1 (en) 1989-10-18

Family

ID=19253405

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860009665A KR890004062B1 (en) 1986-11-15 1986-11-15 Integral circuits for separating digital signals from complete video signals

Country Status (1)

Country Link
KR (1) KR890004062B1 (en)

Also Published As

Publication number Publication date
KR890004062B1 (en) 1989-10-18

Similar Documents

Publication Publication Date Title
KR870008306A (en) Digital Information Reproduction Device
KR880013318A (en) Switched Capacitor Filter
KR890005753A (en) Sampled Analog Electrical Signal Processing Method and Apparatus
KR900013727A (en) Digital / Analog Converter
KR880006909A (en) Integrated circuit for digital information signal separation and digital synchronization signal separation included in composite video signal
US4099204A (en) Delay circuit
KR880006906A (en) Composite Synchronous Signal Separation and Digital Information of Composite Video Signal
KR880006908A (en) Integrated circuit for digital information signal separation and digital sync signal separation included in composite video signal
KR880006904A (en) Synthetic Synchronization Signal Separation and Digital Information of Synthetic Video Signal
KR880009474A (en) Autotune Phase-locked Loop FM Detection System
KR880006905A (en) Integrated circuit for composite synchronous signal separation and high frequency digital information signal separation
KR880003514A (en) Synthetic Synchronization Signal Separation and Digital Information of Synthetic Video Signal
KR880006686A (en) Integrated Circuit for Digital Synchronization Signal Separation of Composite Video Signal
KR880003512A (en) Integrated circuit for digital information signal separation and digital synchronization signal separation included in composite video signal
KR880006599A (en) Digital information signal separation integrated circuit included in composite video signal
KR870001659A (en) Digital information signal separation integrated circuit included in composite video signal
KR910019015A (en) Phase Synchronization Semiconductor Integrated Circuits
KR970055364A (en) Digitally Controlled Multi-Frequency Generator
JP2809549B2 (en) Amplifier
GB2140638A (en) Loudspeaker drive arrangements
KR880003511A (en) Integrated circuit for high frequency digital information signal separation and high frequency digital synchronization signal separation included in composite video signal
KR860007832A (en) Standing clock generation circuit of the time base correction device
KR900005139Y1 (en) Pseudo synchronizing signal generating circuit
KR930003094A (en) Jitter Detection Circuit
KR960009908Y1 (en) Recording control circuit

Legal Events

Date Code Title Description
A201 Request for examination
N231 Notification of change of applicant
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20040331

Year of fee payment: 16

LAPS Lapse due to unpaid annual fee