KR880003514A - Synthetic Synchronization Signal Separation and Digital Information of Synthetic Video Signal - Google Patents

Synthetic Synchronization Signal Separation and Digital Information of Synthetic Video Signal Download PDF

Info

Publication number
KR880003514A
KR880003514A KR1019860007140A KR860007140A KR880003514A KR 880003514 A KR880003514 A KR 880003514A KR 1019860007140 A KR1019860007140 A KR 1019860007140A KR 860007140 A KR860007140 A KR 860007140A KR 880003514 A KR880003514 A KR 880003514A
Authority
KR
South Korea
Prior art keywords
circuit
signal
synchronization signal
comparison voltage
voltage
Prior art date
Application number
KR1019860007140A
Other languages
Korean (ko)
Other versions
KR900003077B1 (en
Inventor
신명철
김영생
Original Assignee
강진구
삼성반도체통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 강진구, 삼성반도체통신 주식회사 filed Critical 강진구
Priority to KR1019860007140A priority Critical patent/KR900003077B1/en
Publication of KR880003514A publication Critical patent/KR880003514A/en
Application granted granted Critical
Publication of KR900003077B1 publication Critical patent/KR900003077B1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Synchronizing For Television (AREA)
  • Picture Signal Circuits (AREA)

Abstract

내용 없음No content

Description

합성동 기신호분리 및 합성비디오신호의 디지탈정보Synthetic Synchronization Signal Separation and Digital Information of Synthetic Video Signal

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 직접회로의 블럭도.2 is a block diagram of an integrated circuit according to the present invention.

제3도는 본발명에 따른 제2도의 구체회로도.3 is a concrete circuit diagram of FIG. 2 according to the present invention.

제4도는 제3도의 구체회로도의 각부 파형도.4 is a waveform diagram of each part of the concrete circuit diagram of FIG.

Claims (1)

합성비디오신호에 포함된 디지탈정보신호 및 디지탈동기 신호를 분리하는 집적회로에 있어서, 입력신호의 전력증폭을 위한 버퍼회로(1)와 입력된신호의 고주파 부분을 제거하는 능동형 제1저주파필터(2)와 여파된 신호중 굴곡으로 나타나는 저주파의 동기신호 부분을 제거하는 샘플링회로(3)와 상기 샘플링 회로(3)에서 출력하는 전압을 비교전압으로 기억하는 기억회로(4)와, 상기 기억된 비교전압을 적절한 레벨의 전압으로 변환하고 샘플링 기간동안 비교전압을 유지하기 위한 고임피던스버퍼회로(5)가 상기 기억회로로부터 입력하는 상기 비교전압과 비디오신호의 데이터와 비교하는 비교회로(6)와 비교된신호를 정당한 레벨의 데이터로 출력하는 제1드라이브회로(7)와 디지탈동기 신호분리를 위해 합성비디오 신호를 증폭하기위한 증폭회로(8)와 합성비디오신호중 특정주파수인 동기신호를 선별하기 위한 공진회로(9)와 공진회로 출력을 비교하기 위한 비교전압을 발생하는 비교전압발생회로(10)와, 상기 비교전압에 따라 공진출력을 비교하는 비교기(11)와 비교된 출력을 적당한 레벨의 구형파로 출력하는 제2드라이브회로(12)와 합성비디오신호중 수평동기신호만 통과시키는 제2저주파필터(13)와, 상기 수평동기신호에서만 오프동작을 하며 소정레벨의 펄스를 출력하는 스위칭회로로만 합성동기분리회로(14)로 구성됨을 특징으로 하는 회로.An integrated circuit for separating a digital information signal and a digital synchronization signal included in a composite video signal, comprising: a buffer circuit (1) for power amplification of an input signal and an active first low frequency filter (2) for removing high frequency portions of an input signal ) And a sampling circuit 3 for removing the low frequency synchronization signal portion of the filtered signal and a storage circuit 4 for storing the voltage output from the sampling circuit 3 as a comparison voltage, and the stored comparison voltage. Is compared with the comparison circuit 6 for comparing the comparison voltage input from the storage circuit with the data of the video signal by the high impedance buffer circuit 5 for converting the voltage into an appropriate level of voltage and maintaining the comparison voltage during the sampling period. A first drive circuit 7 for outputting the signal as a legitimate level of data and an amplification circuit 8 for amplifying the composite video signal for digital synchronization signal separation. A comparison voltage generation circuit 10 for generating a comparison voltage for comparing the resonance circuit 9 for selecting a synchronization signal having a specific frequency among the video signals and an output of the resonance circuit, and a comparator for comparing the resonance output according to the comparison voltage ( A second drive circuit 12 for outputting the output compared with 11) as a square wave of an appropriate level, a second low frequency filter 13 for passing only a horizontal synchronization signal of the composite video signal, and an OFF operation only for the horizontal synchronization signal A circuit comprising a synthetic synchronous separation circuit (14) only as a switching circuit for outputting a pulse of a level. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019860007140A 1986-08-28 1986-08-28 Dividing circuit for television composite video signal KR900003077B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019860007140A KR900003077B1 (en) 1986-08-28 1986-08-28 Dividing circuit for television composite video signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019860007140A KR900003077B1 (en) 1986-08-28 1986-08-28 Dividing circuit for television composite video signal

Publications (2)

Publication Number Publication Date
KR880003514A true KR880003514A (en) 1988-05-17
KR900003077B1 KR900003077B1 (en) 1990-05-07

Family

ID=19251963

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860007140A KR900003077B1 (en) 1986-08-28 1986-08-28 Dividing circuit for television composite video signal

Country Status (1)

Country Link
KR (1) KR900003077B1 (en)

Also Published As

Publication number Publication date
KR900003077B1 (en) 1990-05-07

Similar Documents

Publication Publication Date Title
KR880010608A (en) Picture-in-picture video signal generator
KR840004333A (en) Analog digital inverter
KR880003514A (en) Synthetic Synchronization Signal Separation and Digital Information of Synthetic Video Signal
KR880006906A (en) Composite Synchronous Signal Separation and Digital Information of Composite Video Signal
KR880006905A (en) Integrated circuit for composite synchronous signal separation and high frequency digital information signal separation
KR880006904A (en) Synthetic Synchronization Signal Separation and Digital Information of Synthetic Video Signal
KR880003512A (en) Integrated circuit for digital information signal separation and digital synchronization signal separation included in composite video signal
KR870001659A (en) Digital information signal separation integrated circuit included in composite video signal
KR880006599A (en) Digital information signal separation integrated circuit included in composite video signal
KR880006909A (en) Integrated circuit for digital information signal separation and digital synchronization signal separation included in composite video signal
KR860002204A (en) Television Synchronous Signal Waveform Processing Equipment
KR880006686A (en) Integrated Circuit for Digital Synchronization Signal Separation of Composite Video Signal
KR880006908A (en) Integrated circuit for digital information signal separation and digital sync signal separation included in composite video signal
KR940002763A (en) VISS method of 8mm format
KR880003511A (en) Integrated circuit for high frequency digital information signal separation and high frequency digital synchronization signal separation included in composite video signal
KR930003094A (en) Jitter Detection Circuit
KR920013383A (en) Digital tape recorder
SU1167744A1 (en) Device for time converting of signals
JPH02140059A (en) Method of stretching phase-inverted binary bit-stream only by one full bit and improving transfer characteristic
SU649025A1 (en) Magnetograph record channel
KR930001562A (en) Resolver Signal Demodulation System
KR870002522Y1 (en) Dicture search apparatus
KR950022785A (en) Video signal converter
KR910015112A (en) Oscillator (VCO)
KR910009101A (en) Data selector for color signal digital demodulator

Legal Events

Date Code Title Description
A201 Request for examination
N231 Notification of change of applicant
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20040329

Year of fee payment: 15

LAPS Lapse due to unpaid annual fee