SU1167744A1 - Device for time converting of signals - Google Patents

Abstract

A TEMPORARY TRANSFORMATION SIGNAL DEVICE, containing a first switch and a first memory block, whose information input is connected to the first output of the first switch, a synchronous generator connected in series, a second switch and a first signal converter, the output of which is connected to the address input of the first memory block, the second signal converter, the input of which is connected to the second output of the second switch, characterized in that, in order to extend the functionality by providing temporary Another signal transducer is inserted, the second memory block is inserted, the address input of which is connected to the output of the second converter, and the information input of the second memory block is connected to the second output of the first switch, the frequency divider, whose BXOJDI is connected to the output of the clock generator, connected in series to the third converter the control unit and the third switch, the first and second inputs of which are connected respectively to the outputs of the first and second blocks, the memory, the first output of the control unit is connected to the control (I of the first, second, third switches and the second memory block, the second output of the control unit is connected to the control input of the first memory block, the output of the frequency divider is connected to the second input of the second switch and the input of the third signal converter, while the information input of the first the switch 41 is the input of the device whose output is the output of the third mutator.

Description

The invention relates to a measurement technique and is intended for temporal compression and decompression of signals.

The purpose of the invention is to enhance the functionality by providing a temporal inverse transformation of signals,

The drawing shows the structures of the cha electrical circuit of the device for the temporary conversion of signals

The time signal conversion device comprises the first switch 1, the first memory block 2, the second memory block 3, 0 control unit 4, the second switch 5, the first signal converter 6, the frequency divider 7, the clock generator 8, the second signal converter 9, the third signal converter 10 , third switch 11.

The device for time conversion of signals operates as follows.

The signal S (t) is fed to the information input of the switch 1; If the control input of switch 1 is supplied with a logical unit signal from the first output of block 4, then the signal S (t) is fed through switch 1 to the information input of memory 2, which is set to the signal recording mode S (t ). At the same time, through the switch 5 to the input of the converter 6, clock pulses with a frequency fj are received. The outputs of the converter 6 are connected to the address inputs of the memory block 2. When the address code changes, the signal is recorded in memory block 2. Sync pulses with a frequency f, the first input of the switch 5 is received from frequency divider 7, and also fed to the input of converter 10, the volume of which is equal to the volume of block 2 pa677442

mti expressed in bits of binary information. The division factor of frequency divider 7 is set equal to the compression ratio or 5 decompression of the signal spectrum. After the memory block 2 is completely filled, the block 4 is tilted by the code of the converter 10, and the memory block 2 is signaled

 From the second output of block 4, the stored signal S (t) is transferred to the storage mode and read off the stored signal. The signal from the first input of block 4 switches switches 1, 5 and 11,

5 and the installation of the memory block 3 in the signal recording mode S (t), and the signal S (t) through the switch 1 is fed to the information input of the memory block 3, the address inputs of which have the outputs from the converter 9, to the input of which clock pulses with a frequency fj are received through switch 5 from frequency divider 7. After switching the commutator to clock 5 to the input of converter 6, they come from the output of the clock generator 8, the frequency f of which is twice the frequency fj. As a result, reading information

30 of memory block 2 is implemented at a higher-active frequency. At the same time, the spectrum of the signal S (t) is expanded into Prize and is converted into the signal S (t / n), which from the output of memory block 2 through the switch 11 arrives at the output of the time-conversion device. Decompression of the signal spectrum is carried out in a similar manner,

Q as a compression, only writing to memory blocks 2 and 3 is done at a high clock frequency, and reading is done at a low one, as a result of which the spectrum of the input signal narrows 5 times and becomes S (n / f).

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Claims (1)

A TEMPORARY SIGNAL CONVERSION DEVICE, comprising a first switch and a first memory unit, the information input of which is connected to the first output of the first switch, a sync generator connected in series, the second switch and the first signal converter, the output of which is connected to the address input of the first memory block, the second signal converter, input which is connected to the second output of the second switch, characterized in that, in order to expand functionality by providing temporary back about signal conversion, a second memory block is introduced, the address input of which is connected to the output of the second converter, and the information input of the second memory block is connected to the second output of the first switch, a frequency divider, the input of which is connected to the output of the clock generator, the third converter and the control unit are connected in series, and also a third switch, the first and second inputs of which are connected respectively to the outputs of the first and second memory blocks, the first output of the control unit is connected to the control inputs and the first, second, third switches and the second memory unit, the second output of the control unit is connected to the control input of the first memory unit, the output of the frequency divider is connected to the second input of the second switch and the input of the third signal converter, while the information input of the first switch is the input of the device, the output which is the output of the third switch. FFZZSTT t