KR880001149A - Digital Color Television's Sampling Clock Generation Circuit - Google Patents

Digital Color Television's Sampling Clock Generation Circuit Download PDF

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Publication number
KR880001149A
KR880001149A KR1019860005066A KR860005066A KR880001149A KR 880001149 A KR880001149 A KR 880001149A KR 1019860005066 A KR1019860005066 A KR 1019860005066A KR 860005066 A KR860005066 A KR 860005066A KR 880001149 A KR880001149 A KR 880001149A
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KR
South Korea
Prior art keywords
pulse
sampling clock
output
color television
pass filter
Prior art date
Application number
KR1019860005066A
Other languages
Korean (ko)
Other versions
KR890003236B1 (en
Inventor
한관영
Original Assignee
김정배
삼성전관 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김정배, 삼성전관 주식회사 filed Critical 김정배
Priority to KR8605066A priority Critical patent/KR890003236B1/en
Publication of KR880001149A publication Critical patent/KR880001149A/en
Application granted granted Critical
Publication of KR890003236B1 publication Critical patent/KR890003236B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/06—Generation of synchronising signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Processing Of Color Television Signals (AREA)

Abstract

내용 없음No content

Description

디지탈 칼라 텔레비죤의 샘플링 클럭 발생회로Digital Color Television's Sampling Clock Generation Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 개요도. 제3도는 제2도의 위상동기부의 상세 회로도. 제4도는 제2도의 각 부분에서의 파형도.2 is a schematic diagram of the present invention. 3 is a detailed circuit diagram of the phase synchronizer of FIG. 4 is a waveform diagram in each part of FIG.

Claims (2)

수상기는 인가되는 NTSC 칼라 텔레비죤 신호에서 수평동기신호의 부의 피크치를 일정레벨로 클램핑하는 직류클램핑회로(1)와 이 직류 클램핑회로(1)의 출력에서 수평동기 신호를 검출·분리하는 비교부(2)와 분리된 수평동기펄스를 일정 시정수만큼 지연시켜 출력하는 자연부(3)와 NTSC 칼라 텔레비죤 신호를 대역 여파하여 칼라 버스트 신호를 검출하는 대역통과 필터(4)와 상기한 대역통과 필터(4)와 자연부(3)의 출력신호를 인가하여 색부반송파(fsc)를 발생하는 색부반송파 펄스재생부 (5)와, 상기한 색부반송파 펄스재생부(5)에서 출력되는 칼라 부반송파(fsc)를 이용하여 4개의 위상을 갖는 샘플링 클럭(fs)을 발생하는 위상 동기부(6)로 이루어진 것을 특징으로 하는 디지탈 칼라 텔레비죤의 샘플링 클럭 발생회로.The receiver has a DC clamping circuit 1 for clamping the negative peak value of the horizontal synchronizing signal to a predetermined level in the applied NTSC color television signal, and a comparator for detecting and separating the horizontal synchronizing signal from the output of the DC clamping circuit 1 (2). ) And a band pass filter (4) for detecting color burst signals by band filtering the NTSC color television signal by delaying and outputting the horizontal synchronous pulse separated by a predetermined time constant and the band pass filter (4). ) And a color subcarrier pulse reproducing unit 5 outputted from the color subcarrier pulse reproducing unit 5 and the color subcarrier pulse regenerating unit 5 generating a color subcarrier fsc by applying an output signal from the natural unit 3. And a phase synchronizer (6) for generating a sampling clock (fs) having four phases by using a digital color television sampling clock generation circuit. 제1항에 있어서, 위상동기부(6)의 구성이 색부반송파(fsc)를 455로 분주하는 분주기(DV1)와 전압제어 발진기(VCO)를 5456으로 분주하는 분주기(DV2)와 상기한 양 분주기 (DV1)(DV2)의 출력을 입력으로 하여 양 출력의 위상차를 검출하는 위상검출기(PD)와 상기한 위상검출기(PD)의 출력에서 고주파를 제거하고 일정레벨로 증폭하는 저역통과 필터 및 증폭기(LA)와 상기한 저역통과 필터 및 증폭기(LA)의 출력전압에 따라 소정주파수를 갖는 펄스를 발생하는 전압제어 발진기(VCO)와, 상기한 전압제어발진기(VCO)의 출력펄스를 4로 분주하는 분주기(DV3)등으로 이루어짐을 특징으로 하는 디지탈 칼라 텔레비죤의 샘플링 클럭 발생회로.The method of claim 1, wherein the phase synchronization unit 6 of the configuration is the divider which divides the color subcarrier (fsc) to 455 (DV 1) with cycles of dispensing a voltage controlled oscillator (VCO) to 5456 (DV 2) and A phase detector PD for detecting the phase difference between the two outputs by using the outputs of the dividers DV 1 and DV 2 as an input, and a high frequency is removed from the output of the phase detector PD and amplified to a predetermined level. Of the low pass filter and amplifier LA, the voltage controlled oscillator VCO generating a pulse having a predetermined frequency according to the output voltage of the low pass filter and amplifier LA, and the voltage controlled oscillator VCO. A sampling clock generation circuit of a digital color television, characterized by consisting of a divider (DV 3 ) for dividing an output pulse into four. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR8605066A 1986-06-24 1986-06-24 Sampling circuit for digital color t.v. KR890003236B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR8605066A KR890003236B1 (en) 1986-06-24 1986-06-24 Sampling circuit for digital color t.v.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR8605066A KR890003236B1 (en) 1986-06-24 1986-06-24 Sampling circuit for digital color t.v.

Publications (2)

Publication Number Publication Date
KR880001149A true KR880001149A (en) 1988-03-31
KR890003236B1 KR890003236B1 (en) 1989-08-27

Family

ID=19250696

Family Applications (1)

Application Number Title Priority Date Filing Date
KR8605066A KR890003236B1 (en) 1986-06-24 1986-06-24 Sampling circuit for digital color t.v.

Country Status (1)

Country Link
KR (1) KR890003236B1 (en)

Also Published As

Publication number Publication date
KR890003236B1 (en) 1989-08-27

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