KR870001514A - 제어 장치 - Google Patents

제어 장치 Download PDF

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Publication number
KR870001514A
KR870001514A KR1019860005428A KR860005428A KR870001514A KR 870001514 A KR870001514 A KR 870001514A KR 1019860005428 A KR1019860005428 A KR 1019860005428A KR 860005428 A KR860005428 A KR 860005428A KR 870001514 A KR870001514 A KR 870001514A
Authority
KR
South Korea
Prior art keywords
control
terminal
control signal
releasing
control device
Prior art date
Application number
KR1019860005428A
Other languages
English (en)
Other versions
KR940003631B1 (ko
Inventor
히로시 다게다
Original Assignee
가부시기가이샤 히다찌세이사꾸쇼
미쓰다 가쓰시게
가부시기가이샤 히다찌 세이사꾸쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시기가이샤 히다찌세이사꾸쇼, 미쓰다 가쓰시게, 가부시기가이샤 히다찌 세이사꾸쇼 filed Critical 가부시기가이샤 히다찌세이사꾸쇼
Publication of KR870001514A publication Critical patent/KR870001514A/ko
Application granted granted Critical
Publication of KR940003631B1 publication Critical patent/KR940003631B1/ko

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/4226—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with asynchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Digital Computer Display Output (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

내용 없음.

Description

제어 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 그래픽 표시 시스템에 적용한 경우의 1실시예를 도시한 블록도.
제2도는 실시예의 CRT 콘트롤러의 구체적 블록도.
제3도는 제1도의 시스템의 동작을 설명하기 위한 타이밍 챠트.

Claims (2)

  1. 다이크로 컴퓨터 시스템을 구성하는 주변장치와, 버스를 거쳐서 접속되어, 이를 제어하는 제어장치는, 다른 제어장치로 부터의 제어신호를 받는 단자와, 상기 단자로의 제어신호의 입력에 의해서, 상기 버스를 해방하여 주변 장치를 자기의 제어하에서 절리하도록 하는 제어수단으로 된다.
  2. 특허 청구의 범위 제1항의 제어장치는, 또 상기 제어 신호의 입력에 의해서 버스를 해방한 후, 재빨리 이를 외부에 알리는 신호를 출력하기 위한 단자로 된다.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019860005428A 1985-07-24 1986-07-05 제어장치를 구비한 시스템 KR940003631B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP60-161886 1985-07-24
JP60161886A JPH0746308B2 (ja) 1985-07-24 1985-07-24 表示制御装置およびマイクロコンピュータ・システム

Publications (2)

Publication Number Publication Date
KR870001514A true KR870001514A (ko) 1987-03-14
KR940003631B1 KR940003631B1 (ko) 1994-04-25

Family

ID=15743858

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860005428A KR940003631B1 (ko) 1985-07-24 1986-07-05 제어장치를 구비한 시스템

Country Status (3)

Country Link
US (1) US5079692A (ko)
JP (1) JPH0746308B2 (ko)
KR (1) KR940003631B1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100264613B1 (ko) * 1998-05-16 2000-12-01 이희옥 판상 장식품의 개금 개채 방법

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US5274770A (en) * 1992-07-29 1993-12-28 Tritech Microelectronics International Pte Ltd. Flexible register-based I/O microcontroller with single cycle instruction execution
US5631733A (en) * 1995-01-20 1997-05-20 Photon Dynamics, Inc. Large area defect monitor tool for manufacture of clean surfaces
US5801824A (en) * 1996-11-25 1998-09-01 Photon Dynamics, Inc. Large area defect monitor tool for manufacture of clean surfaces
EP2111884A1 (en) * 1997-05-28 2009-10-28 United States Surgical Corporation Trocar seal system
US20060056234A1 (en) * 2004-09-10 2006-03-16 Lowrey Tyler A Using a phase change memory as a shadow RAM
FR2916873B1 (fr) * 2007-05-29 2009-09-18 Schneider Electric Ind Sas Dispositif de controle de communication entre un module et un bus de transmission
JP5752382B2 (ja) * 2010-09-29 2015-07-22 矢崎総業株式会社 表示装置及び画像データの転送方法

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US4070710A (en) * 1976-01-19 1978-01-24 Nugraphics, Inc. Raster scan display apparatus for dynamically viewing image elements stored in a random access memory array
US4200916A (en) * 1976-07-01 1980-04-29 Gulf & Western Industries, Inc. Programmable controller using microprocessor
US4368512A (en) * 1978-06-30 1983-01-11 Motorola, Inc. Advanced data link controller having a plurality of multi-bit status registers
US4263648A (en) * 1978-12-26 1981-04-21 Honeywell Information Systems Inc. Split system bus cycle for direct memory access of peripherals in a cathode ray tube display system
US4558412A (en) * 1978-12-26 1985-12-10 Honeywell Information Systems Inc. Direct memory access revolving priority apparatus
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US4513390A (en) * 1979-06-08 1985-04-23 Planning Research Corporation System for digital transmission and synthesis of integrated data
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US4415985A (en) * 1980-08-28 1983-11-15 The Bendix Corporation Driving circuit for cathode ray tube
JPS5748122A (en) * 1980-09-05 1982-03-19 Fujitsu Ltd Assignment controlling system of common input-output device
US4527250A (en) * 1980-09-11 1985-07-02 Allen-Bradley Company Video computer terminal with detachable intelligent keyboard module
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JPS5779551A (en) * 1980-11-06 1982-05-18 Nec Corp Information transfer device
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JPS588348A (ja) * 1981-07-07 1983-01-18 Sony Corp 出力表示用メモリの制御回路
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JPS5945527A (ja) * 1982-09-07 1984-03-14 Hitachi Ltd バス制御方法
JPH079569B2 (ja) * 1983-07-01 1995-02-01 株式会社日立製作所 ディスプレイコントローラ及びそれを用いた図形表示装置
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US4570220A (en) * 1983-11-25 1986-02-11 Intel Corporation High speed parallel bus and data transfer method
US4703420A (en) * 1985-02-28 1987-10-27 International Business Machines Corporation System for arbitrating use of I/O bus by co-processor and higher priority I/O units in which co-processor automatically request bus access in anticipation of need
JPH087569B2 (ja) * 1985-06-21 1996-01-29 株式会社日立製作所 表示制御装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100264613B1 (ko) * 1998-05-16 2000-12-01 이희옥 판상 장식품의 개금 개채 방법

Also Published As

Publication number Publication date
JPH0746308B2 (ja) 1995-05-17
US5079692A (en) 1992-01-07
KR940003631B1 (ko) 1994-04-25
JPS6224346A (ja) 1987-02-02

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