JPS6441951A - Dma controller - Google Patents

Abstract

PURPOSE:To attain a high speed action by outputting directly a reading or writing signal to an input output device connected to a data bus only and outputting the address signal of a RAM and the writing or reading signal with the approximately same cycle as the control cycle. CONSTITUTION:An input output interface 5 is connected only to a data bus D of a CPU 1, an input output control circuit 81 and a RAM control circuit 82 are provided at a DMA controller 8, the circuit 82 is respectively connected to the bus D, an address bus A and a control bus C, and a local address bus LA of the circuit 81 and a control bus LC are connected to an interface 5. When the data are transferred from an FD device 7 to a RAM 3, an address signal is outputted from the circuit 82 to the RAM 3 and from the circuit 81 to the interface 5 respectively. Next, a reading signal is outputted from the circuit 81, the data from an FD controller 6 are outputted to the bus D, the writing signal is outputted from the circuit 82 and the data signal on the bus D are stored into the RAM 3.