KR850006653A - 집적회로 장치의 제조방법 - Google Patents
집적회로 장치의 제조방법 Download PDFInfo
- Publication number
- KR850006653A KR850006653A KR1019850001040A KR850001040A KR850006653A KR 850006653 A KR850006653 A KR 850006653A KR 1019850001040 A KR1019850001040 A KR 1019850001040A KR 850001040 A KR850001040 A KR 850001040A KR 850006653 A KR850006653 A KR 850006653A
- Authority
- KR
- South Korea
- Prior art keywords
- transistor
- integrated circuit
- circuit device
- manufacturing
- region
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims 2
- 238000005468 ion implantation Methods 0.000 claims 2
- 238000000034 method Methods 0.000 claims 2
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제6도는 각각 본 발명의 일실시예에 관한 집적회로장치의 제조방법을 설명하는 단면도.
* 도면의 주요부분에 대한 부호의 설명
11 : 반도체기판 12 : 필드산화막
13 : 게이트산화막 14 : 레지스트(Resist)막
15A,15B : 게이트전극 16 : 확산층
A,B : 불순물 농도 프로파일(Profile)
VDD, VSS: 전원 Vin : 입력
Vout : 출력 Vh : 히스테리시스폭
Claims (2)
- 고임계전압 트랜지스터, 상기 고임계전압 트랜지스터와 동일형태로서 저임계전압 트랜지스터를 구비하는 집적회로장치의 제조방법에 있어서, 상기 저임계치의 트랜지스터 형성 예정영역상에 레지스트막을 피착한 상태로서 고임계치의 트랜지스터 형성 예정영역에 임계치제어를 위해 이온주입을 선택적으로 행하는 것을 특징으로 하는 집적회로장치의 제조방법.
- 제1항에 있어서, 게이트가 공통 접속되는 소오스, 드레인 사이에 직렬로 접속되는 제1~제3트랜지스터, 상기 제1트랜지스터 및 제2트랜지스터의 접속점과 제2트랜지스터 및 제3트랜지스터의 접속점에 각각 게이트 및 드레인이 접속되는 출력전위궤환용 제4트랜지스터로 부터 이루어진 입력회로용 슈미트트리거회로의 제2트랜지스터를 포함한 복수의 트랜지스터 제조방법에 있어서, 상기 제2트랜지스터 형성 예정영역상에 레지스트막을 피착한 상태로서 다른 트랜지스터형성 예정영역에 임계치 제어를 위해 채널이온주입공정을 실시하는 것을 특징으로 하는 집적회로장치의 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59063581A JPS60207364A (ja) | 1984-03-31 | 1984-03-31 | 集積回路装置の製造方法 |
| JP59-63581 | 1984-03-31 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR850006653A true KR850006653A (ko) | 1985-10-14 |
| KR890004453B1 KR890004453B1 (ko) | 1989-11-04 |
Family
ID=13233370
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019850001040A KR890004453B1 (ko) | 1984-03-31 | 1985-02-19 | 집적회로장치의 제조방법 |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS60207364A (ko) |
| KR (1) | KR890004453B1 (ko) |
-
1984
- 1984-03-31 JP JP59063581A patent/JPS60207364A/ja active Pending
-
1985
- 1985-02-19 KR KR1019850001040A patent/KR890004453B1/ko not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR890004453B1 (ko) | 1989-11-04 |
| JPS60207364A (ja) | 1985-10-18 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| G160 | Decision to publish patent application | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20041101 Year of fee payment: 16 |
|
| EXPY | Expiration of term |