KR830001223Y1 - FLAT ZONE ALIGNER - Google Patents
FLAT ZONE ALIGNER Download PDFInfo
- Publication number
- KR830001223Y1 KR830001223Y1 KR2019810008244U KR810008244U KR830001223Y1 KR 830001223 Y1 KR830001223 Y1 KR 830001223Y1 KR 2019810008244 U KR2019810008244 U KR 2019810008244U KR 810008244 U KR810008244 U KR 810008244U KR 830001223 Y1 KR830001223 Y1 KR 830001223Y1
- Authority
- KR
- South Korea
- Prior art keywords
- wafer
- flat zone
- carrier
- chip
- present
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
내용 없음.No content.
Description
제1도는 본 고안의 분해사시도.1 is an exploded perspective view of the present invention.
제2a도, 제2b도는 본 고안의 사용상태 단면도.Figure 2a, Figure 2b is a cross-sectional view of the state of use of the present invention.
제3도는 종래의 웨이퍼(Wafer)의 파손상태도.3 is a broken state of a conventional wafer.
제4도는 본 고안의 웨이퍼 파손상태도.4 is a wafer broken state of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 고정판 2 : 회전축1: fixing plate 2: rotating shaft
3 : 재치대 4 : 캐리어3: mounting table 4: carrier
4' : 간막이 5 : 웨이퍼4 ': partition 5: wafer
본 고안은 반도체 웨이퍼 가공공정에 사용되는 장치로서 캐리어에서 웨이퍼를 꺼내어 공정을 수행하거나 완성여부를 조사하는 과정에서 웨이퍼의 일부분 즉, 플랫죤 부분만을 잡고 사용하므로서 칩CHIP)의 기능을 최대한으로 활용할 수 있도록 웨이퍼가 담긴 캐리어를 얼라이너에 놓고 얼라이너를 회동시켜 웨이퍼의 플랫죤이 상부로 정렬되도록한 플랫죤 얼라이너에 관한 것이다.The present invention is a device used in semiconductor wafer processing process and can take full advantage of the function of chip (chip) by taking out part of wafer, that is, flat zone part in the process of taking out wafer from carrier or inspecting completion. The present invention relates to a flat zone aligner in which a carrier containing a wafer is placed on an aligner, and the aligner is rotated so that the flat zone of the wafer is aligned upward.
종래에는 티이져(웨이퍼를 잡을 수 있도록 된 집게)로 캐리어 내부에 있는 웨이퍼를 집어 내는데 있어서 웨이퍼가 캐리어 내에서 일정 방향을 유지하지 못하게 되어 있어 웨이퍼의 아무 곳이나 잡아 쓰게 되는데 이와 같은 작업을 여러 차례 거치는 과정에서 플랫죤 이외의 부분을 마구 잡게되어 웨이퍼를 절단하여 칩을 구성하는데 있어서 플랫죤 이외의 주연부에 있는 칩을 파손하여 칩의 기능을 할수 없도록 되어있는 등 결점이 많았다.Conventionally, in order to pick up a wafer inside a carrier with a teaser (a tong that can hold a wafer), the wafer is not kept in a certain direction in the carrier, so it can be used anywhere on the wafer. In the process of mounting, there were many defects such as the fact that the chip was cut at a portion other than the flat zone to cut the wafer to form a chip, so that the chip at the periphery of the flat zone other than the flat zone could not be functioned.
본 고안은 종래 이러한 결점을 해결코저 안출한 것으로 이를 첨부된 도면에 의하여 상세히 설명하면 다음과 같다.The present invention has been devised to solve these drawbacks in the prior art and will be described in detail by the accompanying drawings as follows.
직, 다수의 간막이(4/)를 가진 캐리어(4)에 웨이퍼(5)를 삽설하고, 캐리어 재치대(3)를 회전축(2)의 양측에 설치하되 재치대(3)의 네면모서리를 삭설하여 형성하고, 이를 고정판(1)에 착설하되 회전축(2)의 일단을 모터(6)에 연결하여서 된 것으로 미설명부호 7은 플랫죤, 8은 칩이다.Directly, the wafer 5 is inserted into the carrier 4 having a large number of partitions 4 /, and the carrier mounting table 3 is installed on both sides of the rotation shaft 2, but the four sides of the mounting table 3 are cut off. It is formed by mounting on the fixed plate (1), but one end of the rotating shaft (2) by connecting the motor 6, reference numeral 7 is a flat zone, 8 is a chip.
이와 같이 구성된 본 고안은 캐리어(4)에 웨이퍼(5)를 삽설하여 이를 꺼꾸로 고정판(1)에 착설된 재치대(3)에 재치한 후, 모터(6)를 회동시키면, 이와 연결된 회전축(2)이 회전하는 것인데, 이때 회전축(2)의 회전으로 이에, 웨이퍼(5)가 접하게 되어 웨이퍼(5)가 회전축(2)을 따라 회동하도가 플랫죤(7) 부분이 회전으로 이에, 웨이퍼(5)가 접하게 되어 웨이퍼(5)가 괘지되면서 웨이퍼(5)가 회전축(2)과 떨어지게 되어 회전이 되지 않는 것으로, 제2(a)도, 제2(b)도와 같이 작동하는 것이다.According to the present invention configured as described above, the wafer 5 is inserted into the carrier 4, and the wafer 5 is placed upside down on the mounting table 3 mounted on the fixed plate 1. Then, when the motor 6 is rotated, the rotating shaft 2 connected thereto is connected. ) Is rotated, in which case the wafer 5 is brought into contact with the rotation of the rotation shaft 2, and the flat zone 7 rotates while the wafer 5 is rotated along the rotation shaft 2. 5) is brought into contact with the wafer 5 and the wafer 5 is separated from the rotating shaft 2 so that the rotation is not performed. The second (a) also operates as shown in the second (b).
따라서 웨이퍼(5)가 정열이 되는데, 캐리어(4)에는 보통 25매의 웨이퍼(5)가 삽설되어 있어 회전축(2)를 계속 회전시키면 25매의 웨이퍼가 정열이 되는 것으로 캐리어(4)를 다시 거꾸로 원상태로 놓게되면 플랫죤(7) 부분이 위로 올라오도록 된 것이다.Thus, the wafers 5 are aligned. In the carrier 4, 25 wafers 5 are usually inserted. If the rotating shaft 2 is continuously rotated, 25 wafers are aligned. If you put it upside down, the flat zone (7) is raised up.
이와 같이 작동하는 본 고안은 간단한 방법으로 웨이퍼(5)를 정열시킬 수 있으며, 정열된 웨이퍼(5)의 플랫죤(7) 부분만을 잡고 사용할 수 있어 칩(8)의 손상을 최대한 막고 칩(8)의 기능을 최대한으로 활용토록한 것이며, 종래의 웨이퍼 손상과 본 고안의 손상을 제3도와 제4도에서 비교한 것을 비추어 보아도 본 고안의 효과는 지대한 것으로 웨이퍼의 손상을 최대한으로 줄여 작업공정중의 불편한 점을 해소하고 재료를 절약할 수 있어 원가가 저렴한 잇점 등을 지닌 것이다.The present invention operating in this manner can align the wafer 5 in a simple manner, and can only hold the flat zone 7 portion of the aligned wafer 5 to prevent damage to the chip 8 and to prevent the chip 8 ), The effect of the present invention is enormous, and the damage of the wafer is maximized. It is possible to eliminate the inconveniences and save materials, which has the advantages of low cost.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019810008244U KR830001223Y1 (en) | 1981-12-07 | 1981-12-07 | FLAT ZONE ALIGNER |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019810008244U KR830001223Y1 (en) | 1981-12-07 | 1981-12-07 | FLAT ZONE ALIGNER |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR830001223Y1 true KR830001223Y1 (en) | 1983-07-18 |
Family
ID=19223456
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019810008244U KR830001223Y1 (en) | 1981-12-07 | 1981-12-07 | FLAT ZONE ALIGNER |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR830001223Y1 (en) |
-
1981
- 1981-12-07 KR KR2019810008244U patent/KR830001223Y1/en active
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