KR20200021230A - method for bonding flip chip - Google Patents
method for bonding flip chip Download PDFInfo
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- KR20200021230A KR20200021230A KR1020180096743A KR20180096743A KR20200021230A KR 20200021230 A KR20200021230 A KR 20200021230A KR 1020180096743 A KR1020180096743 A KR 1020180096743A KR 20180096743 A KR20180096743 A KR 20180096743A KR 20200021230 A KR20200021230 A KR 20200021230A
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- adhesive layer
- substrate
- die
- curing
- bonding
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- C09J5/06—Adhesive processes in general; Adhesive processes not provided for elsewhere, e.g. relating to primers involving heating of the applied adhesive
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Abstract
Description
본 발명은 반도체 소자의 제조에 관한 것으로, 구체적으로 플립 칩 본딩 방법에 관한 것이다.The present invention relates to the manufacture of semiconductor devices, and more particularly to a flip chip bonding method.
전자 기기에 사용되는 반도체 패키지의 크기가 소형화되고 그 두께도 더욱 얇아지는 추세에 있다. 이에 따라, 반도체 패키지의 실장 면적과 두께를 최소화하면서 고밀도, 고용량, 고속 성능을 구현하기 위하여 플립 칩 본딩 (flip chip bonding)을 통해 반도체 칩과 패키지 기판을 인터커넥트(interconnect)하는 방식이 제안되었다.There is a trend that the size of the semiconductor package used in electronic devices becomes smaller and the thickness thereof becomes thinner. Accordingly, a method of interconnecting a semiconductor chip and a package substrate through flip chip bonding has been proposed to realize high density, high capacity, and high speed while minimizing the mounting area and thickness of the semiconductor package.
본 발명의 해결 과제는 보이드(void)와 필렛(fillet)의 결함을 감소시킬 수 있는 플립 칩 본딩 방법을 제공하는 데 있다.An object of the present invention is to provide a flip chip bonding method capable of reducing defects of voids and fillets.
본 발명은 플립 칩 본딩 방법을 개시한다. 그의 방법은, 접착 층이 형성된 제 1 기판을 포함하는 다이를 획득하는 단계; 상기 제 1 기판과 다른 제 2 기판 상에 상기 다이를 본딩하는 단계; 및 상기 접착 층을 경화하는 단계를 포함한다. 여기서, 상기 접착 층을 경화하는 단계는: 상기 제 2 기판을 가열하여 상기 접착 층을 용융시키는 단계; 및 상기 접착 층과 상기 제 2 기판에 상압보다 높은 고압의 공기를 제공하는 단계를 포함할 수 있다. The present invention discloses a flip chip bonding method. The method includes obtaining a die comprising a first substrate having an adhesive layer formed thereon; Bonding the die on a second substrate different from the first substrate; And curing the adhesive layer. Wherein the curing of the adhesive layer comprises: heating the second substrate to melt the adhesive layer; And providing high pressure air higher than normal pressure to the adhesive layer and the second substrate.
본 발명의 일 에에 따른 플립 칩 본딩 방법은, 접착 층이 형성된 제 1 기판을 포함하는 다이를 획득하는 단계; 상기 제 1 기판과 다른 제 2 기판 상에 상기 다이를 제공하는 단계; 상기 다이와 상기 접착 층을 제 1 온도로 가열하여 상기 다이의 범프들과 상기 접착 층을 용융시키는 단계; 상기 제 2 기판 상에 상기 다이를 압착하여 상기 다이를 본딩하는 단계; 상기 다이가 상기 제 2 기판 상에 정해진 개수로 본딩되었는지 판별하는 단계; 상기 다이가 정해진 개수로 본딩된 것으로 판별될 경우, 상기 제 2 기판을 상기 제 1 온도보다 낮은 제 2 온도로 가열하여 상기 접착 층을 재 용융시키는 단계; 및 상기 접착 층과 상기 제 2 기판에 상압보다 높은 고압의 공기를 제공하여 상기 용융된 접착 층의 응집력 또는 표면장력으로 상기 접착 층 내의 보이드를 제거하는 단계를 포함한다.A flip chip bonding method according to one embodiment of the present invention comprises the steps of: obtaining a die comprising a first substrate having an adhesive layer formed thereon; Providing the die on a second substrate different from the first substrate; Heating the die and the adhesive layer to a first temperature to melt the bumps of the die and the adhesive layer; Bonding the die by pressing the die on the second substrate; Determining whether the die is bonded to the second substrate in a predetermined number; If it is determined that the die is bonded in a predetermined number, reheating the adhesive layer by heating the second substrate to a second temperature lower than the first temperature; And providing air of a high pressure higher than normal pressure to the adhesive layer and the second substrate to remove voids in the adhesive layer by the cohesive force or the surface tension of the molten adhesive layer.
본 발명의 개념에 따른 플립 칩 본딩 방법은 상압보다 높은 고압의 공기를 기판과 다이 사이의 접착 층에 제공하여 상기 접착층의 보이드와 필렛의 결함을 감소시킬 수 있다. Flip chip bonding method according to the concept of the present invention can reduce the defects of the voids and fillets of the adhesive layer by providing a higher pressure air than the normal pressure to the adhesive layer between the substrate and the die.
도 1은 본 발명의 개념에 따른 플립 칩 본딩 방법을 보여주는 플로우 챠트이다.
도 2 내지 도 10은 도 1의 플립 칩 본딩 방법을 보여주는 공정 단면도들이다.
도 11은 도 1의 다이를 회득하는 단계의 일 예를 보여주는 플로우 챠트이다.
도 12는 도 1의 다이를 본딩하는 단계의 일 예를 보여주는 플로우 챠트이다.
도 13은 도 1의 접착 층을 경화하는 단계의 일 예를 보여주는 플로우 챠트이다.
도 14는 도 9의 하우징 내의 공기의 압력에 따른 보이드의 제거율을 보여준다.
도 15는 일반적인 진공 압력에서의 접착 층의 필렛을 보여주는 단면도이다. 1 is a flow chart illustrating a flip chip bonding method according to the inventive concept.
2 to 10 are sectional views showing a flip chip bonding method of Figure 1;
FIG. 11 is a flowchart illustrating an example of acquiring a die of FIG. 1 .
12 is a flow chart illustrating an example of bonding the die of FIG. 1 .
FIG. 13 is a flowchart illustrating an example of curing the adhesive layer of FIG. 1 .
FIG. 14 shows the removal rate of voids according to the pressure of air in the housing of FIG. 9 .
15 is a cross-sectional view showing the fillet of the adhesive layer at normal vacuum pressure.
도 1은 본 발명의 개념에 따른 플립 칩 본딩 방법을 보여준다. 도 2 내지 도 10은 도 1의 플립 칩 본딩 방법을 보여주는 공정 단면도들이다. 1 illustrates a flip chip bonding method according to the inventive concept. 2 to 10 are sectional views showing a flip chip bonding method of Figure 1;
도 1 내지 도 10을 참조하면, 본 발명의 플립 칩 본딩 방법은, 다이(40)를 획득하는 단계(S10), 상기 다이(40)를 본딩하는 단계(S20), 상기 다이(40)가 정해진 개수로 본딩되었는지를 판별하는 단계(S30) 및 접착 층(30)을 경화(cure)하는 단계(S40)를 포함할 수 있다. 상기 다이(40)를 획득하는 단계(S10)는 제 1 기판(10)으로부터 상기 다이(40)를 준비하는 단계일 수 있다. 상기 다이(40)를 본딩하는 단계(S20)는 상기 접착 층(30)을 이용하여 상기 다이(40)를 제 2 기판(50)에 접착(attach)시키는 단계일 수 있다. 상기 다이(40)가 정해진 개수로 본딩되었는지를 판별하는 단계(S30)는 미리 정해진 개수의 상기 다이(40)를 상기 제 2 기판(50)에 본딩시키기 위한 단계일 수 있다. 상기 접착 층(30)을 경화하는 단계(S40)는 상기 접착 층(30)의 결함(defect)을 제거하는 단계일 수 있다. If Figure 1 to refer to Figure 10, a flip chip bonding method of the present invention, given a step (S10), the step of bonding the die 40 (S20), the die (40) for obtaining
도 11은 도 1의 다이(40)를 회득하는 단계(S10)의 일 예를 보여준다. FIG. 11 shows an example of step S10 of acquiring the die 40 of FIG. 1 .
도 2 내지 도 4 및 도 11을 참조하면, 상기 다이(40)를 획득하는 단계(S10)는 범프들(20)을 형성하는 단계(S12), 상기 접착 층(30)을 형성하는 단계(S14) 및 상기 접착 층(30)과 상기 제 1 기판(10)을 절취(cut)하는 단계(S16)를 포함할 수 있다. 2 to 4 and 11, the step (S10) of acquiring the
도 2 및 도 11을 참조하면, 볼 어테칭 장치(미도시)는 제 1 기판(10) 상에 범프들(20)을 형성한다(S12). 상기 제 1 기판(10)은 실리콘 웨이퍼를 포함할 수 있다. 상기 제 1 기판(10)은 복수개의 제 1 패드들(12)을 가질 수 있다. 상기 범프들(20)은 상기 복수개의 제 1 패드들(12) 상에 형성될 수 있다. 상기 범프 들(20)의 각각은 솔더 볼을 포함할 수 있다. 2 and 11 , the ball attaching apparatus (not shown) forms
도 3 및 도 11을 참조하면, 접착제 도포 장치(미도시)는 상기 제 1 기판(10) 및 상기 범프들(20) 상에 접착 층(30)을 형성한다(S14). 상기 접착 층(30)은 상기 제 1 기판(10)의 상부면 전체에 도포될 수 있다. 일 예에 따르면, 상기 접착 층(30)은 비 전도성 필름(Non-Conductive Film: NCF) 또는 비 전도성 페이스트(Non-Conductive Past: NCP)를 포함할 수 있다. 예를 들어, 상기 접착 층(30)은 열경화성 수지, 경화제(hardener) 및 환원제(reducer)를 포함할 수 있다. 상기 열경화성 수지는 비스패놀(Bisphenol) A 에폭시 수지, 비스 패놀 F 에폭시 수지, 노볼락(Novolac) 에폭시 수지, 알리파틱(Aliphatic) 에폭시 수지, 또는 글리시디아민(Glycidylamine) 에폭시 수지를 포함할 수 있다. 상기 경화제는 상기 열경화성 수지를 온도 이상에서 경화시킬 수 있다. 상기 경화제는 아민(amine), 또는 폴리이미드(polyimide)를 포함할 수 있다. 일 예에 따르면, 상기 열경화성 수지와 상기 경화제는 약 100J/g 내지 약 150J/g의 단위 질량당 발열량의 당량비(equivalence ratio)를 가질 수 있다. 예를 들어, 상기 열경화성 수지와 상기 경화제는 약 10:1 내지 약 15:1의 혼합비를 가질 수 있다. 상기 환원제는 상기 제 1 패드들(12)과 상기 범프들(20) 상의 자연 산화물(native oxide)을 제거시킬 수 있다. 예를 들어, 상기 환원제는 분자 내에 1개 이상의 알코올(Alcohol)성 수산기(ex, Dimethanol, Diethylen glycol, Butanetriol, 및 Triethanolamine)를 포함하는 환원제, 분자 내에 1개 이상의 패놀성 수산기(ex, Naphthol, Hydroxyhydroquinone, 및 Trihydroxybenzopyenone)를 포함하는 환원제, 분자 내에 1개 이상의 카르복실 산(ex, Oxalic acid, Succinic acid, Malonic acid, Oxoacid 및 Carboxylic acid 유도체)를 포함하는 환원제, 또는 분자 내에 비공유 전자쌍을 갖는 질소함유 화합물(ex, Imidazole류, Amine류)을 포함하는 환원제를 포함하거나 상기 환원제들의 조합물을 포함할 수 있다. 3 and 11 , the adhesive applying device (not shown) forms an
carboxylic hydrate, hydroxyl hydrate, 또는 phenolic hydrate의 플럭스(flux)을 포함할 수 있다. 상기 환원제는 약 150℃에서 상기 자연 산화물과 반응될 수 있다. It may include a flux of carboxylic hydrate, hydroxyl hydrate, or phenolic hydrate. The reducing agent may be reacted with the natural oxide at about 150 ° C.
도 4 및 도 11을 참조하면, 커팅 장치(42)는 상기 접착 층(30) 및 상기 제 1 기판(10)을 절취하여 상기 다이(40)를 형성한다(S16). 상기 커팅 장치(42)는 웨이퍼 쏘잉 장치 또는 레이저 쏘잉 장치일 수 있다. 상기 다이(40)는 메모리 칩, 로직 칩, 또는 AP(Application Process) 칩을 포함할 수 있다. 상기 다이(40)는 평면적인 관점에서 사각형의 모양을 가질 수 있다. 4 and 11 , the
도 12는 도 1의 다이(40) 본딩하는 단계(S20)의 일 예를 보여준다. FIG. 12 shows an example of bonding (S20) the die 40 of FIG. 1 .
도 5 내지 도 7 및 도 12를 참조하면, 상기 다이(40)를 본딩하는 단계(S20)는 상기 다이(40) 및 상기 접착 층(30)의 열 압착 방법을 포함할 수 있다. 일 예에 따르면, 상기 다이(40)를 본딩하는 단계(S20)는 상기 다이(40)를 제공하는 단계(S22), 상기 다이(40)를 가열하는 단계(S24), 상기 다이(40)를 압착하는 단계(S26)를 포함할 수 있다. 5 to 7 and 12, the step (S20) of bonding the die 40 may comprise a thermo-compression bonding method of the die 40 and the
도 5 및 도 12를 참조하면, 본딩 헤드(60)는 상기 다이(40)를 상기 제 2 기판(50) 상에 제공한다(S22). 상기 제 2 기판(50)은 제 2 패드들(52)을 가질 수 있다. 상기 범프들(20)은 상기 제 2 패드들(52)에 정렬될 수 있다. 더불어, 상기 제 1 패드들(12)은 상기 제 2 패드들(52)에 정렬될 수 있다. 상기 본딩 헤드(60)는 상기 제 1 패드들(12)을 약 0.5초 이내로 상기 제 2 패드들(52)에 정렬시킬 수 있다. 상기 본딩 헤드(60)는 제 1 히터(62)를 가질 수 있다. 상기 제 1 히터(62)는 제 1 전원(64) 및 제 1 스위칭 소자(66)에 직렬로 연결될 수 있다. 상기 제 1 전원(64)은 상기 제 1 히터(62)에 제 1 히팅 파워를 공급할 수 있다. 상기 제 1 스위칭 소자(66)는 제 1 히팅 파워를 제어할 수 있다. 5 and 12 , the
도 6 및 도 12를 참조하면, 상기 제 1 스위칭 소자(66)가 턴온될 경우, 상기 제 1 히터(62)는 상기 제 1 히팅 파워를 이용하여 상기 다이(40)를 가열하여 상기 다이(40)의 범프들(20) 및 상기 접착 층(30)을 용융시킨다(S24). 상기 제 1 히터(62)는 상기 다이(40)를 약 150℃ 내지 약 300℃의 온도로 가열할 수 있다. 상기 접착 층(30)과 상기 범프들(20)은 용융될 수 있다. 6 and 12 , when the
도 7 및 도 12를 참조하면, 상기 본딩 헤드(60)는 상기 다이(40)를 상기 제 2 기판(50)에 압착한다(S26). 상기 범프들(20)은 상기 제 1 패드들(12)을 상기 제 2 패드들(52)에 연결시킬 수 있다. 상기 본딩 헤드(60)는 상기 다이(40)를 고속으로 본딩시킬 수 있다. 예를 들어, 상기 본딩 헤드(60)는 상기 다이(40)를 약 3초 내지 약 4초 동안에 본딩시킬 수 있다. 이와 같이 상기 다이(40)가 급속히 본딩될 경우, 상기 접착 층(30)의 열경화성 수지와 경화제의 경화 반응(curing reaction)은 미약하거나 불완전할 수 있다. 나아가, 상기 다이(40)가 급속히 본딩될 경우, 상기 보이드(32)는 상기 접착 층(30) 내에 다량으로 생성될 수 있다. 상기 보이드(32)는 상기 접착 층(30)의 결함(defect)일 수 있다. 상기 보이드(32)는 상기 제 2 기판(50)의 상부 면에 인접하여 주로 생성되며, 상기 접착 층(30) 대비 약 4% 정도로 생성될 수 있다. 7 and 12 , the
이후, 상기 제 1 스위칭 소자(66)가 턴오프되면, 상기 범프들(20)과 상기 접착 층(30)은 냉각될 수 있다. 상기 범프들(20)과 상기 접착 층(30)은 응고(solidified)될 수 있다. 이와 달리, 상기 접착 층(30)이 상기 제 2 기판(50) 상에 형성된 후에, 상기 다이(40)는 상기 접착 층(30) 상에 제공될 수 있다. 그러나, 상기 접착 층(30)은 상기 제 2 기판(50)의 측면과 후면을 오염시킬 뿐만 아니라, 상기 다이(40)의 정렬 불량(alignment fault)을 야기시킬 수 있다. 따라서, 상기 접착 층(30)이 상기 다이(40)에 형성되고, 상기 다이(40)가 상기 제 2 기판(50)에 다시 본딩될 경우, 상기 다이(40)의 정렬 불량(alignment fault)은 방지될 수 있다. Thereafter, when the
다시 도 1 및 도 8을 참조하면, 제어 부(미도시)는 상기 제 2 기판(50) 상에 정해진 개수의 상기 다이(40)가 본딩되었는지를 판별한다(S30). 상기 다이(40)가 상기 제 2 기판(50) 상에 정해진 개수로 본딩되지 않았으면, 상기 본딩 헤드(60)는 상기 제 2 기판(50) 상에 상기 다이(40)를 추가적 및/또는 반복적으로 본딩시킬 수 있다(S20). 그 결과, 정해진 개수의 상기 다이들(40)은 상기 제 2 기판(50) 상에 본딩될 수 있다. 상기 제 2 기판(50)이 인쇄회로기판일 경우, 약 200개 내지 약 500개 정도의 상기 다이들(40)이 약 6분 내지 약 25분 동안에 상기 제 2 기판(50)에 본딩될 수 있다. 상기 제 2 기판(50)이 실리콘 웨이퍼일 경우, 약 1000개 정도의 상기 다이들(40)이 약 50분 내지 약 1시간 내에 상기 제 2 기판(50) 상에 본딩될 수 있다.Referring back to FIGS. 1 and 8 , a controller (not shown) determines whether a predetermined number of dies 40 are bonded on the second substrate 50 (S30). If the
도 13은 도 1의 접착 층(30)을 경화하는 단계(S40)의 일 예를 보여준다. FIG. 13 shows an example of step S40 of curing the
도 9, 도 10 및 도 13을 참조하면, 상기 접착 층(30)을 경화하는 단계(S40)는 상기 접착 층(30)의 리플로우 방법을 포함할 수 있다. 예를 들어, 상기 접착 층(30)은 약 10분 내지 약 60분동안에 충분히 경화(cured)될 수 있다. 일 예에 따르면, 상기 접착 층(30)을 경화하는 단계(S40)는 상기 제 2 기판(50)을 가열하는 단계(S42) 및 공기(82)를 제공하는 단계(S44)를 포함할 수 있다. 9 , 10, and 13 , the step (S40) of curing the
도 9 및 도 13을 참조하면, 정해진 개수의 상기 다이들(40)이 상기 제 2 기판(50) 상에 본딩되었을 경우, 오븐(70)은 상기 제 2 기판(50)을 가열한다(S42). 상기 오븐(70)은 상기 제 2 기판(50)을 가열하여 상기 접착 층(30) 및/또는 상기 범프들(20)을 재 용융시킬 수 있다. 일 예에 따르면, 상기 오븐(70)은 하우징(72), 플레이트(74), 제 2 히터(76), 제 2 전원(78)을 포함할 수 있다. 상기 하우징(72)은 상기 제 2 기판(50)에 대해 외부로부터 밀폐된 공간을 제공할 수 있다. 상기 플레이트(74)는 상기 하우징(72)의 내부 바닥에 배치될 수 있다. 상기 플레이트(74)는 상기 제 2 기판(50)을 수납할 수 있다. 상기 제 2 히터(76)는 상기 플레이트(74) 내에 배치될 수 있다. 상기 제 2 전원(78)이 상기 제 2히터(76)에 제 2 히팅 파워를 공급하면, 상기 제 2 히터(76)는 상기 제 2 기판(50)을 가열시킬 수 있다. 상기 제 2 히터(76)는 상기 제 2 기판(50)을 약 100℃ 내지 약 150℃의 온도로 가열시킬 수 있다. 상기 제 2 기판(50)이 약 100℃ 내지 약 150℃의 온도로 가열되면, 상기 접착 층(30) 및/또는 상기 범프들(20)은 용융될 수 있다. 상기 용융된 접착 층(30)은 약 2000Paㆍsec 내지 약 3000Paㆍsec의 점도를 가질 수 있다. 이와 달리, 상기 접착 층(30)은 50℃ 내지 200℃의 온도에서 용융되고, 약 500Paㆍsec 내지 약 4000Paㆍsec의 점도를 가질 수 있다. 상기 하우징(72)은 공기 공급 부(80)에 연결될 수 있다. 9 and 13 , when a predetermined number of dies 40 are bonded onto the
도 10 및 도 13을 참조하면, 상기 공기 공급 부(80)는 상기 하우징(72) 내의 상기 접착 층(30)에 공기(82)를 제공하여 상기 접착 층(30) 내의 보이드(32)를 제거한다(S44). 상기 공기(82)는 질소 가스, 헬륨 가스, 산소 가스, 이산화탄소 가스, 또는 아르곤 가스를 포함할 수 있다. 상기 공기 공급 부(80)가 상기 하우징(72) 내에 상기 공기(82)를 제공하면, 상기 하우징(72) 내의 상기 공기(82)의 압력은 증가할 수 있다. 상기 하우징 (72) 내의 상기 공기(82)의 압력이 증가하면, 상기 접착 층(30)의 응집력 및/또는 표면 장력은 증가할 수 있다. 상기 접착 층(30)의 응집력 및/또는 표면 장력이 증가하면, 상기 보이드(32)는 상기 접착 층(30)의 외부로 배출되어 제거될 수 있다. 10 and 13 , the
도 14는 도 9의 하우징(72) 내의 공기(82)의 압력에 따른 보이드(32)의 제거율을 보여준다. FIG. 14 shows the removal rate of the void 32 according to the pressure of the
도 14를 참조하면, 상기 하우징(72) 내의 상기 공기(82)의 압력이 약 3기압(0.3Mpa) 이상일 경우, 상기 보이드(32)의 제거율은 97%이상일 수 있다. 상기 공기(82)의 압력이 약 7기압(0.7Mpa) 내지 약 10기압(1.0Mpa)일 경우, 상기 보이드(32)의 제거율은 거의 100%일 수 있다. 상기 공기(82)의 압력이 약 4기압(0.4Mpa) 일 경우, 상기 보이드(32)의 제거율은 거의 98%일 수 있다.상기 공기(82)의 압력이 약 1기압(0.1Mpa) 내지 약 2 기압(0.4Mpa)일 경우, 상기 보이드(32)의 제거율은 95%이하일 수 있다.Referring to FIG. 14 , when the pressure of the
도 15는 일반적인 진공 압력(vacuum pressure)에서의 접착 층(30)의 필렛(34)을 보여준다. 15 shows the
도 15를 참조하면, 상기 하우징(72) 내의 상기 공기(82)의 압력이 진공 압력으로 낮아지면, 상기 보이드(32)는 상기 접착 층(92) 내에서 급속히 제거되거나 감소될 수 있다. 공기 배기 부(90)는 상기 하우징(72)에 연결되어 상기 하우징(72) 내의 상기 공기(82)를 배기 및/또는 펌핑할 수 있다. 상기 하우징(72) 내의 상기 공기(82)의 압력은 진공 압력으로 낮아질 수 있다. 하지만, 상기 공기(82)의 압력이 진공 압력으로 낮아지면, 상기 접착 층(30)의 필렛(34)이 생성 및/또는 증가할 수 있다. 상기 필렛(34)은 상기 다이들(40)에 정렬되어야 할 상기 접착 층(30)이 상기 다이들(40)의 바깥으로 유출되는 결함(defect)이다. 상기 필렛(34)이 상기 다이들(40) 보다 높을 경우, 상기 다이들(40) 상에 형성될 패키지의 적층 불량(stack fault)이 야기될 수 있다. Referring to FIG. 15 , when the pressure of the
다시, 도 9를 참조하면, 공기 공급 부(80)는 상기 하우징(72) 내에 상압 또는 1 기압보다 높은 고압의 상기 공기(82)를 제공하여 상기 접착 층(30)의 상기 보이드(32)와 상기 필렛(34)의 결함을 감소시키거나 제거할 수 있다. Referring again to FIG. 9, an
이상, 첨부된 도면을 참조하여 본 발명의 실시 예를 설명하였지만, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자는 본 발명이 그 기술적 사상이나 필수적인 특징을 변경하지 않고서 다른 구체적인 형태로 실시될 수 있다는 것을 이해할 수 있을 것이다. 그러므로 이상에서 기술한 실시 예에는 모든 면에서 예시적인 것이며 한정적이 아닌 것으로 이해해야만 한다.Although the embodiments of the present invention have been described above with reference to the accompanying drawings, a person of ordinary skill in the art may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. You will understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.
Claims (10)
상기 제 1 기판과 다른 제 2 기판 상에 상기 다이를 본딩하는 단계; 및
상기 접착 층을 경화하는 단계를 포함하되,
상기 접착 층을 경화하는 단계는:
상기 제 2 기판을 가열하여 상기 접착 층을 용융시키는 단계; 및
상기 접착 층과 상기 제 2 기판에 상압보다 높은 고압의 공기를 제공하는 단계를 포함하는 플립 칩 본딩 방법.
Obtaining a die comprising a first substrate having an adhesive layer formed thereon;
Bonding the die on a second substrate different from the first substrate; And
Including curing the adhesive layer,
Curing the adhesive layer is:
Heating the second substrate to melt the adhesive layer; And
And providing air at a higher pressure than normal pressure to the adhesive layer and the second substrate.
상기 공기는 3기압 이상으로 제공되는 플립 칩 본딩 방법.
The method of claim 1,
Flip air bonding method wherein the air is provided to at least 3 atmospheres.
상기 접착 층은:
열경화성 수지; 및
상기 에폭시 수지를 경화시키는 경화제를 포함하되,
상기 에폭시 수지와 상기 경화제는 100J/g 내지 150J/g 단위 질량 당 발열량의 당량비를 갖는 플립 칩 본딩 방법.
The method of claim 1,
The adhesive layer is:
Thermosetting resins; And
Including a curing agent for curing the epoxy resin,
And the epoxy resin and the curing agent have an equivalent ratio of calorific value per unit mass of 100 J / g to 150 J / g.
상기 접착 층은 환원제를 더 포함하는 플립 칩 본딩 방법.
The method of claim 3, wherein
And the adhesive layer further comprises a reducing agent.
상기 환원제는
알코올성 수산기, 패놀성 수산기, 카르복실 산 및 질소함유 화합물 중 적어도 하나를 포함하되,
상기 알코올성 수산기는 Dimethanol, Diethylen glycol, Butanetriol, 및 Triethanolamine을 포함하되,
상기 패놀성 수산기는 Naphthol, Hydroxyhydroquinone, 및 Trihydroxybenzopyenone을 포함하되,
상기 카르복실 산은 Oxalic acid, Succinic acid, Malonic acid, Oxoacid 및 Carboxylic acid 유도체를 포함하되,
상기 질소 함유 화합물은 Imidazole 및 Amine을 포함하는 플립 칩 본딩 방법.
The method of claim 4, wherein
The reducing agent
At least one of an alcoholic hydroxyl group, a phenolic hydroxyl group, a carboxylic acid and a nitrogen-containing compound,
The alcoholic hydroxyl group includes Dimethanol, Diethylen glycol, Butanetriol, and Triethanolamine,
The phenolic hydroxyl group includes Naphthol, Hydroxyhydroquinone, and Trihydroxybenzopyenone,
The carboxylic acid includes oxalic acid, Succinic acid, Malonic acid, Oxoacid and Carboxylic acid derivatives,
The nitrogen-containing compound is a flip chip bonding method comprising Imidazole and Amine.
상기 제 2 기판이 50℃ 내지 200℃로 가열될 때, 상기 접착 층은 500Paㆍsec 내지 4000Paㆍsec의 점도를 갖는 플립 칩 본딩 방법.
The method of claim 1,
And the adhesive layer has a viscosity of 500 Pa.sec to 4000 Pa.sec when the second substrate is heated to 50 ° C to 200 ° C.
상기 접착 층을 경화하는 단계는 리플로우 방법을 포함하는 플립 칩 본딩 방법.
The method of claim 1,
Curing the adhesive layer comprises a reflow method.
상기 다이를 본딩하는 단계는 열 압착 방법을 포함하는 플립 칩 본딩 방법.
The method of claim 1,
Bonding the die comprises a thermocompression method.
상기 다이를 본딩하는 단계는:
상기 제 2 기판 상에 상기 다이를 제공하는 단계;
상기 다이를 가열하는 단계; 및
상기 제 2 기판에 상기 다이를 압착하는 단계를 포함하는 플립 칩 본딩 방법.
The method of claim 1,
Bonding the die is:
Providing the die on the second substrate;
Heating the die; And
And pressing the die onto the second substrate.
상기 다이는 150℃ 내지 300℃로 가열되는 플립 칩 본딩 방법.The method of claim 9,
The die is heated to 150 ° C to 300 ° C.
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6114239A (en) * | 1993-12-13 | 2000-09-05 | Micron Communications, Inc. | Electronic circuit bonding interconnect component and flip chip interconnect bond |
KR20090053954A (en) * | 2006-09-15 | 2009-05-28 | 린텍 가부시키가이샤 | Process for producing semiconductor device |
KR20150075026A (en) * | 2013-12-24 | 2015-07-02 | 닛토덴코 가부시키가이샤 | Adhesive film, dicing·die bond film, manufacturing method for semiconductor device, and semiconductor device |
KR20160045628A (en) * | 2013-08-22 | 2016-04-27 | 세키스이가가쿠 고교가부시키가이샤 | Semiconductor adhesive |
KR20180059901A (en) * | 2015-11-13 | 2018-06-05 | 후지필름 가부시키가이샤 | METHOD FOR PRODUCING LAMINATE, METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, AND LAMINATE |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7323360B2 (en) | 2001-10-26 | 2008-01-29 | Intel Corporation | Electronic assemblies with filled no-flow underfill |
KR101286379B1 (en) | 2003-11-10 | 2013-07-15 | 스태츠 칩팩, 엘티디. | Bump-on-lead flip chip interconnection |
JP2008135410A (en) | 2005-03-14 | 2008-06-12 | Matsushita Electric Ind Co Ltd | Method for mounting electronic component, circuit board having electronic component mounted thereon, and electronic equipment having circuit board mounted thereon |
JP4790587B2 (en) | 2006-12-20 | 2011-10-12 | 日本メクトロン株式会社 | Flip chip mounting method with no flow underfill |
US7829379B2 (en) | 2007-10-17 | 2010-11-09 | Analog Devices, Inc. | Wafer level stacked die packaging |
US8163597B2 (en) | 2009-03-24 | 2012-04-24 | Stats Chippac, Ltd. | Semiconductor device and method of forming no-flow underfill material around vertical interconnect structure |
KR101197193B1 (en) | 2010-01-05 | 2012-11-02 | 도레이첨단소재 주식회사 | Resin composition for no-flow underfill, no-flow underfill film using the same and manufacturing method thereof |
JP5619466B2 (en) | 2010-04-13 | 2014-11-05 | デクセリアルズ株式会社 | Curable resin composition, adhesive epoxy resin paste, die bond agent, non-conductive paste, adhesive epoxy resin film, non-conductive epoxy resin film, anisotropic conductive paste and anisotropic conductive film |
US8963340B2 (en) | 2011-09-13 | 2015-02-24 | International Business Machines Corporation | No flow underfill or wafer level underfill and solder columns |
US8946072B2 (en) | 2012-02-02 | 2015-02-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | No-flow underfill for package with interposer frame |
US9117813B2 (en) | 2012-06-15 | 2015-08-25 | General Electric Company | Integrated circuit package and method of making same |
KR20140044561A (en) | 2012-10-05 | 2014-04-15 | 삼성전기주식회사 | Printed circuit board and semiconductor package using the same, and method for manufacturing the printed circuit board and semiconductor package |
KR101753158B1 (en) | 2016-04-28 | 2017-08-09 | (주)이녹스첨단소재 | Composition for non-conductive film and non-conductive film including the same |
JP2017197688A (en) | 2016-04-28 | 2017-11-02 | 三井化学東セロ株式会社 | Insulation film for underfill |
KR101773711B1 (en) | 2016-06-02 | 2017-08-31 | 주식회사 케이씨씨 | Composition for Nonconductive Adhesive Film and Nonconductive Adhesive Film |
-
2018
- 2018-08-20 KR KR1020180096743A patent/KR102555721B1/en active IP Right Grant
-
2019
- 2019-08-06 US US16/533,450 patent/US10910339B2/en active Active
- 2019-08-15 CN CN201910752106.XA patent/CN110854028A/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6114239A (en) * | 1993-12-13 | 2000-09-05 | Micron Communications, Inc. | Electronic circuit bonding interconnect component and flip chip interconnect bond |
KR20090053954A (en) * | 2006-09-15 | 2009-05-28 | 린텍 가부시키가이샤 | Process for producing semiconductor device |
KR20160045628A (en) * | 2013-08-22 | 2016-04-27 | 세키스이가가쿠 고교가부시키가이샤 | Semiconductor adhesive |
KR20150075026A (en) * | 2013-12-24 | 2015-07-02 | 닛토덴코 가부시키가이샤 | Adhesive film, dicing·die bond film, manufacturing method for semiconductor device, and semiconductor device |
KR20180059901A (en) * | 2015-11-13 | 2018-06-05 | 후지필름 가부시키가이샤 | METHOD FOR PRODUCING LAMINATE, METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, AND LAMINATE |
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US20200058615A1 (en) | 2020-02-20 |
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