KR20190031107A - Resistive memory device including reference cell and method for controlling reference cell - Google Patents

Abstract

According to an exemplary embodiment of the present disclosure, provided is a controlling method of a reference cell included in a resistive memory for determining values stored in a plurality of memory cells, which comprises the following steps: writing a first value to the plurality of memory cells; providing reference currents, which are monotonically increasing or monotonically decreasing, to the reference cell; reading the plurality of memory cells from each of the reference currents; and determining a read reference current based on the read values.

Description

TECHNICAL FIELD [0001] The present invention relates to a resistive memory device including a reference cell, and a control method of the reference cell. BACKGROUND OF THE INVENTION < RTI ID = 0.0 >

Technical aspects of the present disclosure relate to a resistive memory device, and more particularly, to a resistive memory device including a reference cell and a control method of the reference cell.

The resistive memory device may store data in a memory cell that includes a variable resistance element. In order to detect the data stored in the memory cells of the resistive memory device, for example, a read current may be supplied to the memory cell, and the read current and the voltage by the variable resistive element of the memory cell may be detected.

In a memory cell in which a specific value is stored, the resistance value of the variable resistive element may have scattering, and scattering may vary due to PVT (Process Voltage Temperature) or the like. In order to accurately read the values stored in the memory cell, it may be important to set the threshold resistance accurately and quickly, which can distinguish the distributions of the resistance values corresponding to the different values.

The technical idea of the present disclosure relates to a resistive memory device, and more particularly, to a resistive memory device and a control method of a reference cell that can accurately read a value stored in a memory cell by controlling a reference cell.

According to an aspect of the technical idea of the present disclosure, a method of controlling a reference cell included in a resistive memory for determining values stored in a plurality of memory cells includes the steps of: Value reference currents for each of the reference currents, providing reference currents that monotonically increase or monotonically decrease the reference cells, read a plurality of memory cells at each of the reference currents, and determine a read reference current based on the read values Step < / RTI >

Also in accordance with an aspect of the technical aspects of the present disclosure, a method of controlling a reference cell included in a resistive memory for determining values stored in a plurality of memory cells includes the steps of writing a first value to a plurality of memory cells, Setting the resistance values of the reference resistance connected to the cell and passing through the reference current to be monotonic or monotonic; reading a plurality of memory cells from each of the resistance values of the reference resistance; And determining a resistance value.

In addition, according to one aspect of the technical aspects of the present disclosure, a resistive memory device that receives a reference adjustment signal includes a memory cell array including a memory cell and a reference cell, each connected to a different source line and each connected to a different bit line, A current source circuit configured to provide a read current and a variable reference current through the source lines to the memory cell and the reference cell, respectively, in response to the read command, an amplifier configured to sense a voltage between the source lines connected to the memory cell and the reference cell, And a control circuit configured to control the current source circuit such that the reference current is adjusted independently of the read current in accordance with the reference adjustment signal.

According to an exemplary embodiment of the present disclosure, by deriving an accurate threshold resistance through control of a reference cell, the values stored in the memory cells included in the resistive memory device can be read accurately independently of PVT and the like.

Further, according to an exemplary embodiment of the present disclosure, it is possible to provide an adaptive calibration according to the operating environment of the resistive memory device as well as the improved productivity of the resistive memory device by quickly detecting an accurate threshold resistance.

The effects obtainable in the exemplary embodiments of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned can be obtained from the following description of the exemplary embodiments of the present disclosure, And can be clearly understood and understood by those skilled in the art to which the embodiments belong. That is, unintended effects of implementing the exemplary embodiments of the present disclosure may also be derived from those of ordinary skill in the art from the exemplary embodiments of the present disclosure.

1 is a block diagram illustrating a memory device and a controller in accordance with an exemplary embodiment of the present disclosure;
Figure 2 is a timing diagram illustrating an example of the operation in which the memory device and controller of Figure 1 communicate in accordance with an exemplary embodiment of the present disclosure.
Figure 3 is an illustration of an example of the memory cell of Figure 1 in accordance with an exemplary embodiment of the present disclosure.
Figure 4 is a graph showing the distribution of the resistance value provided by the memory cell of Figure 3 in accordance with an exemplary embodiment of the present disclosure.
Figures 5A and 5B are block diagrams illustrating examples of the memory device of Figure 1 in accordance with exemplary embodiments of the present disclosure.
Fig. 6 is a circuit diagram showing an example of the current source circuit of Fig. 1 according to the exemplary embodiment of the present disclosure.
Figures 7A and 7B are circuit diagrams illustrating examples of the reference resistor circuit of Figure 1 in accordance with the exemplary embodiments of the present disclosure.
8 is a flow diagram illustrating a method of controlling a reference cell in accordance with an exemplary embodiment of the present disclosure.
FIGS. 9A and 9B are flowcharts illustrating examples of steps S200 through S600 of FIG. 8 in accordance with exemplary embodiments of the present disclosure.
10 is a flow chart illustrating an example of step S800 of FIG. 8 in accordance with an exemplary embodiment of the present disclosure.
Figure 11 is a graph illustrating an example of an operation in which the threshold resistance is determined by step S800a of Figure 10 according to an exemplary embodiment of the present disclosure.
Figure 12 is a flow chart illustrating an example of step S800 of Figure 8 in accordance with an exemplary embodiment of the present disclosure.
Figure 13 is a graph illustrating an example of an operation in which the threshold resistance is determined by step S800b of Figure 12 according to an exemplary embodiment of the present disclosure.
14 shows a block diagram of a memory device according to an exemplary embodiment of the present disclosure;
15 is a block diagram illustrating a system-on-chip that includes a memory device in accordance with an exemplary embodiment of the present disclosure.

1 is a block diagram illustrating a memory device 100 and a controller 200 in accordance with an exemplary embodiment of the present disclosure and FIGURE 2 illustrates a block diagram of a memory device 100 and a controller 200 of FIGURE 1 in accordance with an exemplary embodiment of the present disclosure. Fig. 2 is a timing chart showing an example of an operation in which the mobile station 200 communicates.

Referring to FIG. 1, a memory device 100 may communicate with a controller 200. The memory device 100 can receive a command CMD and an address ADDR from the controller 200 such as a write command and a read command and can receive the data DATA from the controller 200, (I.e., write data) or transmit the data (DATA) (i.e., read data) to the controller 200. [ 1, the memory device 100 may receive a reference adjustment signal ADJ from the controller 200. Although the command CMD, the address ADDR, the data DATA and the reference adjustment signal ADJ are separately shown in FIG. 1, in some embodiments, the command CMD, the address ADDR, And a reference adjustment signal ADJ may be transmitted through the same channel. 1, the memory device 100 includes a cell array 110, a current source circuit 120, a reference resistance circuit 130, an amplification circuit 140, a control circuit 150, and a nonvolatile memory 160 ).

The cell array 110 may include a plurality of memory cells. The memory cell M may include a variable resistive element (e.g., MTJ in FIG. 3), and the variable resistive element may have a resistance corresponding to a value stored in the memory cell M. Accordingly, the memory device 100 may be referred to as a resistive memory device, or a Resistive Random Access Memory (RRAM) device. For example, the memory device 100 may include a cell array 110 having a structure such as a PRAM (Phase Change Random Access Memory), a FRAM (Ferroelectric Random Access Memory) or the like, and a STT-MRAM (Magnetic Random Access Memory) structure such as a spin-torque magnetic random access memory (SPRAM), a Spin Torque Transfer Magnetization Switching RAM (SPAM), and a Spin Momentum Transfer have. As described below with reference to FIG. 3, exemplary embodiments of the present disclosure will be described primarily with reference to an MRAM, but it is noted that the exemplary embodiments of the present disclosure are not so limited.

The cell array 110 may include a reference cell R used to determine the value stored in the memory cell M. [ For example, as shown in FIG. 1, the cell array 110 may include a plurality of memory cells M and a reference cell R connected in common to a word line WLi, A plurality of memory cells M and a reference cell R commonly connected to the word line WLi can be simultaneously selected by the activated word line WLi. Although only one reference cell R is shown in FIG. 1, in some embodiments, the cell array 110 may include two or more reference cells connected to a word line WLi.

The current source circuit 120 may provide the read current I_RD and the reference current I_REF to the cell array 110. [ For example, the current source circuit 120 may provide the read current I_RD to the memory cell M and provide the reference current I_REF to the reference cell R. [ The current source circuit 120 can adjust the reference current I_REF according to the current control signal CC received from the control circuit 150. [ An example of the current source circuit 120 will be described later with reference to Fig.

The reference resistance circuit 130 may provide a resistance through which the reference current I_REF passes. For example, the reference resistance circuit 130 may provide a resistance having a reference resistance R_REF between the first node N1 and the second node N2. The reference resistance circuit 130 may adjust the reference resistance value R_REF according to the resistance control signal RC received from the control circuit 150. [ The resistance of the reference resistance circuit 130 may be different from the resistance formed inside the cell array 110 and may be better than the resistance formed within the cell array 110 in some embodiments, It can have more insensitive characteristics. Examples of the reference resistance circuit 130 will be described later with reference to FIGS. 7A and 7B.

The amplifying circuit 140 can receive the read voltage V_RD and the reference voltage V_REF and can determine the value stored in the memory cell M based on the read voltage V_RD and the reference voltage V_REF . For example, the amplifying circuit 140 can output a signal corresponding to the value stored in the memory cell M by comparing the read voltage V_RD and the reference voltage V_REF. The read voltage V_RD may include a voltage drop caused when the read current I_RD provided by the current source circuit 120 passes through the variable resistance element included in the memory cell M. [ The read voltage V_RD is not only the voltage drop due to the memory cell M but also the parasitic resistance in the path through which the read current I_RD passes (for example, the column decoder 170a, the source line SLj, , A bit line (BLj)).

Similar to the readout voltage V_RD, the reference voltage V_REF is set so that the reference current I_REF provided by the current source circuit 120 is the parasitic resistance of the path through which the reference current I_REF passes as well as the reference cell R For example, the column decoder 170a, the short-circuit source line SSL, and the short-circuit bit line SBL in FIG. 5A). The reference voltage V_REF may further include a voltage drop caused by the reference resistance R_REF provided by the reference resistance circuit 130. Thereby, the reference voltage V_REF can be adjusted by controlling the reference current I_REF and the reference resistance R_REF of the reference resistance circuit 130, and the reference for determining the value stored in the memory cell M is adjusted .

As described below with reference to FIG. 5A and the like, in some embodiments, the reference cell R may be a shorted cell that does not include a resistance element such as a variable resistance element. Thus, the reference voltage V_REF can be insensitive to the PVT fluctuation due to the characteristics of the reference resistance circuit 130, and when the reference voltage V_REF is accurately determined as described later with reference to Fig. 8 and the like, The operational reliability of the device 100 can be improved.

The control circuit 150 can control the current source circuit 120 and the reference resistance circuit 130 through the current control signal CC and the resistance control signal RC and can access the nonvolatile memory 160 have. In some embodiments, the control circuit 150 may generate a current control signal CC and a resistance control signal RC in accordance with a reference adjustment signal ADJ received from the controller 200. For example, the control circuit 150 may increase or decrease the reference current I_REF according to the reference adjustment signal ADJ and may increase or decrease the reference resistance R_REF of the reference resistance circuit 130 . As a result, the reference voltage V_REF can be adjusted according to the reference adjustment signal ADJ provided from the controller 200. [

In some embodiments, to adjust the reference voltage V_REF, one of the resistance of the reference current I_REF and the resistance of the reference resistance circuit 130 may be fixed. For example, when the reference current I_REF is fixed, the control circuit 150 may not generate the current control signal CC and may output the reference current Ip through the resistance control signal RC in accordance with the reference adjustment signal ADJ. The resistance value of the resistance circuit 130 can be adjusted. On the other hand, when the resistance value of the reference resistance circuit 130 is fixed, the control circuit 150 may not generate the resistance control signal RC and may generate the current control signal CC according to the reference adjustment signal ADJ. The reference current I_REF can be adjusted through the reference current I_REF.

The non-volatile memory 160 may store information about the reference voltage V_REF. For example, the non-volatile memory 160 stores information on a reference current used for a read operation of the memory cell M, that is, information on a read reference current, and a reference resistance used in a read operation of the memory cell M, You can store information about resistors. In some embodiments, the control circuit 150 receives information about the reference voltage V_REF in response to a command CMD (or setup command) that directs the setting of the reference voltage V_REF from the controller 200 to non-volatile Volatile memory 160 in response to a command CMD (or a read command) for instructing the reading of data from the memory 160. The current control signal CC and the resistance control signal RC). In some embodiments, non-volatile memory 160 may be omitted. For example, at least some of the memory cells included in the cell array 110 may store information about the reference voltage (V_REF) and may be accessed by the control circuitry 150.

The controller 200 may include a reference trimmer 210. The reference trimmer 210 can adjust the reference voltage V_REF of the memory device 100 through the reference adjustment signal ADJ and adjust the reference voltage V_REF based on the value read from the memory cell M in accordance with the adjusted reference voltage V_REF. The reference voltage V_REF to be used when reading the memory cell M, that is, the read reference voltage.

In some embodiments, the reference adjustment signal ADJ may be provided to the memory device 100 in synchronization with the read command, i.e., concurrently with the read command or following or preceding the read command. For example, as shown in Fig. 2, the controller 200 receives a read command (READ), a first address A1 (A1), and a second address A2 (A2) at a time t1 through a command CMD, an address ADDR and a reference adjustment signal ADJ And the first option OP1 to the memory device 100. [ The control circuit 150 of the memory device 100 may generate the current control signal CC and the resistance control signal RC in accordance with the first option OP1 and accordingly the reference current I_REF and the reference resistance circuit & The resistance value of the resistor 130 can be determined. The memory cell M and the reference cell R corresponding to the first address A1 can be selected in accordance with the read command READ and the read voltage V_RD according to the memory cell M and the reference voltage The value stored in the memory cell M can be determined by the current I_REF and the reference voltage V_REF according to the reference resistance value R_REF of the reference resistance circuit 130. [ The determined value may be provided to the controller 200 through the data DATA to the first output OUT1. Similarly, at time t2, in response to the read command (READ), the second address A2 and the second option OP2 of the controller 200, the memory device 100 outputs the second output OUT2 to the controller 200). 2, the reference adjustment signal ADJ may be provided to the memory device 100 in synchronization with a dedicated command different from the read command READ.

In some embodiments, the reference trimmer 210 may read a plurality of memory cells to which a predefined value has been written, according to reference voltages that are monotonic or monotonic decreasing, and read reference voltages Can be determined. By controlling the reference cell R in this manner, the accurate threshold resistance of the memory cell M can be derived, and the value stored in the memory cell M can be accurately read, as described later. In addition, an accurate threshold resistance can be quickly detected, thereby providing improved productivity of the resistive memory device 100 and adaptive calibration can be provided depending on the operating environment of the resistive memory device 100. [

3 is an illustration of an example of a memory cell M of FIG. 1 in accordance with an exemplary embodiment of the present disclosure, and FIG. 4 is a cross-sectional view of a memory cell M of FIG. This graph shows the scattering of the resistance value. Specifically, FIG. 3 shows a memory cell M 'including a MTJ (Magnetic Tunnel Junction) element as a variable resistance element, and FIG. 4 shows dispersion of a resistance value of the variable resistance element MTJ of FIG.

As shown in FIG. 3, the memory cell M 'may include a variable resistance element MTJ and a cell transistor CT connected in series between the bit line BLj and the source line SLj. In some embodiments, may be connected in the order of the variable resistive element MTJ and the cell transistor CT between the bit line BLj and the source line SLj, as shown in FIG. 3, 3, the cell transistor CT and the variable resistive element MTJ may be connected in this order between the bit line BLj and the source line SLj.

The variable resistance element MTJ may include a free layer FL and a pined layer PL and may include a barrier layer between the free layer FL and the pinned layer PL. BL). 3, the magnetization direction of the pinned layer PL may be fixed, while the free layer FL may have the same or opposite magnetization direction as the magnetization direction of the pinned layer PL. The variable resistive element MTJ can be referred to as being in a parallel state P when the pinned layer PL and the free layer FL have magnetization directions in the same direction while the pinned layer PL and the free layer & The variable resistive element MTJ may be referred to as being in an anti-parallel state AP when the floating point elements FL have magnetization directions opposite to each other. In some embodiments, the variable resistive element MTJ may further include an anti-ferromagnetic layer such that the pinned layer PL has a fixed magnetization direction.

The variable resistive element MTJ may have a relatively low resistance value R _P in the parallel state P and a relatively high resistance value R _AP in the antiparallel state AP. In this specification, when the variable resistance value element MTJ has a low resistance value R _P , the memory cell M 'stores'0', and when the variable resistance value element MTJ has a high resistance value R _AP The memory cell M 'is assumed to store a' 1 '. In this specification, the resistance value R _P corresponding to '0' may be referred to as a parallel resistance value R _P , and the resistance value R _AP corresponding to '1' may be referred to as an anti-parallel resistance value R _AP .

Referring to Fig. 4, the resistance value of the variable resistive element MTJ may have scattering. For example, as shown in FIG. 4, there may be a scatter (or first scatter) of the parallel resistance value R _P in memory cells storing '0', and in a memory cell storing a '1' There may be a scatter (or a second scatter) of antiparallel resistance values (R _AP ). In some embodiments, as shown in FIG. 4, the antiparallel resistance value R _AP may have a depletion that is worse than the parallel resistance value R _P , i.e., a dispersion having a higher dispersion. Further, as indicated by a dotted line in Fig. 4, the dispersion of the resistance value of the variable resistive element MTJ may be deteriorated due to various causes. Thus, the range of the threshold resistance value R _TH for distinguishing the dispersion of the parallel resistance value R _P and the dispersion of the antiparallel resistance value R _AP can be reduced, and the accurate threshold resistance value R _TH can be determined It can be important. As will be described later with reference to Figs. 8 to 13, according to the exemplary embodiments of the present disclosure, the dispersion of the resistance value of the variable resistive element MTJ can be estimated by controlling the reference cell R, The threshold resistance value R _TH can be determined based on the scattering.

Referring again to FIG. 3, the cell transistor CT may include a source and a drain connected to the gate connected to the word line WLi, the source line SLj, and the variable resistive element MTJ. The cell transistor CT can electrically connect or disconnect the variable resistive element MTJ and the source line SLj according to a signal applied to the word line WLi. For example, in order to write '0' to the memory cell M 'in a write operation, the cell transistor CT may be turned on and a current from the bit line BLj to the source line SLj may be The variable resistive element MTJ and the cell transistor CT. Further, in order to write '1' to the memory cell M ', the cell transistor CT can be turned on, and the current from the source line SLj to the bit line BLj is supplied to the cell transistors CT and It can pass through the variable resistive element MTJ. In the read operation, the cell transistor CT can be turned on and the current flowing from the bit line BLj to the source line SLj or the current flowing from the source line SLj to the bit line BLj, The current I_RD can pass through the cell transistor CT and the variable resistive element MTJ. It is assumed herein that the read current I_RD flows from the source line SLj to the bit line BLj.

Figures 5A and 5B are block diagrams illustrating examples of the memory device 100 of Figure 1 in accordance with the illustrative embodiments of the present disclosure. 5A and 5B illustrate memory devices 100a and 100b in a read operation and reference resistor circuits 130a and 130b in memory devices 100a and 100b may be arranged differently. Hereinafter, Figs. 5A and 5B will be described with reference to Fig. 1, and overlapping descriptions of Figs. 5A and 5B will be omitted.

5A, the memory device 100a may include a cell array 110a, a current source circuit 120a, a reference resistance circuit 130a, an amplification circuit 140a, and a column decoder 170a. The cell array 110a may include a memory cell M and a reference cell R connected in common to the word line WLi. The memory cell M may be connected to the bit line BLj and the source line SLj respectively and the reference cell R may be connected to the shorting bit line SBL and the shorting source line SSL respectively. The bit line BLj, the source line SLj, the shorting bit line SBL and the shorting source line SSL can be extended to the column decoder 170a.

The memory cell M may include a variable resistance element MTJ and a cell transistor CT connected in series between the bit line BLj and the source line SLj while the reference cell R may comprise a shorting bit line SBL and a cell transistor CT connected to the shorting source line SSL. The shorting bit line SBL and the shorting source line SSL can be electrically short-circuited or opened by the cell transistor CT of the reference cell R, May be referred to as a shorted cell. Connected to the shorting bit line SBL and the shorting source line SSL as shown in FIG. 5A in order to compensate for the voltage drop by the bit line BLj and the source line SLj connected to the memory cell M, The cell R may be disposed in the cell array 110a. 5A, the reference cell R may be a short-circuited cell, and accordingly, the voltage drop by the variable resistance element MTJ of the memory cell M may be referred to as a reference And can be compared with the voltage drop by the resistance element 130a. The reference resistance element 130a disposed outside the cell array 110a can provide a reference resistance value R_REF having a wide variable range and insensitivity to PVT, etc., as the cell array 110 deviates from the spatial structural constraints of the cell array 110 , So that the reference voltage V_REF can be accurately adjusted.

The column decoder 170a can route the bit line BLj, the source line SLj, the shorting bit line SBL and the shorting source line SSL according to the column address COL. The column address COL may be generated from the address ADDR received from the controller 200 of Fig. 1 and the column decoder 170a may be generated from the memory selected in accordance with the word line WLi activated in the cell array 110a At least some of the cells and the reference cells may be selected according to the column address COL. 5A, the column decoder 170a may connect the bit line BLj of the memory cell M to the negative supply voltage VSS and the source line SLj to the current source circuit < RTI ID = 0.0 > (120) a). The column decoder 170a may connect the shorting bit line SBL of the reference cell R to the reference resistance circuit 130a and may connect the shorting source line SSL to the current source circuit 120a. Thus, the read current I_RD can flow through the source line SLj, the memory cell M and the bit line BLj to the negative supply voltage VSS and the reference current I_REF flows through the short- (SSL), the reference cell R, the shorting bit line SBL and the reference resistance circuit 130a to the negative supply voltage VSS.

The amplifying circuit 140a can be connected to the nodes from which the read current I_RD and the reference current I_REF are outputted from the current supply circuit 120a and the voltages of the nodes such as the read voltage V_RD and the reference voltage V_REF (Q) < / RTI > The reference voltage V_REF can be determined by the reference resistance value R_REF and the reference current I_REF while the read voltage V_RD can be determined by the resistance value and the readout current I_RD of the variable resistance element MTJ of the memory cell M, . ≪ / RTI > The amplifying circuit 140a amplifies the voltage of the memory cell M when the read voltage V_RD is higher than the reference voltage V_REF (that is, when the resistance value of the variable resistance element MTJ of the memory cell M is larger than the threshold resistance R _TH ) When the read voltage V_RD is lower than the reference voltage V_REF (i.e., when the resistance value of the variable resistive element MTJ of the memory cell M is lower than the reference voltage V_REF) Threshold resistance value R _TH ), it is possible to generate the output signal Q corresponding to '0'.

5B, the memory device 100b may include a cell array 110b, a current source circuit 120b, a reference resistance circuit 130b, an amplification circuit 140b, and a column decoder 170b. Compared to the memory device 100a of FIG. 5A, the memory device 100b of FIG. 5B may include a reference resistor circuit 130b disposed between the column decoder 170b and the current source circuit 120b. Thus, the reference current I_REF can flow through the reference resistance circuit 130b, the short-circuit source line SSL, the reference cell R, and the short-circuit bit line SBL to the negative supply voltage VSS. Hereinafter, exemplary embodiments of the present disclosure will be described, by way of example, with the reference resistance circuit 130a disposed between the reference cell R and the negative supply voltage VSS, as in the memory device 100a of FIG. It is to be noted that the exemplary embodiments of the present disclosure are not limited thereto.

6 is a circuit diagram illustrating an example of the current source circuit 120 of FIG. 1 according to an exemplary embodiment of the present disclosure. The current source circuit 120 'of FIG. 6 can generate the read current I_RD and the reference current I_REF, and when n is a positive integer, the control circuit 150' The reference current I_REF can be adjusted according to the current control signal CC [1: n].

6, the current source circuit 120 'includes a plurality of transistors P0, P1, P2, ..., Pn, Pr having sources connected in common to a positive supply voltage VDD . The plurality of transistors P0, P1, P2, ..., Pn, Pr can be PMOS transistors and can form a current mirror. Accordingly, the current I_0 flowing through the transistor P0 and the current flowing from the positive supply voltage VDD depending on the size of each of the plurality of transistors P0, P1, P2, ..., Pn, The size can be determined. In some embodiments, transistor P0 and transistor Pr may have the same magnitude and thus readout current I_RD may have approximately the same magnitude as current I_0.

The n transistors P1, P2, ..., Pn that generate the reference current I_REF are connected to n transistors PS1, PS2, ..., Pn controlled by the current control signals CC [1: n] ., PSn), respectively. the current control signals CC [1: n] can be applied to the gates of the n transistors PS1, PS2, ..., PSn, The magnitude of the reference current I_REF can be determined. For example, when the transistor PS1 is turned on in accordance with the low level first current control signal CC [1], the current passing through the transistor P1 may be included in the reference current I_REF, The current by the transistor P1 can be excluded from the reference current I_REF when the transistor PS1 is turned off according to the high level first current control signal CC [1]. The n transistors P1, P2, ..., Pn may have the same size in some embodiments and may have different sizes in some embodiments.

Figures 7A and 7B are circuit diagrams illustrating examples of the reference resistance circuit 130 of Figure 1 in accordance with the illustrative embodiments of the present disclosure. As described above with reference to Fig. 1, the reference resistor circuits 130a ', 130a " of Figs. 7a and 7b can provide a resistance through which the reference current I_REF passes, and when m is a positive integer, The resistance value of the resistance, that is, the reference resistance value R_REF, can be adjusted according to the resistance control signals RC [1: m] of the control circuits 150a 'and 150a' '. The reference resistor circuits 130a 'and 130a " in FIGS. 7A and 7B have a reference resistance R_REF between the shorting source line SSL and the negative supply voltage VSS, as described above with reference to FIG. The overlapping contents of the description of Figs. 7A and 7B will be omitted.

Referring to FIG. 7A, the reference resistance circuit 130a 'includes a plurality of resistors R1a, R2a, ..., Rma and a plurality of resistors R1a, R2a, ..., Rma connected in series between the short-circuit source line SSL and the negative supply voltage VSS, (N1a, N2a, ..., Nma). The resistance control signals RC [1: m] can be applied to the gates of the plurality of transistors N1a, N2a, ..., Nma, The reference resistance value R_REF can be determined. For example, the reference resistance value R_REF can be determined by the first resistor R1a when the transistor N1a is turned on in accordance with the first resistance control signal RC [1] of the high level, The reference resistance value R_REF can be determined irrespective of the first resistor R1a when the transistor N1a is turned off according to the first resistance control signal RC [1] of the level. As a result, the reference resistance value R_REF of the reference resistance circuit 130a 'is set so that those selected by the resistance control signals RC [1: m] among the plurality of resistors R1a, R2a, ..., Rma are connected in parallel Can be determined from the equivalent circuit.

Referring to Figure 7B, the reference resistance circuit 130a " includes a plurality of resistors R1b, R2b, ..., Rmb connected in series between the short-circuit source line SSL and the negative supply voltage VSS And may include a plurality of transistors N1b, N2b, ..., Nmb connected in parallel with a plurality of resistors R1b, R2b, ..., Rmb. The plurality of transistors N1b, The resistance control signals RC [1: m] can be applied to the gates of the reference resistors R [1: N2b, ..., Nmb) For example, when the transistor N1b is turned off according to the first resistance control signal RC [1] of the low level, the reference resistance value R_REF is set to the resistance value of the first resistor R1b On the other hand, when the transistor N1b is turned on according to the high level first resistance control signal RC [1], the reference resistance value R_REF is set such that the turn-on resistance of the transistor N1b is approximately spirit( the reference resistance R_REF of the reference resistance circuit 130a " may be equal to or greater than the resistance value of the plurality of resistors R1b, R2b, ..., Rmb. The ones selected by the medium-resistance control signal RC [1: m] may be determined from an equivalent circuit connected in series.

8 is a flow diagram illustrating a method of controlling a reference cell in accordance with an exemplary embodiment of the present disclosure. As shown in FIG. 8, the method of controlling the reference cell may include a plurality of steps (S200, S400, S600, S800). In some embodiments, the method of FIG. 8 may be performed by a controller 200 that includes a reference trimmer 210 to control a reference cell R included in the memory device 100 of FIG. 1 Hereinafter, Fig. 8 will be described with reference to Fig.

In step S200, an operation of writing the same value to a plurality of memory cells may be performed. For example, an operation of writing '0' to a plurality of memory cells or writing '1' may be performed. The method of controlling the reference voltage in the subsequent step S400 may be determined according to the value written in the plurality of memory cells. An example of writing '0' to a plurality of memory cells will be described later with reference to FIG. 9A, and an example of writing '1' to a plurality of memory cells will be described below with reference to FIG. 9B.

In step S400, an operation of generating reference voltages for monotone increasing or monotonously decreasing may be performed. For example, there may be case where the writing of "0" corresponding to the parallel resistance (R _P) of the variable resistance element in the plurality of memory cells, to a reference voltage which monotonically increases from a minimum reference voltage generated in step S200. On the other hand, when '1' corresponding to the antiparallel resistance value R _AP of the variable resistive element is written in the plurality of memory cells in step S200, reference voltages that monotonously decrease from the maximum reference voltage can be generated.

In step S600, an operation of reading a plurality of memory cells at each of the reference voltages may be performed. For example, an operation of reading a plurality of memory cells at each of monotonically increasing reference voltages may be performed, and an operation of reading a plurality of memory cells at each of monotonically decreasing reference voltages may be performed. Examples of the foregoing steps S200 to S600 will be described later with reference to Figs. 9A and 9B.

In step S800, an operation of determining a read reference voltage based on the readout results may be performed. In some embodiments, the scattering (or first scattering) of the parallel resistance value R _P of the variable resistive element is obtained from results read from each of the monotonically increasing reference voltages on a plurality of memory cells written with '0' Can be estimated. In some embodiments, from the results read from each of the reference voltages for monotonically decreasing a plurality of memory cells written with ' 1 ', the dispersion of the antiparallel resistance value R _AP of the variable resistive element (i.e., ) Can be estimated. The threshold resistance value R _TH can be determined based on at least one of the estimated variations, and the read reference voltage can be determined from the threshold resistance value R _TH . Examples of step S800 will be described below with reference to FIGS. 10 to 13. FIG.

FIGS. 9A and 9B are flowcharts illustrating examples of steps S200 through S600 of FIG. 8 in accordance with exemplary embodiments of the present disclosure. As described above with reference to Fig. 8, an operation of writing the same value to a plurality of memory cells in steps S200a and S200b of Figs. 9A and 9B may be performed, and in step S400a and step S400b, And operations of reading a plurality of memory cells from each of the reference voltages in steps S600a and S600b may be performed. Hereinafter, Figs. 9A and 9B will be described with reference to Fig. 4 showing the scattering of the resistance value of Fig. 1 and the variable resistance element, and redundant contents of the description of Figs. 9A and 9B will be omitted.

Referring to FIG. 9A, in step S200a, an operation of writing '0' to a plurality of memory cells may be performed. For example, the controller 200 can transmit to the memory device 100 a command (CMD) for instructing writing, an address ADDR corresponding to a plurality of memory cells, and data (DATA) including '0' . Accordingly, the plurality of memory cells may have resistance values distributed as in the parallel resistance value (R _P ) dispersion of FIG. In some embodiments, a '0' may be written to a plurality of memory cells connected to one word line WLi in the cell array 110.

Step S400a may include steps S420a and S440a. In step S420a, an operation of setting a minimum reference current and a minimum reference resistance may be performed. For example, the controller 200 may send a reference adjustment signal ADJ corresponding to a minimum reference current and a minimum reference resistance to the memory device 100, and the control circuit 150 of the memory device 100 may control the reference adjustment The reference current I_REF and the reference resistance R_REF can be set to the minimum values respectively by generating the current control signal CC and the resistance control signal RC in response to the signal ADJ. Accordingly, the reference voltage V_REF determined by the reference current I_REF and the reference resistance R_REF may have a minimum value, and the threshold resistance value R _TH corresponding to the reference voltage V_REF may be the parallel resistance value R _P ) ≪ / RTI >

In some embodiments, the reference current I_REF and the reference resistance R_REF may not be set to a minimum value. For example, for the reference voltage (V_REF) corresponding to the parallel resistance (R _P) changes, the parallel resistance (R _P) have an average lower threshold resistance (R _TH), which may have dispersion on the basis of the distribution of, An arbitrary reference current I_REF and a reference resistance R_REF may be set. As shown in Fig. 9A, step S620a may be performed following step S420a.

In step S620a, an operation of reading out a plurality of memory cells may be performed. For example, the controller 200 can transmit to the memory device 100 a command CMD for instructing reading and an address ADDR corresponding to a plurality of memory cells. In some embodiments, as described above with reference to Fig. 2, the command CMD for reading and the address ADDR are set to the reference adjustment signal ADJ for setting the minimum reference current and the minimum reference resistance of step S420a, And may be transmitted to the memory device 100 in synchronism. The memory device 100 may transmit to the controller 200 data (DATA) including the result of reading out the memory cells to which '0' has been written using the minimum reference current according to the set minimum reference current and the minimum reference resistance .

In step S640a, an operation of determining whether to re-execute the read operation of a plurality of memory cells may be performed based on the number of '0' included in the readout result. For example, as shown in FIG. 9A, the reference trimmer 210 of the controller 200 determines whether the number of '0' included in the data (DATA) received from the memory device 100, that is, (X> 0) and the number of '0' is greater than or equal to 'X', the setting of the reference current and the reference resistance, and the setting of the reference current for a plurality of memory cells The reading can be stopped, while if not, step S440a can be performed subsequently. That is, the setting operation of the reference current I_REF and the reference resistance value R_REF and the read operation of the plurality of memory cells until '0' is read out from the predetermined number of memory cells among the plurality of memory cells written '0' The operation can be repeated. In some embodiments, 'X' may match the number of memory cells written '0', and 'X' in some embodiments may be half the number of memory cells written '0'.

In step S440a, an operation of setting the increased reference current and / or the increased reference resistance may be performed. For example, the controller 200 may send a reference adjustment signal ADJ corresponding to an increased reference current and / or an increased reference resistance to the memory device 100 and may be coupled to the control circuit 150 of the memory device 100 May generate the current control signal CC and / or the resistance control signal RC in response to the reference adjustment signal ADJ to set the increased reference current I_REF and the increased reference resistance R_REF. Accordingly, the reference voltage V_REF can also increase, and the threshold resistance value R _TH corresponding to the reference voltage V_REF can be shifted to the right in the dispersion of the parallel resistance value R _P in Fig.

When steps S440a and S600a are repeated, the threshold resistance value R _TH can be shifted to the right in the dispersion of the parallel resistance value R _P in accordance with the gradually increasing reference voltage V_REF. Accordingly, the variation of the parallel resistance (R _P) in the process of moving from the left to the right of distribution of the threshold resistance (R _TH) is parallel to the resistance (R _P) may be estimated. The operation of estimating the scattering following step S600a and determining the read reference voltage from the estimated scatter, that is, examples of step S800 in Fig. 8 will be described below with reference to Figs. 10 to 13. Fig.

Referring to FIG. 9B, in step S200b, an operation of writing '1' to a plurality of memory cells may be performed. Thus, the plurality of memory cells may have resistive values distributed as an antiparallel resistance (R _AP ) spread of FIG.

Step S400b may include steps S420b and S440b. In step S420b, an operation of setting the maximum reference current and the maximum reference resistance may be performed. For example, the controller 200 may transmit a reference adjustment signal ADJ corresponding to a maximum reference current and a maximum reference resistance to the memory device 100, and the control circuit 150 of the memory device 100 may control the reference adjustment The reference current I_REF and the reference resistance R_REF can be respectively set to the maximum value by generating the current control signal CC and the resistance control signal RC in response to the signal ADJ. Accordingly, the reference voltage V_REF determined by the reference current I_REF and the reference resistance R_REF may have a maximum value, and the threshold resistance R _TH corresponding to the reference voltage V_REF may be the antiparallel resistance value R _AP ). ≪ / RTI >

In some embodiments, the reference current I_REF and the reference resistance R_REF may not be set to a maximum value. For example, the reference voltage (V_REF) corresponding to anti-parallel to the resistance value on the basis of the variation in the distribution of (R _AP), anti-parallel to the resistance value (R _AP) the average higher than the threshold resistance (R _TH), which may have dispersion in , An arbitrary reference current I_REF and a reference resistance R_REF may be set. As shown in Fig. 9B, subsequent to step S420b, step S620b may be performed.

In step S620b, an operation of reading out a plurality of memory cells may be performed. Accordingly, the memory device 100 outputs data (DATA) including the result of reading the memory cells in which '1' is written to the controller 200 using the maximum reference current according to the set maximum reference current and the maximum reference resistance Lt; / RTI >

In step S640b, an operation of determining whether or not the read operation of the plurality of memory cells is performed again based on the number of '1' included in the readout result may be performed. 9B, the reference trimmer 210 of the controller 200 counts the number of '1's included in the data (DATA) received from the memory device 100, that is, the stored value is' 1' (Y> 0), and when the number of '1's is greater than or equal to' Y ', the reference current and the reference resistance are set and the number of memory cells read to the plurality of memory cells The reading can be stopped, but if not, step S440b can be performed subsequently. That is, the setting operation of the reference current I_REF and the reference resistance value R_REF and the read operation of the plurality of memory cells until '1' is read out from a predetermined number of memory cells among the plurality of memory cells written '1' The operation can be repeated. In some embodiments, 'Y' may correspond to the number of memory cells in which '1' is written, and in some embodiments, 'Y' may be one-half of the number of memory cells in which '1' is written.

In step S440b, an operation of setting a reduced reference current and / or a reduced reference resistance may be performed. Accordingly, the reference voltage V_REF can also be reduced, and the threshold resistance value R _TH corresponding to the reference voltage V_REF can be shifted to the left in the dispersion of the antiparallel resistance value R _AP in FIG.

When step S440b and step S600b are repeated, the threshold resistance R _TH can be shifted to the left in the dispersion of the antiparallel resistance value R _AP in accordance with the gradually decreasing reference voltage V_REF. Accordingly, the distribution of anti-parallel to the resistance value (R _AP) can be estimated in the process of moving to the left to the right of distribution of analogy to the example of Figure 9a, the threshold resistance (R _TH) antiparallel the resistance value (R _AP) .

FIG. 10 is a flow chart illustrating an example of step S800 of FIG. 8 in accordance with an exemplary embodiment of the present disclosure, and FIG. 11 is a flowchart of an operation in which the threshold resistance is determined by step S800a of FIG. 10 according to an exemplary embodiment of the present disclosure. FIG. Specifically, the step S800a of FIG. 10 includes a threshold resistance value R _TH derived from a plurality of memory cells written as' 0 'as described above with reference to FIG. 9A, and a threshold resistance R _TH from' 1 May be performed after the threshold resistance value R _TH derived from the plurality of memory cells written in 'is prepared. As described above with reference to Fig. 8, in step S800a of Fig. 10, an operation of determining a read reference voltage based on the results read out from each of the reference voltages may be performed.

In step S820a, an operation of estimating the dispersion of the parallel resistance value R _P and the dispersion of the antiparallel resistance value R _AP may be performed. For example, the threshold resistance value R _TH derived from the example of Fig. 9A can be estimated as the average (R _P ') of the dispersion of the parallel resistance value R _P. In some embodiments, if '0' is written and the number of memory cells to be read is relatively large, then it can be determined whether a '0' is read from more than half of the memory cells (ie, Is a half of the number of memory cells in which " 0 " is written), the threshold resistance R _{TH in} such a case can be estimated as an average of the dispersion of the parallel resistance value R _P. In some embodiments, if '0' is written and the number of memory cells to be read is relatively small, then it can be determined whether a '0' is read from all of the memory cells (ie, 'X' 0 " matches the number of written memory cells), the threshold resistance R _{TH in} such a case can be estimated as an average of the dispersion of the parallel resistance value R _P. Likewise, the threshold resistance R _TH derived in the example of FIG. 9B can be estimated as the mean (R _AP ') of the dispersion of the antiparallel resistance value R _AP . In some embodiments, if a '1' is written and a relatively large number of memory cells are read, 'Y' in FIG. 9B may be one-half the number of memory cells in which '1' is written, 'Y' in FIG. 9B may match the number of the memory cells in which '1' is written when '1' is written and the number of the memory cells to be read is relatively small. Accordingly, as shown in Figure 11, the mean (R _P ') of the parallel resistance (R _P) dispersion and a high resistance value is parallel resistance value position of the distribution of (R _AP) (R _P) of by the steps S820a and half Can be estimated by the average (R _AP ') of the parallel resistance values (R _AP ). By thus estimating the average, the dispersion of the resistance value can be estimated quickly.

In step S840a, an operation of calculating the threshold resistance value R _TH from the dispersion of the parallel resistance value R _P and the dispersion of the antiparallel resistance value R _AP may be performed. In some embodiments, offsets based on the standard deviations of the estimated distributions may be reflected in the average, and the threshold resistance R _TH may be calculated from the results that reflect the offset. The standard deviations can be derived in advance by testing a variable resistance value element (e.g., MTJ in FIG. 3), and the threshold resistance R _TH can be determined more accurately as the standard deviation is reflected in the estimated average. For example, as shown in FIG 11, a and b is greater than zero (zero), offset relative to the standard deviation (σ _P) to the mean (R _P ') of the parallel resistance (R _P) (a ? _P ) can be added. Further, an offset b · σ _AP proportional to the standard deviation σ _AP can be subtracted from the average (R _AP ') of the antiparallel resistance value (R _AP ). Accordingly, the threshold resistance value R _TH is a value (R _P '+ a · σ _P , R _AP ' - b · R _AP ) in which the standard deviations σ _A and σ _AP are reflected in the averages R _P 'and R _AP 'lt; / RTI > _AP ) as factors. In some embodiments, the threshold resistance (R _TH ) for reading a memory cell may be calculated as: " (1) "

In step S860a, an operation of determining the read reference current and / or the read reference resistance may be performed. For example, the reference trimmer 210 can calculate the reference voltage V_REF corresponding to the threshold resistance R _TH calculated in step S840a, that is, the reference voltage V_REF corresponding to the reference voltage V_REF I_REF and the reference resistance R_REF as the read reference current and the read reference resistance. Information about the determined read reference current and the read reference resistance may be communicated to the control circuit 150 of the memory device 100 and the control circuit 150 may provide information about the read reference current and the read reference resistance to the read reference voltage Can be stored in the non-volatile memory 160 as information on the non-volatile memory.

Fig. 12 is a flow chart illustrating an example of step S800 of Fig. 8 in accordance with an exemplary embodiment of the present disclosure, and Fig. 13 is a flowchart of an operation in which the threshold resistance is determined by step S800b of Fig. 12 according to an exemplary embodiment of the present disclosure FIG. More specifically, the step S800b of FIG. 12 can use only the threshold resistance value R _TH determined from the plurality of memory cells written '0' as described above with reference to FIG. 9A, as compared with the step S800a of FIG. As described above with reference to Fig. 8, in step S800b of Fig. 12, an operation of determining a read reference voltage based on the results read out from each of the reference voltages may be performed. Hereinafter, the description overlapping with the description of FIG. 10 of the description of FIG. 12 will be omitted.

In step S820b, an operation of estimating the dispersion of the parallel resistance value R _P may be performed. A threshold resistance (R _TH) obtained in the example of Figure 10, in analogy to step S820a of Fig. 9a may be estimated as the average (R _P ') parallel to the dispersion of the resistance (R _P). Accordingly, as shown in FIG. 13, the position of the dispersion of the parallel resistance value R _P can be estimated by the average R _P '. In some embodiments, depending on the characteristics of the variable resistance element, antiparallel the resistance value (R _AP) are so may have a deteriorated than parallel resistance (R _P) dispersion, the dispersion of the parallel resistance (R _P) may be used .

In step S840b, an operation of calculating the threshold resistance value R _TH from the dispersion of the parallel resistance value R _P may be performed. In some embodiments, the offset based on the standard deviation of the estimated scatter can be reflected in the average, and the threshold resistance R _TH can be calculated from the offset reflection result. For example, an offset which is proportional to the standard deviation (σ _P) to the mean (R _P ') of, when c is greater than zero (zero), a parallel resistance (R _P) as shown in Figure 13 (c · σ _P ) can be added. Accordingly, the threshold resistance value R _TH can be calculated by a function g having a value (R _P '+ c · σ _P ) in which the standard deviation (σ _P ) is reflected to the average (R _P ') . In some embodiments, the threshold resistance (R _TH ) for reading a memory cell may be calculated as: < EMI ID = 2.0 >

In step S860b, an operation of determining the read reference current and / or the read reference resistance may be performed. For example, the reference trimmer 210 can calculate the reference voltage V_REF corresponding to the threshold resistance R _TH calculated in step S840b, that is, the reference voltage V_REF corresponding to the reference voltage V_REF I_REF and the reference resistance R_REF as the read reference current and the read reference resistance. Information about the determined read reference current and the read reference resistance may be communicated to the control circuit 150 of the memory device 100 and the control circuit 150 may provide information about the read reference current and the read reference resistance to the read reference voltage Can be stored in the non-volatile memory 160 as information on the non-volatile memory.

14 shows a block diagram of a memory device 300 in accordance with an exemplary embodiment of the present disclosure. 14, the memory device 300 may include an amplifier circuit 340, a control circuit 350, a non-volatile memory 360, and a reference trimmer 370. Although not shown in FIG. 14, the memory device 300 of FIG. 14 may include a cell array, a current source circuit, and a reference resistance circuit, similar to the memory device 100 of FIG. Hereinafter, the description overlapping with the description of FIG. 1 in the description of FIG. 14 will be omitted.

Compared to the memory device 100 of FIG. 1, the memory device 300 of FIG. 14 may receive a calibration signal (CAL) and may further include a reference trimmer 370. Thus, the memory device 300 may derive its own correct reference voltage in response to the calibration signal CAL, and the system including the memory device 300 may issue a calibration signal (CAL) to the memory device 300 The operation reliability of the memory device 300 can be maintained.

In response to the received calibration signal (CAL), the reference trimmer 370 may write the same value to a plurality of memory cells of the cell array and cause the control circuit 350 to generate reference voltages that are monotonically increasing or monotonically decreasing Signal. The reference trimmer 370 may receive a signal corresponding to the values read from the plurality of memory cells at each of the reference voltages from the amplifier circuit 340 and may determine the read reference voltage based on the read values. The reference trimmer 370 can provide information about the read reference voltage to the control circuit 350 and the control circuit 350 can store information about the read reference voltage in the nonvolatile memory 360. [ Thereafter, when the memory device 300 receives the read command, the control circuit 350 controls the reference current I_REF so that the read reference voltage is generated based on the information about the read reference voltage stored in the non-volatile memory 360. [ And / or the reference resistance value R_REF.

FIG. 15 is a block diagram illustrating a system-on-a-chip 400 including a memory device according to an exemplary embodiment of the present disclosure. System on Chip (SoC) 400 may refer to an integrated circuit that integrates components of a computing system or other electronic system. For example, as system-on-a-chip 400, an application processor (AP) may include components for a processor and other functions. 15, the system-on-chip 400 includes a core 410, a DSP (Digital Signal Processor) 420, a GPU (Graphic Processing Unit) 430, an internal memory 440, A memory interface 450 and a memory interface 460. The components of system-on-chip 400 may communicate with each other via bus 470.

The core 410 may process instructions and may control the operation of components included in the system-on-chip 400. For example, the core 410 may operate an operating system and execute applications on the operating system by processing a series of instructions. The DSP 420 may generate useful data by processing a digital signal, e.g., a digital signal provided from the communication interface 450. [ The GPU 430 may generate data for image output from the image data provided from the built-in memory 440 or the memory interface 460 through the display device, and may encode the image data.

Internal memory 440 may store data required for core 410, DSP 420 and GPU 430 to operate. The embedded memory 440 may include a resistive memory in accordance with an exemplary embodiment of the present disclosure, so that the embedded memory 440 can provide high reliability due to an accurate reference voltage.

The communication interface 450 may provide a communication network or an interface for one-to-one communication. The memory interface 460 may provide an interface to the external memory of the system-on-chip 400, for example, a dynamic random access memory (DRAM), a flash memory, and the like.

As described above, exemplary embodiments have been disclosed in the drawings and specification. Although the embodiments have been described herein with reference to specific terms, it should be understood that they have been used only for the purpose of describing the technical idea of the present disclosure and not for limiting the scope of the present disclosure as defined in the claims . Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the present invention. Accordingly, the true scope of protection of the present disclosure should be determined by the technical idea of the appended claims.

Claims (10)

A method of controlling a reference cell included in a resistive memory for determining values stored in a plurality of memory cells,
Writing a first value to the plurality of memory cells;
Providing reference currents that monotonically increase or monotonically decrease in the reference cell;
Reading the plurality of memory cells at each of the reference currents; And
And determining a read reference current based on the read values. The method according to claim 1,
Further comprising setting resistance values of the reference resistance connected to the reference cell and through which the reference current passes,
Wherein the reading step reads the plurality of memory cells in each of the resistance values of the reference currents and the reference resistance,
And determining a read reference resistance value based on the read values. The method according to claim 1,
The step of determining the read reference current may include estimating a first spread of the resistance value corresponding to the first value of the memory cell based on the number of the first ones of the read values Of the reference cell. The method of claim 3,
Wherein the first value and the second value different from the first value correspond to a low resistance value and a high resistance value of the plurality of memory cells, respectively,
Wherein providing the reference currents comprises providing monotonically increasing reference currents,
Wherein the step of estimating the first scattering estimates a resistance value of a memory cell corresponding to a reference current when the number of the first values is equal to or greater than a predetermined number as a mean of the first scattering, Cell control method. The method of claim 4,
Writing the second value to the plurality of memory cells;
Wherein providing the reference currents further comprises providing monotonically decreasing reference currents,
Wherein determining the read reference current further comprises estimating a second dispersion of the resistance value corresponding to the second value of the memory cell based on the number of the second one of the readout values,
Wherein the step of estimating the second scattering estimates the resistance value of the memory cell corresponding to the reference current when the number of the second values is equal to or greater than a predetermined number as an average of the second scattering, Way. The method of claim 5,
Wherein the step of determining the read reference current comprises the steps of: calculating a first resistance value by adding a resistance value based on a standard deviation of the first dispersion to an average of the first dispersion; And the reference current corresponding to the intermediate value of the second resistance value obtained by subtracting the basic resistance value is determined as the read reference current. The method of claim 4,
Wherein the step of determining the read reference current further comprises calculating the read reference current based on a predefined function having an average of the first spread as a factor. The method according to claim 1,
And writing control information corresponding to the read reference current to the resistive memory. A method of controlling a reference cell included in a resistive memory for determining values stored in a plurality of memory cells,
Writing a first value to the plurality of memory cells;
Setting resistance values connected to the reference cell and monotonically increasing or monotonically decreasing of the reference resistance through which the reference current passes;
Reading the plurality of memory cells at each of the resistance values of the reference resistors; And
And determining a read reference resistance based on the read values. 1. A resistive memory device for receiving a reference adjustment signal,
A cell array including a memory cell and a reference cell each connected to different source lines and connected to different bit lines, respectively;
A current source circuit configured to provide a read current and a variable reference current through the source lines to the memory cell and the reference cell, respectively, in response to the read command;
An amplifying circuit configured to sense a voltage between the source lines connected to the memory cell and the reference cell, respectively; And
And a control circuit configured to control the current source circuit such that the reference current is adjusted independently of the read current in accordance with the reference adjustment signal.

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