JP2017107620A - Semiconductor device and nonvolatile memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of coping with arbitrary variations.SOLUTION: A semiconductor device 10 comprises: a plurality of memory cells 11 including a memory cell outputting first data corresponding to a first storage state and a memory cell outputting second data corresponding to a second storage state; a first mean value determination circuit 12 for determining a mean value of a plurality of pieces of the first data; a second mean value determination circuit 13 for determining a mean value of a plurality of pieces of the second data; a threshold value determination circuit 14 for determining a threshold value which identifies the first and second storage states on the basis of the respective determination results of the first mean value determination circuit 12 and the second mean value determination circuit 13; and an identification circuit 15 for identifying a storage state of the plurality of memory cells on the basis of the determination result of the threshold value determination circuit 14 and the readout result of the plurality of memory cells.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device and a nonvolatile memory, for example, a semiconductor device having a memory cell and a nonvolatile memory.

  In recent years, electrically rewritable nonvolatile memories (nonvolatile memory devices) have been widely used. A flash memory, which is one type of nonvolatile memory, is used as a storage device built in many electronic devices such as personal computers, digital cameras, and mobile phones, or as an external storage device. In addition, ReRAM (resistance random access memory), which is another nonvolatile memory, uses a change in resistance due to voltage application, consumes little power, can be highly integrated, and can be read. Due to its high speed, it is attracting attention as an alternative to flash memory.

  For example, Patent Documents 1 and 2 are known as techniques related to the nonvolatile memory.

Japanese Patent Laid-Open No. 11-297084 JP 2009-009688 A

  In the nonvolatile memory, a threshold value is set to determine the ON / OFF state (for example, the state corresponding to 1/0 of the stored data) of the memory cell to be read. In Patent Document 1, paying attention to the temperature dependence of the threshold value, the temperature of the semiconductor chip is measured with a thermometer on the semiconductor chip, and the threshold value is appropriately changed according to the temperature characteristics of the memory cell.

  However, the related technique such as Patent Document 1 has a problem that it can cope with variations due to temperature changes of the semiconductor chip but cannot cope with other variations such as process variations and voltage variations.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, a semiconductor device includes a plurality of memory cells, a first intermediate value determination circuit, a second intermediate value determination circuit, a threshold value determination circuit, and an identification circuit. The plurality of memory cells include a memory cell that outputs first data corresponding to the first storage state and a memory cell that outputs second data corresponding to the second storage state. The first intermediate value determination circuit determines intermediate values of the plurality of first data, and the second intermediate value determination circuit determines intermediate values of the plurality of second data. The threshold value determination circuit determines a threshold value for identifying the first and second storage states based on the determination results of the first and second intermediate value determination circuits. The identification circuit identifies the storage states of the plurality of memory cells based on the determination result of the threshold value determination circuit and the read result from the plurality of memory cells.

  According to the one embodiment, it is possible to cope with an arbitrary variation.

1 is a configuration diagram showing a schematic configuration of a semiconductor device according to a first embodiment. FIG. 6 is a distribution diagram illustrating a characteristic distribution of the semiconductor device according to the first embodiment. 1 is a configuration diagram illustrating a configuration example of a nonvolatile memory according to a first embodiment. 3 is a configuration diagram showing a configuration example of a memory cell according to the first embodiment. FIG. FIG. 3 is a configuration diagram showing a configuration example of a memory cell array according to the first embodiment. FIG. 3 is a configuration diagram illustrating a configuration example of a memory cell and a sense amplifier according to the first embodiment. 4 is a distribution diagram showing a characteristic distribution of the nonvolatile memory according to Embodiment 1. FIG. 3 is a flowchart showing an operation of the nonvolatile memory according to the first embodiment. 6 is a distribution diagram showing a characteristic distribution of a nonvolatile memory according to Modification 1 of Embodiment 1. FIG. 10 is a table showing symbols used in the nonvolatile memory according to Modification 2 of Embodiment 1. 10 is a table showing symbols used in the nonvolatile memory according to Modification 2 of Embodiment 1. FIG. 10 is a configuration diagram illustrating a configuration example of a median value detection circuit according to a third modification of the first embodiment. FIG. 10 is a configuration diagram illustrating a configuration example of a median value detection circuit according to a third modification of the first embodiment. FIG. 10 is a configuration diagram illustrating a configuration example of a median value detection circuit according to a third modification of the first embodiment. FIG. 6 is a diagram illustrating an operation flow of the nonvolatile memory according to the second embodiment. FIG. 6 is a diagram illustrating an operation flow of the nonvolatile memory according to the second embodiment. FIG. 6 is a configuration diagram illustrating a configuration example of a nonvolatile memory according to a third embodiment.

  For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. Each element described in the drawings as a functional block for performing various processes can be configured by a CPU, a memory, and other circuits in terms of hardware, and a program loaded in the memory in terms of software. Etc. Therefore, it is understood by those skilled in the art that these functional blocks can be realized in various forms by hardware only, software only, or a combination thereof, and is not limited to any one. Note that, in each drawing, the same element is denoted by the same reference numeral, and redundant description is omitted as necessary.

(Embodiment 1)
The first embodiment will be described below with reference to the drawings.

<Outline of Embodiment 1>
FIG. 1 shows a schematic configuration of a semiconductor device according to the present embodiment. As shown in FIG. 1, the semiconductor device 10 according to the present embodiment includes a plurality of memory cells 11, a first intermediate value determination circuit 12, a second intermediate value determination circuit 13, a threshold value determination circuit 14, and an identification circuit 15. It has.

  The plurality of memory cells 11 include a memory cell that outputs first data corresponding to the first storage state and a memory cell that outputs second data corresponding to the second storage state. The first intermediate value determination circuit 12 determines intermediate values of the plurality of first data, and the second intermediate value determination circuit 13 determines intermediate values of the plurality of second data.

  The threshold value determination circuit 14 determines threshold values for identifying the first and second storage states based on the determination results of the first intermediate value determination circuit 12 and the second intermediate value determination circuit 13. The identification circuit 15 identifies the storage state of the plurality of memory cells 11 based on the determination result of the threshold value determination circuit 14 and the read result from the plurality of memory cells 11.

  FIG. 2 shows an example of variation due to temperature change in the distribution of the first state (first data) and the second state (second data) of the memory cell 11. FIG. 2A shows the distribution at room temperature, and FIG. 2B shows the distribution at high temperature. When the temperature changes from room temperature to high temperature, the distribution of the first state and the second state shifts. If an offset due to this variation can be predicted, the margin can be reduced. Therefore, in the present embodiment, the threshold value is determined based on the intermediate value (for example, the center value or the average value) of the first data and the intermediate value of the second data. That is, the threshold value is shifted according to the shift of the distribution. As a result, the threshold value can be set not only for the temperature change but also for other variations, and can operate with a small margin.

<Configuration of Nonvolatile Memory of First Embodiment>
FIG. 3 shows a configuration example of the nonvolatile memory according to this embodiment. As shown in FIG. 3, the nonvolatile memory (semiconductor device) 1 according to the present embodiment includes a memory cell array 100 and a read circuit 200.

  The memory cell array 100 is a memory cell array of a nonvolatile memory, and includes a memory cell 101, a sense amplifier 102, and an analog comparator 103 for each bit to be stored. The memory cell array 100 includes a large number of nonvolatile memory cells 101 corresponding to the bits to be stored, and data is simultaneously read from n (n> 2) of the memory cells 101. By providing the analog comparator 103 that compares a plurality of reference voltages (VREF) for each memory cell 101, data can be simultaneously read from the plurality of memory cells. Here, the data written in the nonvolatile memory (memory cell array) is assumed to be n bits by converting the original k bits (k <n) data into an error correction code (ECC). In this embodiment, it is assumed that n-bit read data always includes at least one bit in the ON state (one of 0 or 1) and one bit in the OFF state (the other of 0 or 1).

  For example, when the nonvolatile memory is a resistance change memory (ReRAM), the resistance value corresponding to the ON state or the OFF state is read from the memory cell 101. Each memory cell 101 is connected to a separate sense amplifier 102. The sense amplifier 102 reads the resistance value of the memory cell 101 and outputs a corresponding voltage. Here, an example of the sense amplifier 102 that outputs a voltage inversely proportional to the input current will be described. That is, the higher the resistance value of the memory cell 101, the smaller the value of the flowing current, and the higher the output voltage of the sense amplifier 102. Here, for example, a sense amplifier 102 that outputs a current or a sense amplifier 102 that outputs a voltage directly proportional to an input current can be used. Next, the output of the sense amplifier 102 is compared with m reference voltages VREF <b> 1 to VREFm by using m (m> 2) analog comparators 103, and is read out as an m-bit multi-value comparison result. Multi-valued data output from n memory cells 101 is a total of n × m bits. This value is sent to the buffer of the read circuit 200.

  As shown in FIG. 3, the read circuit 200 includes a buffer 201, a median value detection circuit 202, a threshold value determination circuit 203, a threshold value storage circuit 204, a data selection circuit 205, and a decoder 206. The buffer 201 buffers the resistance value (comparison result) read from the memory cell 101 of each bit and outputs it to the median value detection circuit 202 and the data selection circuit 205. The median value detection circuit 202 detects the median value of the distribution of resistance values based on the resistance values of the plurality of memory cells 101 acquired via the buffer 201.

  The threshold value determination circuit 203 determines a threshold value based on the median value of the detected resistance value distribution. The threshold value storage circuit 204 stores the determined threshold value. The data selection circuit 205 determines the resistance value of the memory cell 101 acquired through the buffer 201 using the threshold value determined and stored, and selects the ON / OFF state (memory state). The decoder 206 decodes the data based on the selected ON / OFF state.

<Configuration and Operation of Memory Cell of First Embodiment>
The configuration and operation of a resistance change type memory ReRAM will be described with reference to FIGS. 4 to 6 as an example of a nonvolatile memory constituting a memory cell array. Although ReRAM will be described here, other non-volatile memories such as flash memory, MRAM (magnetic resistance RAM), FeRAM (ferroelectric memory) may be used.

  FIG. 4 shows the configuration and operation of a ReRAM memory cell. The memory cell of the ReRAM changes to two states of low resistance (ON) or high resistance (OFF) by applying positive and negative voltages to both ends of the variable resistance element, and as this memory element is maintained by maintaining this state. work.

  As shown in FIG. 4, the memory cell 101 includes a resistance change element Rc and a cell transistor Tr. The resistance change element Rc is a two-terminal element, and one end is connected to a PL (plate line) terminal and the other end is connected to a BL (bit line) terminal via a cell transistor Tr. In FIG. 4, the gate voltage (word line WL voltage) of the cell transistor Tr is H, and the ON resistance of the cell transistor Tr is sufficiently smaller than the resistance value of the resistance change element Rc. The resistance value of the resistance change element Rc changes depending on the polarity of the voltage applied to the PL terminal and the BL terminal.

  For example, as shown in FIG. 4A, when the voltage Vw is applied to the PL terminal and the voltage 0V is applied to the BL terminal, the resistance value of the resistance change element Rc decreases, and the memory cell 101 enters the low resistance ON state. As shown in FIG. 4B, when a voltage of 0 V is applied to the PL terminal and a voltage Vw is applied to the BL terminal, the resistance value of the resistance change element Rc increases, and the memory cell 101 enters a high resistance OFF state. In order to read the resistance value from the memory cell 101, as shown in FIG. 4C, a voltage of 0V is applied to the BL terminal and a voltage of ΔVw smaller than the voltage Vw is applied to the PL terminal. This ΔVw is set to a small value such that the resistance value of the resistance change element Rc does not change. At this time, the state of ON or OFF can be read by measuring (sensing) the current flowing through the resistance change element Rc.

  FIG. 5 shows an example of a ReRAM memory cell array 100 incorporating the variable resistance element. In the memory cell array 100, word lines WL and plate lines PL are arranged in the horizontal direction, and bit lines BL are arranged in the vertical direction, and one memory cell is selected by a combination of these voltages. FIG. 5 shows the applied voltage when reading the resistance value from the memory cell. As shown in FIG. 5, the memory cell 101a surrounded by the dotted line is selected by applying a voltage of H, L, or L + ΔL to each wiring.

  Here, as shown in FIG. 6, the resistance value of the memory cell can be read by connecting the sense amplifier 102 to the plate line PL of the selected memory cell 101a. In FIG. 6, a constant voltage source 121 is provided at the input portion of the sense amplifier 102, and the voltage of the plate line PL becomes a constant voltage regardless of the resistance of the memory cell 101. At this time, a cell current Icell flows corresponding to the resistance value of the memory cell 101. This Icell passes through the constant voltage source 121 as it is, enters the current-voltage converter 122, and the current-voltage converter 122 outputs a voltage VAMP corresponding to the current value Icell. This voltage VAMP is input to the analog comparator 103.

<Operation of Read Circuit of First Embodiment>
FIG. 7 is an example of the correspondence between the distribution of the probability of occurrence of the resistance value stored in the memory cell 101 according to this embodiment and the reference voltage (reference voltage of the comparator). VREF1 to VREFm are reference voltages corresponding to resistance values. Hereinafter, VREFx <VREFy (x <y). In the binary storage memory cell 101, the resistance distribution is a distribution of a low resistance ON resistance (ON resistance value) and a distribution of a high resistance OFF resistance (OFF resistance value). There is a peak (center). In FIG. 7, a Gaussian distribution is assumed for both distributions, and regions that are higher than the threshold generation probability are set as an ON determination region and an OFF determination region, respectively. In the present embodiment, as described below, the threshold resistance R _TH is set in a region where the probability of occurrence between the ON determination region and the OFF determination region is low, so that the ON state and the OFF state of the memory cell 101 are changed. Can be identified with low error probability.

  The flowchart in FIG. 8 shows the operation of the read circuit 200 according to this embodiment. As shown in FIG. 8, first, the read circuit 200 reads data from the memory cell array 100 (S101). As described above, a voltage corresponding to the resistance value of the memory cell 101 is output from the sense amplifier 102, and n m-bit comparison results are input from the analog comparator 103 to the median value detection circuit 202 via the buffer 201.

  Subsequently, the read circuit 200 obtains resistance distributions of the low resistance and the high resistance from the read data (S102). The median value detection circuit 202 divides the comparison results input via the buffer 201 into those belonging to the ON determination region, those belonging to the OFF determination region, and those not belonging to either as shown in FIG. Then, the median value detection circuit 202 obtains the median value for each set belonging to the ON and OFF determination areas. Although the median value is obtained here, an average value (or other intermediate value) may be obtained instead. The median value obtained here can be regarded as indicating the resistance values of the respective peaks of the ON resistance distribution and the OFF resistance distribution in the distribution of FIG. Here, assuming a resistance distribution such as a Gaussian distribution, the shape of each distribution can be determined from the resistance value at the peak (center). For example, even if the distribution of the ON state and OFF state changes due to fluctuations in temperature, voltage, process, noise, etc., the distribution taking into account these fluctuation factors can be obtained by reading the actual memory cells and obtaining the distribution. I can do it.

Subsequently, the readout circuit 200 determines a threshold value from the obtained resistance distribution (S103). In FIG. 7, the resistance value R _TH at which the _tails of the ON state and OFF state distributions intersect can be minimized. Therefore, the threshold resistance that can minimize the error probability can be found by obtaining the resistance value at which the tails intersect from the median value or average value (or intermediate value) of the ON state and OFF state distributions. The threshold value determination circuit 203 determines the threshold resistance RTH from the median value or average value of the ON state and the OFF state. Determination of the threshold value can be easily realized, for example, by previously storing a correspondence between the median value or average value (or intermediate value) of the ON state and the OFF state and the resistance value of the threshold value as a table. Next, the threshold voltage Vrefc closest to the resistance is selected and used as the output of the threshold value determination circuit 203. Once the threshold value is determined, this value is stored in the threshold value storage circuit 204.

  Subsequently, the read circuit 200 reads data using the determined new threshold value (S104), and decodes the data (S105). The data selection circuit 205 selects and outputs 1-bit input value corresponding to the threshold voltage Vrefc from each of the n m-bit data acquired via the buffer 201 (whether or not the threshold is exceeded). judge). The output of the data selection circuit 205 is n bits. Then, the decoder 206 decodes the n-bit data according to the error correction method to restore the k-bit data.

<Effect of Embodiment 1>
In the above-mentioned Patent Document 1, there is a problem that although it can cope with the temperature change of the chip, it cannot cope with process variations and voltage variations. In Patent Document 2, a reference index cell different from the main is read, a read voltage level (threshold) is set according to the number of fail bits of the read data, and the main voltage is set according to the set voltage level. The data of the memory cell is read out. In Patent Document 2, there is a problem that the chip area is increased because a reference memory cell is required in addition to the main memory cell, and if there is a characteristic variation between the main memory cell and the reference memory cell, There is a problem that a simple threshold cannot be set.

  In the present embodiment, the threshold value for determining the ON / OFF state is determined from the data itself stored in the nonvolatile memory as described above. For this reason, the influence of fluctuation factors such as temperature, voltage, process and noise can be eliminated. Accordingly, even when the difference between the ON and OFF values, that is, when the read margin is small, the data can be read accurately, and the error rate can be reduced. In addition, since the threshold value is set by using a memory cell that actually stores data, a reference memory cell is not required, so that an increase in chip area can be suppressed and the influence of characteristic variation can be reduced. .

(Modification 1 of Embodiment 1)
FIG. 9 is an example of a distribution of resistance values of the memory cell 101 according to the first modification of the first embodiment. The resistance value stored in the variable resistance element can be multivalued as shown in FIG. 9 of Modification 1 instead of the binary value of ON and OFF as shown in FIG. 7 of the first embodiment.

FIG. 9 shows an example in which the memory cell 101 stores four-value states of 0, 1, 2, and 3. Also in this case, the output of the sense amplifier 102 is compared with m reference voltages VREF <b> 1 to VREFm using m (m> 2) analog comparators 103, and is read as an m-bit multi-value comparison result. The 0 determination area to 3 determination aggregates comparison result for each reference voltage belonging to the respective areas calculated median or mean value, from the result, the three thresholds resistor _{R TH01, R TH12, R TH23} decide.

(Modification 2 of Embodiment 1)
In the first embodiment, it is assumed that n-bit read data always includes at least one of the ON state and the OFF state. However, when the input data is composed of a plurality of binary data, this condition is not always satisfied. Therefore, in the second modification, a code uniquely determined for the input data is defined, and the code always includes at least one of 0 and 1 data.

  An example of a code that satisfies this condition is shown in FIG. FIG. 10 shows an example using a (7, 4 bit) Hamming code. In FIG. 10, 16 types of original data take values from 0000 to 1111 in 4 bits. Some of the original data is composed of only 0 or 1 only. A hamming code is obtained by adding 3 redundant bits to this code. Here, not normal redundant bits but data obtained by bit-reversing redundant bits are added. The generated code includes at least one of 0 and 1 data. Furthermore, since it is a Hamming code, it has a 1-bit error correction capability, so that reliability can be improved.

  In FIG. 10, 3 bits are added to 4 bits. However, in order to ensure that the code includes at least one data of 0 and 1, as shown in FIG. It is also possible to add 1 bit to (4-5 bit conversion). Here, with respect to the original 4 bits, odd parity is calculated with only 1 to 3 bits and added to the 5th bit. However, with this code, only parity check is possible, and it does not have error correction capability like a Hamming code.

  In the second modification, for example, an encoder (not shown) is provided in the writing circuit of the nonvolatile memory, and the encoder encodes the codes shown in FIGS. 10 and 11 and writes the encoded data into the memory cell array. Further, the decoder 206 of the reading circuit 200 decodes the codes in FIGS. 10 and 11 into the original data.

(Modification 3 of Embodiment 1)
FIG. 12 is a configuration example of the median value detection circuit according to the third modification of the first embodiment. The input of the median value detection circuit 202 is the output of the m analog comparators 103 for every n bits of the memory cell array 100, and the total is n × m bits. Here, the output of the qth (1 ≦ q ≦ m) analog comparator 103 of the r-th bit (1 ≦ r ≦ n) is CMPq, r. As shown in FIG. 12, the median value detection circuit 202 has an ON median value detection circuit 202a and an OFF median value detection circuit 202b for determining median values of the ON distribution and the OFF distribution.

  Referring to FIG. 12, the ON median value detection circuit 202a uses the outputs CMP1,1 to CMPi + 1, n of the 1st to (i + 1) th analog comparators 103, and the OFF median value detection circuit 202b is the j−1 to mth analog. The outputs CMPj−1,1 to CMPm, n of the comparator 103 are used. The median value detection circuits 202a and 202b output MEDON1 to MEDONi + 1 and MEDOFFj-1 to MEDOFFm as median values. MEDON1 to MEDONi + 1 correspond to CMP1, r to CMPi + 1, r, and only one bit serving as the median is H, and the others are L. MEDOFFj-1 to MEDOFFm correspond to CMPj-1, r to CMPm, r, where only one bit which is the median is H, and L otherwise.

  FIG. 13 is a detailed circuit diagram of the ON median value detection circuit 202a of FIG. As shown in FIG. 13, the ON median value detection circuit 202a includes i + 1 counters 221, i multipliers 222, i binary comparators 223, i NOT circuits 224, and i-1 AND circuits. 225. The counter 221 counts the output of the analog comparator 203 for each bit (memory cell 101). The n-bit values of CMP1, r to CMPi + 1, r (1 ≦ r ≦ n) are input to the 1st to i + 1th counters 221 respectively. Each counter 221 counts the number of input signals that are L and outputs them to CNT1 to CNTi + 1. Here, since the output value is one of 0 to n, the value of CNTi is, for example, an s-bit binary number (n <2s). Multiplier 222 doubles the output of counter 221 and binary comparator 223 compares the output of multiplier 222 with the total number of bits. That is, 2CNT1 to 2CNTi obtained by doubling the values of CNT1 to CNTi by the multiplier 222 are compared with CNTi + 1 by the binary comparator 223 of s + 1 bits to obtain the comparison results DCMP1 to DCMP1. Here, in order to double the value of CNTi, CNTi is shifted by 1 bit. For this reason, 2CNT1 to 2CNTi are binary numbers of s + 1 bits.

  The NOT circuit 224 and the AND circuit 225 output a median value based on the comparison result of the binary comparator 223. Since the value of CNTi + 1 is the total number of bits included in the ON distribution, and the values of CNT1 to CNTi are the number of bits having a voltage lower than the reference voltages VREF1 to VREFi, DCMPx is L and DCMPx + 1 (1 ≦ x ≦ i) X is the median. Therefore, the NOT circuit 224 generates the inverted value of DCMPx, and the AND circuit 225 outputs the inverted value of DCMPx and the AND of DCMPx + 1 as the median value MEDON. Here, although i + 1 bits of MEDON1 to MEDONi + 1 are obtained, only one bit is H. This circuit is composed only of a combinational circuit and can detect a median at high speed.

  The OFF median value detection circuit 202b can also be configured in a similar manner. The OFF median value detection circuit 202b can be configured by replacing CMP1 in FIG. 13 with CMPm, CMP2 with CMPm-1,..., And counting the number of input signals that are H in the counter 221. With such a configuration, the median can be detected easily and at high speed.

  Although the median value is detected in the circuit of FIG. 13, a circuit for detecting an average value as shown in FIG. 14 can also be used. The input / output signals in FIG. 14 are the same as those in FIG. By using the circuit of FIG. 14 for the circuit of FIG. 12 instead of FIG. 13, the circuit of FIG. 12 can be an average value detection circuit.

  As shown in FIG. 14, the ON median value detection circuit (here, the average value detection circuit) 202 a includes i + 1 counters 231, i adders 232, i + 1 multipliers 233, adders 234, and introduction 235. , I + 1 binary comparators 236, i NOT circuits 237, and i−1 AND circuits 228. In FIG. 14, n-bit values of CMP1, r to CMPi + 1, r (1 ≦ r ≦ n) are input to the counters 231 of No. 1 to i + 1, respectively. Each counter 231 counts the number of input signals that are L, obtains the difference between the respective count values by an adder 232, and outputs the difference to CNT1 to CNTi + 1. CNT1 to CNTi + 1 are the number of bits that fall within the respective threshold ranges. The next multiplier 233 multiplies the number of bits by resistance values RREF1 to RREFi + 1 at threshold values. Further, an adder 234 adds all the multiplication results to obtain an overall sum SUM.

  When this SUM is divided by a divider 235 by CNTall, which is the sum of CNT1 to CNTi + 1, an average RAVE of resistance values is obtained. When the RAVE is compared with the resistance values RREF1 to RREFi + 1 at the respective threshold values by the binary comparator 236, and the result is calculated by the NOT circuit 237 and the AND circuit 238 in the same manner as the median value in FIG. 13, MEDON1 to MEDONi + 1. I + 1 bit output is obtained. Among these, only one bit becomes H, and this is the minimum threshold resistance larger than the resistance value RAVE, that is, the threshold resistance near the average value. With such a configuration, the average value can be detected simply and at high speed.

(Embodiment 2)
The second embodiment will be described below with reference to the drawings. 15 and 16 show the timing of the data read operation according to the present embodiment. The configuration is the same as in the first embodiment.

  In FIG. 15 which is an example of the operation, it is assumed that one clock time is required for each of the four operations of cell reading, median value detection, threshold value determination, and data decoding. That is, the data read from the memory cell 101 is held in the buffer 201 at the first clock, the median value detection circuit 202 detects the median value at the second clock, and the threshold value determination circuit 203 is the threshold value at the third clock. The decoder 206 decodes the data at the fourth clock. Then, it takes 4 clocks to output data after the read circuit 200 receives the read command.

  However, since these four operations operate in parallel, the speed can be increased by the pipeline. As a continuous read operation, the start of the operation is shifted by one clock, and the second and third data read is performed. That is, as shown in FIG. 15, the first reading is started from the first clock, the second reading is started from the second clock, and the third reading is started from the third clock. As a result, the first data needs to wait for 4 clocks, but the second and subsequent data can be extracted every clock.

  In FIG. 16, which is another example of the operation, the first read requires 4 clocks as in FIG. 15. However, as described in Embodiment 1, the obtained threshold value is stored in the threshold value storage circuit 204. By storing, the threshold value used in the first reading is used in the second reading. For this reason, in the second read, data is output by two operations of cell read and data decode after the read circuit 200 receives a read command, so that it can be read in a time of two clocks.

  Similarly, the data can be read out with two clocks after the third time, so that the reading speed can be increased even when continuous data reading is not performed. In the second reading, after the data is output, the threshold value using the read data is recalculated, stored in the threshold value memory, and used for the subsequent reading. For example, in the second reading, the median value is detected and the threshold value is determined at the fifth and sixth clocks while cell read data decoding is performed at the fourth and fifth clocks.

(Embodiment 3)
The third embodiment will be described below with reference to the drawings. FIG. 17 shows a configuration example of the nonvolatile memory according to this embodiment.

  As shown in FIG. 17, the nonvolatile memory 1 according to the present embodiment includes a training circuit 300 in addition to the memory cell array 100 and the read circuit 200. In the first embodiment, since m analog comparators 103 are used for each bit, n × m analog comparators are required for the entire chip in FIG. In contrast, in the present embodiment, only one analog comparator 103 is provided for each bit. Instead, it has one training circuit 300 for n bits.

  Immediately after the power is turned on, the threshold value is determined by operating the training circuit 300 before starting the read operation, and the read operation is performed using this threshold value. As shown in FIG. 17, the training circuit 300 includes m analog comparators 103, a comparison value latch 207, a median value detection circuit 202, a threshold value determination circuit 203, a threshold value storage circuit 204, and switches SW1 and SW2. Prepare. In this embodiment, the memory cell array 100 includes a memory cell 101, a sense amplifier 102, and an analog comparator 103 for each bit, and the read circuit 200 includes a buffer 201 and a decoder 206.

  The operation of FIG. 17 will be described. In the training operation, the memory cell 101 is operated in the same manner as a normal read operation. At this time, one of the outputs VAMP1 to VAMPn of the n sense amplifiers 102 is connected to the training circuit 300 by the changeover switch SW1. Then, the output is compared with m reference voltages VREF1 to VREFm, and the comparison result of m bits is stored in the comparison value latch 207. By switching the changeover switch SW1, the comparison value latch 207 stores n bits of the comparison result n × m bits. Using this data, the threshold value is determined by the median value detection circuit 202 and the threshold value determination circuit 203 as in the first embodiment, and is stored in the threshold value storage circuit 204.

  In the read operation, one of the reference voltages VREF1 to VREFm is connected to VREFAll by the changeover switch SW2 according to the value of the threshold value storage circuit 204. In this state, data is read from the memory cell 101. Then, the analog comparator 103 in the memory cell array 100 compares the outputs VAMP1 to VAMPn of the n sense amplifiers 102 with VREFAll, whereby an n-bit comparison result is obtained. This data is transferred via the buffer 201, and decoded by the decoder 206 according to the error correction method to restore k-bit data.

  In this embodiment, since the number of analog comparators can be reduced as compared with the first embodiment, the chip area can be reduced. Further, by obtaining the threshold value in advance, it is possible to speed up data reading as in the second embodiment. Here, although the timing for performing the training operation is set immediately after the power is turned on, the training operation can be appropriately performed thereafter. For example, in Patent Document 2, normal reading cannot be performed during the training operation using the reference, but the training circuit and the memory cell can operate in parallel in FIG. It can be performed.

  In addition, a training operation can be performed at predetermined time intervals such as every second or every minute using a timer. Furthermore, a thermometer can be mounted on the chip, and the training operation can be performed when the chip temperature changes by a certain value such as 5 ° C. or 10 ° C. Thereby, an appropriate threshold value can be set.

A part or all of the above-described embodiment can be described as in the following supplementary notes, but is not limited thereto.
(Appendix 1)

A state is read from a plurality of memory cells stored in an H or L state, and an average value or a center value of each of the read states that are substantially close to the H state and substantially close to the L state is obtained, A non-volatile memory, wherein a threshold value for identifying a state of H and L is determined from an average value or a center value, and a state read from the memory cell is identified as H or L.
(Appendix 2)

The nonvolatile memory according to appendix 1, wherein input data is encoded into data to be written in a memory cell, and the code includes at least one of an H state and an L state.
(Appendix 3)

The non-volatile memory according to appendix 2, wherein a plurality of comparators having different threshold values are read in order to read the state, and the comparators are operated simultaneously to obtain a comparison result for the plurality of threshold values. Non-volatile memory.
(Appendix 4)

The nonvolatile memory according to claim 3, wherein the state read from the memory cell is a resistance value.
(Appendix 5)

The nonvolatile memory according to attachment 3, further comprising a memory for storing a threshold value for identifying the H and L states, and when the threshold value is stored, the operation for determining the threshold value is not performed. A non-volatile memory using a stored threshold value.
(Appendix 6)

The nonvolatile memory according to appendix 3, wherein the plurality of comparators having different threshold values are only one set regardless of the number of the plurality of memory cells from which the state is read, and the one set of comparators and the plurality of memories A switch for connecting any one of the cells is provided, and the switch is switched every time a read operation is performed, and a comparison operation is performed on all of the plurality of memory cells that read the state, and the H and L states are identified. A nonvolatile memory characterized by determining a threshold value.
(Appendix 7)

  The nonvolatile memory according to claim 6, wherein the operation for determining the threshold value is performed immediately after the power is turned on, at regular intervals, or by detecting a change in the external environment.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

DESCRIPTION OF SYMBOLS 1 Nonvolatile memory 10 Semiconductor device 11 Memory cell 12 1st intermediate value determination circuit 13 2nd intermediate value determination circuit 14 Threshold value determination circuit 15 Identification circuit 100 Memory cell array 101 Memory cell 102 Sense amplifier 103 Analog comparator 121 Constant voltage source 122 Current-voltage converter 200 Read circuit 201 Buffer 202 Median value detection circuit 202a ON median value detection circuit 202b OFF median value detection circuit 203 Threshold decision circuit 204 Threshold storage circuit 205 Data selection circuit 206 Decoder 207 Comparison value latch 221 Counter 222 Multiplier 223 Binary comparator 224 NOT circuit 225 AND circuit 231 Counter 232 Adder 233 Multiplier 234 Adder 235 Divider 236 Binary comparator 237 NOT circuit 238 AND circuit 300 Training circuit

Claims (14)

A plurality of memory cells including a memory cell that outputs first data according to a first storage state and a memory cell that outputs second data according to a second storage state;
A first intermediate value determining circuit for determining an intermediate value of the plurality of first data;
A second intermediate value determining circuit for determining an intermediate value of the plurality of second data;
A threshold value determination circuit for determining a threshold value for identifying the first and second storage states based on respective determination results of the first and second intermediate value determination circuits;
An identification circuit for identifying a storage state of the plurality of memory cells based on a determination result of the threshold determination circuit and a read result from the plurality of memory cells;
A semiconductor device comprising: The intermediate value is a central value of the distribution of the plurality of first or second data.
The semiconductor device according to claim 1. The threshold value is a value of a portion where the tail of the distribution of the first data and the tail of the distribution of the second data overlap.
The semiconductor device according to claim 2. The intermediate value is an average value of the plurality of first or second data.
The semiconductor device according to claim 1. In the plurality of memory cells, data encoded so as to include the memory cells in the first storage state and the memory cells in the second storage state is written.
The semiconductor device according to claim 1. The encoded data includes redundant bits corresponding to the first storage state and the second storage state and performing error detection or error correction.
The semiconductor device according to claim 5. Each of the memory cells includes a plurality of analog comparators that compare a signal read from the memory cell with a plurality of reference voltages and output the first or second data.
The semiconductor device according to claim 1. The first or second intermediate value determination circuit includes:
A plurality of counters for counting outputs of a plurality of analog comparators for each of the memory cells;
A multiplier for doubling the counted value;
A binary comparator that compares the doubled value with the total number of the first or second data;
An output circuit that outputs the intermediate value based on a comparison result of the binary comparator;
The semiconductor device according to claim 7, comprising: A plurality of analog comparators for comparing a signal read from the memory cell with a plurality of reference voltages and outputting the first or second data;
A changeover switch for switching connection between the plurality of memory cells and the plurality of analog comparators;
A latch circuit for latching outputs of the plurality of analog comparators;
The semiconductor device according to claim 1, comprising: A threshold value storage circuit for storing the determined threshold value;
The identification circuit identifies the storage state based on the stored threshold;
The semiconductor device according to claim 1. The identification circuit identifies the storage state based on a threshold value stored in a previous read operation;
The semiconductor device according to claim 10. The threshold value determination circuit determines the threshold value when the power is turned on, at regular intervals, or when the external environment changes;
The semiconductor device according to claim 1. A plurality of nonvolatile memory cells including a nonvolatile memory cell that outputs first data according to a first storage state and a nonvolatile memory cell that outputs second data according to a second storage state;
A first intermediate value determining circuit for determining an intermediate value of the plurality of first data;
A second intermediate value determining circuit for determining an intermediate value of the plurality of second data;
A threshold value determination circuit for determining a threshold value for identifying the first and second storage states based on respective determination results of the first and second intermediate value determination circuits;
An identification circuit for identifying a storage state of the plurality of nonvolatile memory cells based on a determination result of the threshold value determination circuit and a read result from the plurality of nonvolatile memory cells;
A non-volatile memory. The nonvolatile memory cell is a resistance change type memory cell,
The first and second data are resistance values.
The non-volatile memory according to claim 13.

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