SG11201607150TA - Testing apparatuses, hierarchical priority encoders, methods for controlling a testing apparatus, and methods for controlling a hierarchical priority encoder - Google Patents
Testing apparatuses, hierarchical priority encoders, methods for controlling a testing apparatus, and methods for controlling a hierarchical priority encoderInfo
- Publication number
- SG11201607150TA SG11201607150TA SG11201607150TA SG11201607150TA SG11201607150TA SG 11201607150T A SG11201607150T A SG 11201607150TA SG 11201607150T A SG11201607150T A SG 11201607150TA SG 11201607150T A SG11201607150T A SG 11201607150TA SG 11201607150T A SG11201607150T A SG 11201607150TA
- Authority
- SG
- Singapore
- Prior art keywords
- controlling
- methods
- hierarchical priority
- testing
- encoders
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
- G06F16/20—Information retrieval; Database structures therefor; File system structures therefor of structured data, e.g. relational data
- G06F16/24—Querying
- G06F16/245—Query processing
- G06F16/24569—Query processing with adaptation to specific hardware, e.g. adapted for using GPUs or SSDs
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
- G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
- G11C15/046—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements using non-volatile storage elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Human Computer Interaction (AREA)
- Computational Linguistics (AREA)
- Data Mining & Analysis (AREA)
- Databases & Information Systems (AREA)
- Read Only Memory (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SG11201607150TA SG11201607150TA (en) | 2014-02-28 | 2015-03-02 | Testing apparatuses, hierarchical priority encoders, methods for controlling a testing apparatus, and methods for controlling a hierarchical priority encoder |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SG10201400292T | 2014-02-28 | ||
SG10201400303Y | 2014-02-28 | ||
PCT/SG2015/000065 WO2015130234A1 (en) | 2014-02-28 | 2015-03-02 | Testing apparatuses, hierarchical priority encoders, methods for controlling a testing apparatus, and methods for controlling a hierarchical priority encoder |
SG11201607150TA SG11201607150TA (en) | 2014-02-28 | 2015-03-02 | Testing apparatuses, hierarchical priority encoders, methods for controlling a testing apparatus, and methods for controlling a hierarchical priority encoder |
Publications (1)
Publication Number | Publication Date |
---|---|
SG11201607150TA true SG11201607150TA (en) | 2016-09-29 |
Family
ID=54009429
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG11201607150TA SG11201607150TA (en) | 2014-02-28 | 2015-03-02 | Testing apparatuses, hierarchical priority encoders, methods for controlling a testing apparatus, and methods for controlling a hierarchical priority encoder |
Country Status (3)
Country | Link |
---|---|
US (1) | US20170169075A1 (en) |
SG (1) | SG11201607150TA (en) |
WO (1) | WO2015130234A1 (en) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9875799B1 (en) | 2015-01-12 | 2018-01-23 | Micron Technology, Inc. | Methods for pattern matching using multiple cell pairs |
KR20190002708A (en) * | 2016-05-17 | 2019-01-08 | 실리콘 스토리지 테크놀로지 인크 | An array of three-gate flash memory cells with separate memory cell read, program, and erase |
US10269440B2 (en) * | 2016-05-17 | 2019-04-23 | Silicon Storage Technology, Inc. | Flash memory array with individual memory cell read, program and erase |
US10032508B1 (en) * | 2016-12-30 | 2018-07-24 | Intel Corporation | Method and apparatus for multi-level setback read for three dimensional crosspoint memory |
CN108806751B (en) * | 2017-04-26 | 2021-04-09 | 中芯国际集成电路制造(上海)有限公司 | Multi-time programmable flash memory cell array, operation method thereof and memory device |
KR102414183B1 (en) * | 2017-09-15 | 2022-06-29 | 삼성전자주식회사 | Resistive memory device including reference cell and method for controlling reference cell |
CN110147200A (en) * | 2018-02-13 | 2019-08-20 | 矽创电子股份有限公司 | The controller and control method of flash memory |
US11553618B2 (en) | 2020-08-26 | 2023-01-10 | PassiveLogic, Inc. | Methods and systems of building automation state load and user preference via network systems activity |
US20220284009A1 (en) * | 2021-03-03 | 2022-09-08 | The Toronto-Dominion Bank | System and Method for Processing Hierarchical Data |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7069378B2 (en) * | 2002-07-22 | 2006-06-27 | Integrated Device Technology, Inc. | Multi-bank content addressable memory (CAM) devices having staged segment-to-segment soft and hard priority resolution circuits therein and methods of operating same |
US20080007995A1 (en) * | 2006-07-10 | 2008-01-10 | Schwerin Ulrike Gruening-Von | Memory cell having a switching active material, and corresponding memory device |
US7783654B1 (en) * | 2006-09-19 | 2010-08-24 | Netlogic Microsystems, Inc. | Multiple string searching using content addressable memory |
CN102498475A (en) * | 2009-07-10 | 2012-06-13 | 柰米闪芯积体电路有限公司 | Novel high speed high density NAND-based 2t-NOR flash memory design |
US9245653B2 (en) * | 2010-03-15 | 2016-01-26 | Intelligent Intellectual Property Holdings 2 Llc | Reduced level cell mode for non-volatile memory |
EP2901329A4 (en) * | 2012-08-02 | 2016-07-13 | Agency Science Tech & Res | Testing apparatuses, servers and methods for controlling a testing apparatus |
-
2015
- 2015-03-02 SG SG11201607150TA patent/SG11201607150TA/en unknown
- 2015-03-02 US US15/121,991 patent/US20170169075A1/en not_active Abandoned
- 2015-03-02 WO PCT/SG2015/000065 patent/WO2015130234A1/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
WO2015130234A1 (en) | 2015-09-03 |
US20170169075A1 (en) | 2017-06-15 |
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