KR102414183B1 - Resistive memory device including reference cell and method for controlling reference cell - Google Patents

Abstract

According to an exemplary embodiment of the present disclosure, a method for controlling a reference cell included in a resistive memory to determine values stored in a plurality of memory cells includes: writing a first value into the plurality of memory cells; monotonically increasing the reference cell The method may include providing reference currents that increase or decrease monotonically, reading a plurality of memory cells from each of the reference currents, and determining a read reference current based on the read values.

Description

A resistive memory device including a reference cell and a control method of the reference cell

The technical idea of the present disclosure relates to a resistive memory device, and more particularly, to a resistive memory device including a reference cell and a control method of the reference cell.

The resistive memory device may store data in a memory cell including a variable resistance element. In order to detect data stored in the memory cell of the resistive memory device, for example, a read current may be supplied to the memory cell, and the read current and a voltage by the variable resistance element of the memory cell may be detected.

In memory cells in which a specific value is stored, the resistance value of the variable resistance value device may have a dispersion, and the dispersion may vary due to a process voltage temperature (PVT) or the like. In order to accurately read a value stored in a memory cell, it may be important to accurately and quickly set a threshold resistance value capable of distinguishing distributions of resistance values respectively corresponding to different values.

The technical idea of the present disclosure relates to a resistive memory device, and to a resistive memory device capable of accurately reading a value stored in a memory cell by controlling the reference cell and a method for controlling the reference cell.

In order to achieve the above object, according to an aspect of the technical concept of the present disclosure, there is provided a method of controlling a reference cell included in a resistive memory to determine values stored in a plurality of memory cells, a first writing a value, providing monotonically increasing or monotonically decreasing reference currents to the reference cell, reading a plurality of memory cells from each of the reference currents, and determining a read reference current based on the read values may include steps.

In addition, according to an aspect of the inventive concept, a method of controlling a reference cell included in a resistive memory to determine values stored in a plurality of memory cells includes: writing a first value into the plurality of memory cells; Setting resistance values that monotonically increase or decrease monotonically of a reference resistance connected to the cell and through which a reference current passes, reading a plurality of memory cells from each of the resistance values of the reference resistance, and a read reference based on the read values It may include determining a resistance value.

Also, according to an aspect of the inventive concept, a resistive memory device receiving a reference control signal includes a cell array including a memory cell and a reference cell, each connected to different source lines and respectively connected to different bit lines , in response to a read command, a current source circuit configured to provide a read current and a variable reference current to the memory cell and the reference cell, respectively, through the source lines, respectively, an amplification configured to sense a voltage between the source lines respectively coupled to the memory cell and the reference cell circuit, and a control circuit configured to control the current source circuit such that the reference current is adjusted independently of the read current according to the reference control signal.

According to an exemplary embodiment of the present disclosure, a value stored in a memory cell included in a resistive memory device may be accurately read independently of a PVT or the like by deriving an accurate threshold resistance through control of a reference cell.

In addition, according to an exemplary embodiment of the present disclosure, by quickly detecting an accurate threshold resistance, it is possible to provide not only improved productivity of the resistive memory device but also adaptive calibration according to an operating environment of the resistive memory device.

Effects obtainable in exemplary embodiments of the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned are exemplary of the present disclosure from the description of exemplary embodiments of the present disclosure below. Embodiments can be clearly derived and understood by those of ordinary skill in the art. That is, unintended effects of carrying out the exemplary embodiments of the present disclosure may also be derived by those of ordinary skill in the art from the exemplary embodiments of the present disclosure.

1 is a block diagram illustrating a memory device and a controller according to an exemplary embodiment of the present disclosure.
FIG. 2 is a timing diagram illustrating an example of an operation in which the memory device and the controller of FIG. 1 communicate according to an exemplary embodiment of the present disclosure.
3 is a diagram illustrating an example of the memory cell of FIG. 1 according to an exemplary embodiment of the present disclosure;
4 is a graph illustrating a distribution of resistance values provided by the memory cell of FIG. 3 according to an exemplary embodiment of the present disclosure.
5A and 5B are block diagrams illustrating examples of the memory device of FIG. 1 according to example embodiments of the present disclosure.
6 is a circuit diagram illustrating an example of the current source circuit of FIG. 1 according to an exemplary embodiment of the present disclosure.
7A and 7B are circuit diagrams illustrating examples of the reference resistor circuit of FIG. 1 according to exemplary embodiments of the present disclosure.
8 is a flowchart illustrating a method of controlling a reference cell according to an exemplary embodiment of the present disclosure.
9A and 9B are flowcharts illustrating examples of steps S200 to S600 of FIG. 8 according to exemplary embodiments of the present disclosure.
Fig. 10 is a flowchart illustrating an example of step S800 of Fig. 8 according to an exemplary embodiment of the present disclosure.
11 is a graph illustrating an example of an operation in which a threshold resistance value is determined by step S800a of FIG. 10 according to an exemplary embodiment of the present disclosure.
12 is a flowchart illustrating an example of step S800 of FIG. 8 according to an exemplary embodiment of the present disclosure.
13 is a graph illustrating an example of an operation in which a threshold resistance value is determined by step S800b of FIG. 12 according to an exemplary embodiment of the present disclosure.
14 is a block diagram of a memory device according to an exemplary embodiment of the present disclosure.
15 is a block diagram illustrating a system-on-chip including a memory device according to an exemplary embodiment of the present disclosure.

1 is a block diagram illustrating a memory device 100 and a controller 200 according to an exemplary embodiment of the present disclosure, and FIG. 2 is a memory device 100 and a controller 200 of FIG. 1 according to an exemplary embodiment of the present disclosure. It is a timing diagram illustrating an example of an operation in which 200 communicates.

Referring to FIG. 1 , the memory device 100 may communicate with the controller 200 . The memory device 100 may receive a command CMD and an address ADDR such as a write command and a read command from the controller 200 , and data DATA from the controller 200 . (ie, write data) may be received or data DATA (ie, read data) may be transmitted to the controller 200 . Also, as shown in FIG. 1 , the memory device 100 may receive the reference adjustment signal ADJ from the controller 200 . Although each of the command CMD, address ADDR, data DATA, and reference control signal ADJ is illustrated separately in FIG. 1 , in some embodiments the command CMD, address ADDR, and data DATA ) and at least two or more of the reference control signal ADJ may be transmitted through the same channel. 1 , the memory device 100 includes a cell array 110 , a current source circuit 120 , a reference resistor circuit 130 , an amplifier circuit 140 , a control circuit 150 , and a non-volatile memory 160 . ) may be included.

The cell array 110 may include a plurality of memory cells. The memory cell M may include a variable resistance element (eg, the MTJ of FIG. 3 ), and the variable resistance element may have a resistance value corresponding to a value stored in the memory cell M . Accordingly, the memory device 100 may be referred to as a resistive memory device or a resistive random access memory (RRAM) (or ReRAM) device. For example, the memory device 100 may include, as a non-limiting example, the cell array 110 having a structure such as phase change random access memory (PRAM), ferroelectric random access memory (FRAM), and the like, and STT-MRAM ( The cell array 110 may include a magnetic random access memory (MRAM) structure such as Spin-Transfer Torque Magnetic Random Access Memory (Spin-Transfer Torque Magnetic Random Access Memory), Spin-RAM (Spin Torque Transfer Magnetization Switching RAM), and SMT-RAM (Spin Momentum Transfer). have. As will be described later with reference to FIG. 3 , exemplary embodiments of the present disclosure will be mainly described with reference to MRAM, but it is noted that exemplary embodiments of the present disclosure are not limited thereto.

The cell array 110 may include a reference cell R used to determine a value stored in the memory cell M. For example, as shown in FIG. 1 , the cell array 110 may include a plurality of memory cells M and a reference cell R commonly connected to the word line WLi, and thus the word line WLi. The plurality of memory cells M and the reference cell R commonly connected to WLi may be simultaneously selected by the activated word line WLi. Although only one reference cell R is illustrated in FIG. 1 , in some embodiments, the cell array 110 may include two or more reference cells connected to the word line WLi.

The current source circuit 120 may provide the read current I_RD and the reference current I_REF to the cell array 110 . For example, the current source circuit 120 may provide the read current I_RD to the memory cell M and may provide the reference current I_REF to the reference cell R. Also, the current source circuit 120 may adjust the reference current I_REF according to the current control signal CC received from the control circuit 150 . An example of the current source circuit 120 will be described later with reference to FIG. 6 .

The reference resistor circuit 130 may provide a resistance through which the reference current I_REF passes. For example, the reference resistor circuit 130 may provide a resistor having a reference resistance value R_REF between the first node N1 and the second node N2 . Also, the reference resistance circuit 130 may adjust the reference resistance value R_REF according to the resistance control signal RC received from the control circuit 150 . The resistance of the reference resistor circuit 130 may have different characteristics than the resistance formed inside the cell array 110 , and in some embodiments, better characteristics than the resistance formed inside the cell array 110 , for example, in response to PVT fluctuations. It may have a more insensitive characteristic. Examples of the reference resistor circuit 130 will be described later with reference to FIGS. 7A and 7B .

The amplification circuit 140 may receive the read voltage V_RD and the reference voltage V_REF, and may determine a value stored in the memory cell M based on the read voltage V_RD and the reference voltage V_REF. . For example, the amplifier circuit 140 may output a signal corresponding to a value stored in the memory cell M by comparing the read voltage V_RD and the reference voltage V_REF. The read voltage V_RD may include a voltage drop generated when the read current I_RD provided by the current source circuit 120 passes through the variable resistance element included in the memory cell M. In addition, the read voltage V_RD is not only a voltage drop by the memory cell M, but also a parasitic resistance in a path through which the read current I_RD passes (eg, the column decoder 170a of FIG. 5A , the source line SLj). , a voltage drop generated by the bit line BLj) may be further included.

Similar to the read voltage V_RD, the reference voltage V_REF has a parasitic resistance ( For example, it may include a voltage drop generated by the column decoder 170a of FIG. 5A , the shorted source line SSL, and the shorted bit line SBL). In addition, the reference voltage V_REF may further include a voltage drop caused by the reference resistance value R_REF provided by the reference resistance circuit 130 . Accordingly, the reference voltage V_REF can be adjusted by controlling the reference current I_REF and the reference resistance value R_REF of the reference resistor circuit 130, and the reference for determining the value stored in the memory cell M is adjusted. can

As will be described later with reference to FIG. 5A and the like, in some embodiments, the reference cell R may be a shorted cell that does not include a resistance element such as a variable resistance value element. Accordingly, the reference voltage V_REF may be insensitive to PVT fluctuations due to the characteristics of the reference resistor circuit 130 , and as will be described later with reference to FIG. 8 , when the reference voltage V_REF is accurately determined, the memory Operation reliability of the device 100 may be improved.

The control circuit 150 may control the current source circuit 120 and the reference resistance circuit 130 respectively through the current control signal CC and the resistance control signal RC, and may access the non-volatile memory 160 . have. In some embodiments, the control circuit 150 may generate the current control signal CC and the resistance control signal RC according to the reference adjustment signal ADJ received from the controller 200 . For example, the control circuit 150 may increase or decrease the reference current I_REF according to the reference control signal ADJ, and increase or decrease the reference resistance R_REF of the reference resistance circuit 130 . can As a result, the reference voltage V_REF may be adjusted according to the reference adjustment signal ADJ provided from the controller 200 .

In some embodiments, in order to adjust the reference voltage V_REF, one of the reference current I_REF and the resistance value of the reference resistor circuit 130 may be fixed. For example, when the reference current I_REF is fixed, the control circuit 150 may not generate the current control signal CC, and may be referenced through the resistance control signal RC according to the reference control signal ADJ. The resistance value of the resistor circuit 130 may be adjusted. On the other hand, when the resistance value of the reference resistance circuit 130 is fixed, the control circuit 150 may not generate the resistance control signal RC, and the current control signal CC according to the reference control signal ADJ The reference current (I_REF) can be adjusted through

The nonvolatile memory 160 may store information about the reference voltage V_REF. For example, the nonvolatile memory 160 includes information on a reference current used for a read operation of the memory cell M, that is, a read reference current, and a reference resistance used for a read operation of the memory cell M, that is, a read reference. Information about resistance can be stored. In some embodiments, the control circuit 150 non-volatile information about the reference voltage V_REF in response to a command CMD (or a setting command) instructing to set the reference voltage V_REF from the controller 200 . A current control signal CC and a resistance control signal (CC) and a resistance control signal (CC) according to information stored in the nonvolatile memory 160 in response to a command CMD (or a read command) that can be written to the memory 160 and instructs to read data RC) can be created. In some embodiments, the non-volatile memory 160 may be omitted. For example, at least some of the memory cells included in the cell array 110 may store information about the reference voltage V_REF and may be accessed by the control circuit 150 .

The controller 200 may include a reference trimmer 210 . The reference trimmer 210 may adjust the reference voltage V_REF of the memory device 100 through the reference adjustment signal ADJ, and based on the value read from the memory cell M according to the adjusted reference voltage V_REF. Thus, the reference voltage V_REF to be used when reading the memory cell M, that is, the read reference voltage may be determined.

In some embodiments, the reference adjustment signal ADJ may be provided to the memory device 100 in synchronization with the read command, that is, simultaneously with the read command or subsequent to or prior to the read command. For example, as shown in FIG. 2 , the controller 200 controls the read command READ and the first address A1 at time t1 through the command CMD, the address ADDR, and the reference control signal ADJ. ) and the first option OP1 may be provided to the memory device 100 . The control circuit 150 of the memory device 100 may generate the current control signal CC and the resistance control signal RC according to the first option OP1 , and accordingly, the reference current I_REF and the reference resistance circuit A resistance value of 130 may be determined. In addition, the memory cell M and the reference cell R corresponding to the first address A1 may be selected according to the read command READ, and the read voltage V_RD and the reference according to the memory cell M may be selected. The value stored in the memory cell M may be determined by the current I_REF and the reference voltage V_REF according to the reference resistance R_REF of the reference resistor circuit 130 . The determined value may be provided to the controller 200 as the first output OUT1 through the data DATA. Similarly, at time t2, in response to the read command READ of the controller 200, the second address A2, and the second option OP2, the memory device 100 transmits the second output OUT2 to the controller 200) can be provided. In some embodiments, different from that illustrated in FIG. 2 , the reference adjustment signal ADJ may be provided to the memory device 100 in synchronization with a dedicated command different from the read command READ.

In some embodiments, the reference trimmer 210 may read a plurality of memory cells having predefined values written therein according to reference voltages that monotonically increase or decrease monotonically, and based on the read results, the read reference voltage is read. can be decided By controlling the reference cell R in this way, as will be described later, an accurate threshold resistance of the memory cell M may be derived, and a value stored in the memory cell M may be accurately read. In addition, an accurate threshold resistance may be detected quickly, and accordingly, improved productivity of the resistive memory device 100 may be provided, and an adaptive correction may be provided according to an operating environment of the resistive memory device 100 .

3 is a diagram illustrating an example of the memory cell M of FIG. 1 according to an exemplary embodiment of the present disclosure, and FIG. 4 is a diagram provided by the memory cell M of FIG. 3 according to an exemplary embodiment of the present disclosure. It is a graph showing the dispersion of resistance values. Specifically, FIG. 3 shows a memory cell M' including a magnetic tunnel junction (MTJ) element as a variable resistance element, and FIG. 4 illustrates a distribution of resistance values of the variable resistance element MTJ of FIG. 3 .

As shown in FIG. 3 , the memory cell M′ may include a variable resistance element MTJ and a cell transistor CT connected in series between a bit line BLj and a source line SLj. In some embodiments, as shown in FIG. 3 , the variable resistance element MTJ and the cell transistor CT may be connected in order between the bit line BLj and the source line SLj, and in some embodiments, as shown in FIG. 3 , the cell transistor CT and the variable resistance element MTJ may be sequentially connected between the bit line BLj and the source line SLj.

The variable resistance element MTJ may include a free layer FL and a pinned layer PL, and a barrier layer is formed between the free layer FL and the pinned layer PL. BL) may be included. As indicated by arrows in FIG. 3 , the magnetization direction of the pinned layer PL may be fixed, while the free layer FL may have the same or opposite magnetization direction to the magnetization direction of the pinned layer PL. When the pinned layer PL and the free layer FL have magnetization directions in the same direction, the variable resistance element MTJ may be referred to as being in a parallel state P, while the pinned layer PL and the free layer are in a parallel state P. When FL has magnetization directions opposite to each other, the variable resistance element MTJ may be referred to as being in an anti-parallel state AP. In some embodiments, the variable resistance element MTJ may further include an anti-ferromagnetic layer such that the pinned layer PL has a fixed magnetization direction.

The variable resistance element MTJ may have a relatively low resistance value R _P in the parallel state P, and may have a relatively high resistance value R _AP in the antiparallel state AP. In the present specification, when the variable resistance element MTJ has a low resistance value R _P , the memory cell M' stores '0', and when the variable resistance value element MTJ has a high resistance value R _AP . It is assumed that the memory cell M' stores '1'. Also, in this specification, the resistance value R _P corresponding to '0' may be referred to as a parallel resistance value ( _RP ), and the resistance value (R _AP ) corresponding to '1' is an antiparallel resistance value (R _AP ). may be referred to.

Referring to FIG. 4 , the resistance values of the variable resistance element MTJ may have a distribution. For example, as shown in FIG. 4 , a distribution (or first distribution) of the parallel resistance value R _P may exist in memory cells storing '0', and in memory cells storing '1' A dispersion (or a second dispersion) of the antiparallel resistance values R _AP may exist. In some embodiments, as illustrated in FIG. 4 , the antiparallel resistance value R _AP may have a deteriorated dispersion than the parallel resistance value R _P , ie, a dispersion having a higher dispersion. In addition, as indicated by a dotted line in FIG. 4 , the resistance value distribution of the variable resistance value element MTJ may be deteriorated due to various causes. Accordingly, the range of the threshold resistance R _TH for distinguishing the distribution of the parallel resistance value R _P and the distribution of the antiparallel resistance value R _AP can be reduced, and it is difficult to determine the correct threshold resistance value R _TH . can be important As will be described later with reference to FIGS. 8 to 13 , according to exemplary embodiments of the present disclosure, by controlling the reference cell R, the distribution of the resistance value of the variable resistance element MTJ can be estimated, and the estimated The threshold resistance R _TH may be determined based on the dispersion.

Referring back to FIG. 3 , the cell transistor CT may include a gate connected to the word line WLi, a source line SLj, and a source and drain connected to the variable resistance element MTJ. The cell transistor CT may electrically connect or block the variable resistance value element MTJ and the source line SLj according to a signal applied to the word line WLi. For example, in order to write '0' to the memory cell M' in the write operation, the cell transistor CT may be turned on, and a current flowing from the bit line BLj to the source line SLj may It may pass through the variable resistance element MTJ and the cell transistor CT. In addition, in order to write a '1' to the memory cell M', the cell transistor CT may be turned on, and a current flowing from the source line SLj to the bit line BLj is transferred to the cell transistor CT and It may pass through the variable resistance element MTJ. In the read operation, the cell transistor CT may be turned on, and a current from the bit line BLj to the source line SLj or a current from the source line SLj to the bit line BLj, that is, read The current I_RD may pass through the cell transistor CT and the variable resistance element MTJ. In this specification, it is assumed that the read current I_RD flows from the source line SLj to the bit line BLj.

5A and 5B are block diagrams illustrating examples of the memory device 100 of FIG. 1 according to example embodiments of the present disclosure. Specifically, FIGS. 5A and 5B illustrate the memory devices 100a and 100b in a read operation, and the reference resistor circuits 130a and 130b in the memory devices 100a and 100b may be arranged differently. Hereinafter, FIGS. 5A and 5B will be described with reference to FIG. 1 , and overlapping descriptions of FIGS. 5A and 5B will be omitted.

Referring to FIG. 5A , the memory device 100a may include a cell array 110a, a current source circuit 120a, a reference resistor circuit 130a, an amplifier circuit 140a, and a column decoder 170a. The cell array 110a may include a memory cell M and a reference cell R commonly connected to the word line WLi. The memory cell M may be connected to the bit line BLj and the source line SLj, respectively, and the reference cell R may be connected to the short bit line SBL and the short source line SSL, respectively. The bit line BLj, the source line SLj, the short bit line SBL, and the short source line SSL may extend to the column decoder 170a.

The memory cell M may include a variable resistance value element MTJ and a cell transistor CT connected in series between the bit line BLj and the source line SLj, while the reference cell R is a short-circuited bit line ( SBL) and a cell transistor CT connected to the short-circuit source line SSL. Accordingly, the short-circuited bit line SBL and the short-circuited source line SSL may be electrically shorted or opened by the cell transistor CT of the reference cell R, and as such, the reference cell R without the resistance element may be referred to as a shorted cell. In order to compensate for a voltage drop caused by the bit line BLj and the source line SLj connected to the memory cell M, the reference connected to the short-circuited bit line SBL and the short-circuited source line SSL as shown in FIG. 5A . The cell R may be disposed in the cell array 110a. As shown in FIG. 5A , the reference cell R may be a short-circuited cell, and accordingly, the voltage drop by the variable resistance value element MTJ of the memory cell M is a reference disposed outside the cell array 110a. It can be compared with the voltage drop caused by the resistive element 130a. As the cell array 110 is freed from the spatial and structural constraints, the reference resistance element 130a disposed outside the cell array 110a may provide a reference resistance value R_REF with a wide variable range and insensitive to PVT and the like. , the reference voltage V_REF may be accurately adjusted accordingly.

The column decoder 170a may route the bit line BLj, the source line SLj, the short bit line SBL, and the short source line SSL according to the column address COL. The column address COL may be generated from the address ADDR received from the controller 200 of FIG. 1 , and the column decoder 170a includes a memory selected according to the word line WLi activated in the cell array 110a. At least some of the cells and the reference cells may be selected according to the column address COL. For example, as shown in FIG. 5A , the column decoder 170a may connect the bit line BLj of the memory cell M to the negative supply voltage VSS, and connect the source line SLj to the current source circuit. (120)a) can be connected. Also, the column decoder 170a may connect the short-circuit bit line SBL of the reference cell R to the reference resistor circuit 130a and the short-circuit source line SSL to the current source circuit 120a. Accordingly, the read current I_RD may flow to the negative supply voltage VSS through the source line SLj, the memory cell M, and the bit line BLj, and the reference current I_REF may be the short-circuit source line (SSL), the reference cell (R), the short-circuit bit line (SBL), and may flow through the reference resistor circuit 130a as a negative supply voltage (VSS).

The amplification circuit 140a may be respectively connected to nodes from which the read current I_RD and the reference current I_REF are output from the current supply circuit 120a, and the voltages of the nodes, that is, the read voltage V_RD and the reference voltage V_REF ), the output signal Q may be generated. The read voltage V_RD may be determined by the resistance value and the read current I_RD of the variable resistance value element MTJ of the memory cell M, while the reference voltage V_REF is the reference resistance value R_REF and the reference current I_REF. can be determined by The amplification circuit 140a, when the read voltage V_RD is higher than the reference voltage V_REF (that is, when the resistance of the variable resistance element MTJ of the memory cell M is greater than the threshold resistance R _TH ), While the output signal Q corresponding to '1' can be generated, when the read voltage V_RD is lower than the reference voltage V_REF (that is, the resistance value of the variable resistance element MTJ of the memory cell M) If it is less than the threshold resistance (R _TH )), an output signal Q corresponding to '0' may be generated.

Referring to FIG. 5B , the memory device 100b may include a cell array 110b , a current source circuit 120b , a reference resistor circuit 130b , an amplifier circuit 140b , and a column decoder 170b . Compared to the memory device 100a of FIG. 5A , the memory device 100b of FIG. 5B may include a reference resistor circuit 130b disposed between the column decoder 170b and the current source circuit 120b. Accordingly, the reference current I_REF may flow as a negative supply voltage VSS through the reference resistor circuit 130b, the short-circuit source line SSL, the reference cell R, and the short-circuit bit line SBL. Hereinafter, exemplary embodiments of the present disclosure will mainly focus on an example in which the reference resistor circuit 130a is disposed between the reference cell R and the negative supply voltage VSS, such as the memory device 100a of FIG. 5A . Although it will be described with reference, it is noted that exemplary embodiments of the present disclosure are not limited thereto.

6 is a circuit diagram illustrating an example of the current source circuit 120 of FIG. 1 according to an exemplary embodiment of the present disclosure. As described above with reference to FIG. 1 , the current source circuit 120 ′ of FIG. 6 may generate a read current I_RD and a reference current I_REF, and when n is a positive integer, the control circuit 150 ′ The reference current I_REF can be adjusted according to the current control signal CC[1:n].

Referring to FIG. 6 , the current source circuit 120 ′ may include a plurality of transistors P0, P1, P2, ..., Pn, Pr having sources commonly connected to a positive supply voltage VDD. can The plurality of transistors P0, P1, P2, ..., Pn, Pr may be PMOS transistors and may form a current mirror. Accordingly, the current I_0 flowing through the transistor P0 and the current drawn from the positive supply voltage VDD according to the size of each of the plurality of transistors P0, P1, P2, ..., Pn, Pr. The size can be determined. In some embodiments, the transistor P0 and the transistor Pr may have the same size, and accordingly, the read current I_RD may have approximately the same size as the current I_0.

The n transistors P1, P2, ..., Pn generating the reference current I_REF are the n transistors PS1, PS2, .. that are controlled by the current control signal CC[1:n]. .,PSn) and each can be connected in series. A current control signal CC[1:n] may be respectively applied to the gates of the n transistors PS1, PS2, ..., PSn, and accordingly, the current control signal CC[1:n] The size of the reference current I_REF may be determined by For example, when the transistor PS1 is turned on according to the low-level first current control signal CC[1], the current passing through the transistor P1 may be included in the reference current I_REF, while When the transistor PS1rk is turned off according to the high-level first current control signal CC[1], the current by the transistor P1 may be excluded from the reference current I_REF. The n transistors P1, P2, ..., Pn may have the same size in some embodiments, or different sizes in some embodiments.

7A and 7B are circuit diagrams illustrating examples of the reference resistor circuit 130 of FIG. 1 according to exemplary embodiments of the present disclosure. As described above with reference to FIG. 1, the reference resistor circuits 130a', 130a" of FIGS. 7A and 7B may provide a resistance through which the reference current I_REF passes, and when m is a positive integer, The resistance value of the resistor, that is, the reference resistance value R_REF, may be adjusted according to the resistance control signal RC[1:m] of the control circuits 150a' and 150a". The reference resistor circuits 130a ′, 130a″ of FIGS. 7A and 7B , as described above with reference to FIG. 5A , have a reference resistance value R_REF between the short-circuit source line SSL and the negative supply voltage VSS. It is possible to provide a resistor having a. Hereinafter, redundant content in the description of FIGS. 7A and 7B will be omitted.

Referring to FIG. 7A , the reference resistor circuit 130a' includes a plurality of resistors R1a, R2a, ..., Rma and a plurality of resistors R1a, R2a, ..., Rma respectively connected in series between the short-circuit source line SSL and the negative supply voltage VSS. of transistors N1a, N2a, ..., Nma. A resistance control signal RC[1:m] may be applied to the gates of the plurality of transistors N1a, N2a, ..., Nma, and accordingly, the resistance control signal RC[1:m] is The reference resistance value R_REF may be determined by For example, when the transistor N1a is turned on according to the high level first resistance control signal RC[1], the reference resistance R_REF may be determined by the first resistor R1a, while the low When the transistor N1a is turned off according to the level of the first resistance control signal RC[1], the reference resistance value R_REF may be determined regardless of the first resistance R1a. As a result, the reference resistance value R_REF of the reference resistance circuit 130a' is selected by the resistance control signal RC[1:m] among the plurality of resistors R1a, R2a, ..., Rma are connected in parallel. It can be determined from an equivalent circuit.

Referring to FIG. 7B , the reference resistor circuit 130a" may include a plurality of resistors R1b, R2b, ..., Rmb connected in series between a short-circuit source line SSL and a negative supply voltage VSS. and a plurality of resistors R1b, R2b, ..., Rmb and a plurality of transistors N1b, N2b, ..., Nmb connected in parallel, respectively. The resistance control signal RC[1:m] may be applied to the gates of N2b, ..., Nmb, and accordingly, the reference resistance value R_REF by the resistance control signal RC[1:m]. For example, when the transistor N1b is turned off according to the low-level first resistance control signal RC[1], the reference resistance value R_REF is the resistance value of the first resistance R1b. On the other hand, when the transistor N1b is turned on according to the high-level first resistance control signal RC[1], the reference resistance value R_REF is approximately equal to the turn-on resistance of the transistor N1b. When the value is zero, the first resistor R1b may not be included. As a result, the reference resistance value R_REF of the reference resistor circuit 130a" is the plurality of resistors R1b, R2b, ..., Rmb) selected by the resistance control signal RC[1:m] may be determined from an equivalent circuit connected in series.

8 is a flowchart illustrating a method of controlling a reference cell according to an exemplary embodiment of the present disclosure. As shown in FIG. 8 , the method of controlling a reference cell may include a plurality of steps ( S200 , S400 , S600 , and S800 ). In some embodiments, the method of FIG. 8 may be performed by the controller 200 including the reference trimmer 210 to control the reference cell R included in the memory device 100 of FIG. 1 . , hereinafter, FIG. 8 will be described with reference to FIG. 1 .

In operation S200, an operation of writing the same value to a plurality of memory cells may be performed. For example, an operation of writing '0' or writing '1' to the plurality of memory cells may be performed. A method of controlling the reference voltage may be determined in a subsequent operation S400 according to values written in the plurality of memory cells. An example of writing '0' in the plurality of memory cells will be described later with reference to FIG. 9A, and an example of writing '1' in the plurality of memory cells will be described later with reference to FIG. 9B.

In operation S400, an operation of generating monotonically increasing or monotonically decreasing reference voltages may be performed. For example, when '0' corresponding to the parallel resistance value R _P of the variable resistance element is written in the plurality of memory cells in operation S200, reference voltages monotonically increasing from the minimum reference voltage may be generated. On the other hand, when '1' corresponding to the antiparallel resistance value R _AP of the variable resistance element is written in the plurality of memory cells in operation S200 , reference voltages monotonically decreasing from the maximum reference voltage may be generated.

In operation S600 , an operation of reading a plurality of memory cells from each of the reference voltages may be performed. For example, an operation of reading a plurality of memory cells may be performed at each of monotonically increasing reference voltages, or an operation of reading a plurality of memory cells may be performed at each of monotonically decreasing reference voltages. Examples of the above steps S200 to S600 will be described later with reference to FIGS. 9A and 9B .

In operation S800 , an operation of determining the read reference voltage based on the read results may be performed. In some embodiments, the distribution (or first distribution) of the parallel resistance value R _P of the variable resistance value element from the results of reading the plurality of memory cells written as '0' at each of the monotonically increasing reference voltages. can be estimated. In some embodiments, from the results of reading the plurality of memory cells written as '1' at each of the monotonically decreasing reference voltages, the distribution of the antiparallel resistance R _AP of the variable resistance element (ie, the second distribution) ) can be estimated. The threshold resistance R _TH may be determined based on at least one of the estimated distributions, and the read reference voltage may be determined from the threshold resistance R _TH . Examples of step S800 will be described later with reference to FIGS. 10 to 13 .

9A and 9B are flowcharts illustrating examples of steps S200 to S600 of FIG. 8 according to exemplary embodiments of the present disclosure. As described above with reference to FIG. 8 , an operation of writing the same value to the plurality of memory cells may be performed in steps S200a and S200b of FIGS. 9A and 9B , and monotonically increasing or monotonically decreasing in steps S400a and S400b An operation of generating reference voltages may be performed, and an operation of reading a plurality of memory cells from each of the reference voltages may be performed in steps S600a and S600b. Hereinafter, FIGS. 9A and 9B will be described with reference to FIG. 1 and FIG. 4 showing the distribution of resistance values of the variable resistance element, and overlapping descriptions of FIGS. 9A and 9B will be omitted.

Referring to FIG. 9A , an operation of writing '0' to the plurality of memory cells may be performed in step S200a. For example, the controller 200 may transmit a write instructing command CMD, an address ADDR corresponding to a plurality of memory cells, and data DATA including '0' to the memory device 100 . . Accordingly, the plurality of memory cells may have distributed resistance values like the distribution of the parallel resistance values R _P of FIG. 4 . In some embodiments, '0' may be written in a plurality of memory cells connected to one word line WLi in the cell array 110 .

Step S400a may include steps S420a and S440a. In step S420a, an operation of setting a minimum reference current and a minimum reference resistance may be performed. For example, the controller 200 may transmit a reference adjustment signal ADJ corresponding to the minimum reference current and the minimum reference resistance to the memory device 100 , and the control circuit 150 of the memory device 100 may control the reference. By generating the current control signal CC and the resistance control signal RC in response to the signal ADJ, the reference current I_REF and the reference resistance value R_REF may be set to the minimum values, respectively. Accordingly, the reference voltage V_REF determined by the reference current I_REF and the reference resistance R_REF may have a minimum value, and the threshold resistance R _TH corresponding to the reference voltage V_REF is the parallel resistance R _P ) may be lower than the average of the dispersion.

In some embodiments, the reference current I_REF and the reference resistance value R_REF may not be set to minimum values. For example, based on the variation in the distribution of the parallel resistance value R _P , for the reference voltage V_REF corresponding to the threshold resistance value R _TH , which is lower than the average that the distribution of the parallel resistance value R _P may have, An arbitrary reference current I_REF and a reference resistance value R_REF may be set. As shown in FIG. 9A , step S620a may be performed subsequent to step S420a.

In operation S620a, an operation of reading a plurality of memory cells may be performed. For example, the controller 200 may transmit a read instructing command CMD and an address ADDR corresponding to the plurality of memory cells to the memory device 100 . In some embodiments, as described above with reference to FIG. 2 , the read command CMD and the address ADDR include a reference adjustment signal ADJ for setting the minimum reference current and the minimum reference resistance in step S420a and It may be synchronized and transmitted to the memory device 100 . The memory device 100 may transmit data DATA including a result of reading the memory cells in which '0' is written to the controller 200 using the set minimum reference current and the minimum reference voltage according to the minimum reference resistance. .

In operation S640a, an operation of determining whether to re-perform the read operation of the plurality of memory cells may be performed based on the number of '0' included in the read result. For example, as shown in FIG. 9A , in the reference trimmer 210 of the controller 200 , the number of '0's included in the data DATA received from the memory device 100, that is, the stored value is '0'. ' can be compared with a predetermined value 'X' (X > 0), and when the number of '0' is greater than or equal to 'X', the While reading may be stopped, if not, step S440a may be subsequently performed. That is, the setting operation of the reference current I_REF and the reference resistance value R_REF and the reading of the plurality of memory cells are performed until '0' is read from a predetermined number of memory cells in which '0' is written. The action may be repeated. In some embodiments, 'X' may correspond to the number of memory cells in which '0' is written, and in some embodiments, 'X' may be half the number of memory cells in which '0' is written.

In step S440a, an operation of setting an increased reference current and/or an increased reference resistance may be performed. For example, the controller 200 may transmit a reference adjustment signal ADJ corresponding to the increased reference current and/or the increased reference resistance to the memory device 100 , and the control circuit 150 of the memory device 100 . ) may set the increased reference current I_REF and the increased reference resistance R_REF by generating the current control signal CC and/or the resistance control signal RC in response to the reference control signal ADJ. Accordingly, the reference voltage V_REF may also increase, and the threshold resistance R _TH corresponding to the reference voltage V_REF may move to the right in the distribution of the parallel resistance R _P of FIG. 4 .

When steps S440a and S600a are repeated, the threshold resistance R _TH may move to the right in the distribution of the parallel resistance R _P according to the gradually increasing reference voltage V_REF . Accordingly, the distribution of the parallel resistance R _P may be estimated while the threshold resistance R _TH moves from the left to the right of the distribution of the parallel resistance R _P . An operation of estimating the distribution following step S600a and determining the read reference voltage from the estimated distribution, that is, examples of step S800 of FIG. 8 will be described later with reference to FIGS. 10 to 13 .

Referring to FIG. 9B , an operation of writing '1' to the plurality of memory cells may be performed in step S200b. Accordingly, the plurality of memory cells may have distributed resistance values as in the antiparallel resistance (R _AP ) distribution of FIG. 4 .

Step S400b may include steps S420b and S440b. In step S420b, an operation of setting the maximum reference current and the maximum reference resistance may be performed. For example, the controller 200 may transmit a reference adjustment signal ADJ corresponding to the maximum reference current and the maximum reference resistance to the memory device 100 , and the control circuit 150 of the memory device 100 may control the reference. By generating the current control signal CC and the resistance control signal RC in response to the signal ADJ, the reference current I_REF and the reference resistance value R_REF may be set to maximum values, respectively. Accordingly, the reference voltage V_REF determined by the reference current I_REF and the reference resistance R_REF may have a maximum value, and the threshold resistance R _TH corresponding to the reference voltage V_REF is the antiparallel resistance value ( R _AP ) may be higher than the average of the dispersion.

In some embodiments, the reference current I_REF and the reference resistance value R_REF may not be set to maximum values. For example, based on the variation in the distribution of the antiparallel resistance R _AP , the reference voltage V_REF corresponding to the threshold resistance R _TH that is higher than the average that the distribution of the antiparallel resistance R _AP may have is For this purpose, an arbitrary reference current I_REF and a reference resistance value R_REF may be set. As shown in FIG. 9B , step S620b may be performed subsequent to step S420b.

In operation S620b, an operation of reading a plurality of memory cells may be performed. Accordingly, the memory device 100 transmits, to the controller 200 , data DATA including a result of reading the memory cells in which '1' is written using the set maximum reference current and the maximum reference voltage according to the maximum reference resistance. can be transmitted

In operation S640b, an operation of determining whether to re-perform the read operation of the plurality of memory cells may be performed based on the number of '1's included in the read result. For example, as shown in FIG. 9B , in the reference trimmer 210 of the controller 200 , the number of '1's included in the data DATA received from the memory device 100, that is, the stored value is '1'. ' can be compared with a predetermined value of 'Y' (Y > 0), and when the number of '1's is 'Y' or greater, reference current and reference resistance settings and While reading may be stopped, if not, step S440b may be subsequently performed. That is, the operation of setting the reference current I_REF and the reference resistance value R_REF and reading the plurality of memory cells until '1' is read from a predetermined number of memory cells in which '1' is written. The action may be repeated. In some embodiments, 'Y' may correspond to the number of memory cells in which '1' is written, and in some embodiments, 'Y' may be half the number of memory cells in which '1' is written.

In step S440b, an operation of setting the reduced reference current and/or the reduced reference resistance may be performed. Accordingly, the reference voltage V_REF may also decrease, and the threshold resistance R _TH corresponding to the reference voltage V_REF may move to the left in the distribution of the antiparallel resistance R _AP of FIG. 4 .

When steps S440b and S600b are repeated, the threshold resistance R _TH may shift to the left in the distribution of the antiparallel resistance R _AP according to the gradually decreasing reference voltage V_REF . Accordingly, similar to the example of FIG. 9A , the distribution of the antiparallel resistance R _AP may be estimated while the threshold resistance R _TH moves from the right to the left of the distribution of the antiparallel resistance R _AP . .

10 is a flowchart illustrating an example of step S800 of FIG. 8 according to an exemplary embodiment of the present disclosure, and FIG. 11 is an operation in which a threshold resistance value is determined by step S800a of FIG. 10 according to an exemplary embodiment of the present disclosure. This is a graph showing an example. Specifically, in step S800a of FIG. 10 , the threshold resistance R _TH derived from the plurality of memory cells written as '0' as described above with reference to FIG. 9A and '1' as described above with reference to FIG. 9B This may be performed after the threshold resistance R _TH derived from the plurality of memory cells written as ' is prepared. As described above with reference to FIG. 8 , in step S800a of FIG. 10 , an operation of determining a read reference voltage based on results read from each of the reference voltages may be performed.

In operation S820a, an operation of estimating the distribution of the parallel resistance value R _P and the distribution of the antiparallel resistance value R _AP may be performed. For example, the threshold resistance value R _TH derived from the example of FIG. 9A may be estimated as the average R _P ′ of the distribution of the parallel resistance values R _P . In some embodiments, when the number of memory cells to which '0' is written and read is relatively large, it may be determined whether '0' is read from more than half of the memory cells (ie, 'X' in FIG. 9A ). When ' is half of the number of memory cells in which '0' is written), the threshold resistance R _TH in such a case may be estimated as an average of the distribution of the parallel resistance values R _P . In some embodiments, when the number of memory cells to which '0' is written and read is relatively small, it may be determined whether '0' is read from all of the memory cells (ie, 'X' in FIG. 9A is When '0' coincides with the number of written memory cells), the threshold resistance R _TH in such a case may be estimated as an average of the distribution of the parallel resistance values R _P . Similarly, the threshold resistance R _TH derived in the example of FIG. 9B may be estimated as the average R _AP ′ of the dispersion of the antiparallel resistance R _AP . In some embodiments, when the number of memory cells to which '1' is written and read is relatively large, 'Y' of FIG. 9B may be half of the number of memory cells to which '1' is written, in some embodiments , when the number of memory cells to which '1' is written and read is relatively small, 'Y' in FIG. 9B may match the number of memory cells to which '1' is written. Accordingly, as shown in FIG. 11 , by step S820a, the position of the distribution of the parallel resistance value R _P and the distribution of the high resistance value R _AP is the average ( _RP ') and half of the parallel resistance value ( _RP ). It can be estimated by the average (R _AP ') of the parallel resistance (R _AP ). By estimating the average in this way, the dispersion of the resistance values can be quickly estimated.

In operation S840a, an operation of calculating the threshold resistance R _TH from the distribution of the parallel resistance value R _P and the distribution of the antiparallel resistance value R _AP may be performed. In some embodiments, offsets based on standard deviations of the estimated distributions may be reflected in the average, and a threshold resistance (R _TH ) may be calculated from the reflected results. The standard deviations may be derived in advance by testing the variable resistance element (eg, the MTJ of FIG. 3 ), and as the standard deviation is reflected in the estimated average, the threshold resistance R _TH may be more accurately determined. For example, as shown in FIG. 11 , when a and b are greater than zero, the offset (a) proportional to the standard deviation (σ _P ) to the average ( _RP ′) of the parallel resistance values ( _RP ) ·σ _P ) can be added. In addition, an offset (b·σ _AP ) proportional to the standard deviation (σ _AP ) may be subtracted from the average (R _AP ′) of the antiparallel resistance values (R _AP ). Accordingly, the threshold resistance (R _TH ) is the averages (R _P ', R _AP ') and the standard deviations (σ _A , σ _AP ) are reflected values ( _{RP ' + a σ P ,} R _AP ' - b· σ _AP ) can be calculated by a function f having as factors. In some embodiments, the threshold resistance R _TH for reading the memory cell may be calculated as shown in Equation 1 below.

In operation S860a, an operation of determining a read reference current and/or a read reference resistance value may be performed. For example, the reference trimmer 210 may calculate a reference voltage V_REF corresponding to the threshold resistance R _TH calculated in step S840a, that is, a read reference voltage, and a reference current (V_REF) corresponding to the reference voltage V_REF. I_REF) and the reference resistance value R_REF may be determined as the read reference current and the read reference resistance value. Information on the determined read reference current and the read reference resistance value may be transmitted to the control circuit 150 of the memory device 100 , and the control circuit 150 may transmit information on the read reference current and the read reference resistance value to the read reference voltage. It may be stored in the non-volatile memory 160 as information about the .

12 is a flowchart illustrating an example of step S800 of FIG. 8 according to an exemplary embodiment of the present disclosure, and FIG. 13 is an operation in which a threshold resistance value is determined by step S800b of FIG. 12 according to an exemplary embodiment of the present disclosure. This is a graph showing an example. Specifically, in step S800b of FIG. 12 , compared with step S800a of FIG. 10 , only the threshold resistance R _TH determined from the plurality of memory cells written as '0' as described above with reference to FIG. 9A may be used. As described above with reference to FIG. 8 , in step S800b of FIG. 12 , an operation of determining a read reference voltage based on results read from each of the reference voltages may be performed. Hereinafter, content that overlaps with the description of FIG. 10 among the description of FIG. 12 will be omitted.

In operation S820b, an operation of estimating the distribution of the parallel resistance values R _P may be performed. Similar to step S820a of FIG. 10 , the threshold resistance R _TH derived in the example of FIG. 9A may be estimated as the average R _P ′ of the distribution of the parallel resistance values R _P . Accordingly, as shown in FIG. 13 , the location of the distribution of the parallel resistance values R _P may be estimated by the average R _P ′. In some embodiments, depending on the characteristics of the variable resistance element, the antiparallel resistance value R _AP may have a deteriorated distribution than the parallel resistance value R _P , so the distribution of the parallel resistance value R _P may be used. .

In operation S840b, an operation of calculating the threshold resistance R _TH from the distribution of the parallel resistance R _P may be performed. In some embodiments, an offset based on the standard deviation of the estimated distribution may be reflected in the average, and the threshold resistance R _TH may be calculated from the reflected result of the offset. For example, as shown in FIG. 13 , when c is greater than zero, the offset (c·σ) proportional to the standard deviation (σ _P ) to the average ( _RP ′) of the parallel resistance values ( _RP ) _P ) can be added. Accordingly, the threshold resistance (R _TH ) may be calculated by a function (g) having as a factor a value ( _RP ′ + c·σ _{P ) in which the standard deviation (σ P )} is reflected in the average ( _RP ′). . In some embodiments, the threshold resistance R _TH for reading the memory cell may be calculated as shown in Equation 2 below.

In operation S860b, an operation of determining a read reference current and/or a read reference resistance value may be performed. For example, the reference trimmer 210 may calculate a reference voltage V_REF corresponding to the threshold resistance R _TH calculated in step S840b , that is, a read reference voltage, and a reference current (V_REF) corresponding to the reference voltage V_REF. I_REF) and the reference resistance value R_REF may be determined as the read reference current and the read reference resistance value. Information on the determined read reference current and the read reference resistance value may be transmitted to the control circuit 150 of the memory device 100 , and the control circuit 150 may transmit information on the read reference current and the read reference resistance value to the read reference voltage. It may be stored in the non-volatile memory 160 as information about the .

14 is a block diagram of a memory device 300 according to an exemplary embodiment of the present disclosure. 14 , the memory device 300 may include an amplifier circuit 340 , a control circuit 350 , a nonvolatile memory 360 , and a reference trimmer 370 . Although not shown in FIG. 14 , the memory device 300 of FIG. 14 may include a cell array, a current source circuit, and a reference resistor circuit, similar to the memory device 100 of FIG. 1 . Hereinafter, content that overlaps with the description of FIG. 1 among the description of FIG. 14 will be omitted.

Compared with the memory device 100 of FIG. 1 , the memory device 300 of FIG. 14 may receive the calibration signal CAL and may further include a reference trimmer 370 . Accordingly, the memory device 300 may derive an accurate reference voltage by itself in response to the calibration signal CAL, and the system including the memory device 300 applies the calibration signal CAL to the memory device 300 . By providing it, it is possible to maintain the operational reliability of the memory device 300 .

The reference trimmer 370 may write the same value to the plurality of memory cells of the cell array in response to the received calibration signal CAL, and may be configured to generate monotonically increasing or monotonically decreasing reference voltages to the control circuit 350 . signal can be transmitted. The reference trimmer 370 may receive a signal corresponding to values read from the plurality of memory cells at each of the reference voltages from the amplification circuit 340 , and may determine the read reference voltage based on the read values. The reference trimmer 370 may provide information about the read reference voltage to the control circuit 350 , and the control circuit 350 may store information about the read reference voltage in the nonvolatile memory 360 . Thereafter, when the memory device 300 receives the read command, the control circuit 350 generates the read reference voltage based on the information about the read reference voltage stored in the nonvolatile memory 360 , the reference current I_REF and/or the reference resistance value R_REF may be controlled.

15 is a block diagram illustrating a system-on-chip 400 including a memory device according to an exemplary embodiment of the present disclosure. The System on Chip (SoC) 400 may refer to an integrated circuit in which components of a computing system or other electronic system are integrated. For example, as the system-on-chip 400, an application processor (AP) may include components for a processor and other functions. 15 , the system-on-chip 400 includes a core 410 , a digital signal processor (DSP) 420 , a graphic processing unit (GPU) 430 , a built-in memory 440 , and a communication interface. 450 and a memory interface 460 . Components of system-on-chip 400 may communicate with each other via bus 470 .

The core 410 may process instructions and control operations of components included in the system-on-chip 400 . For example, the core 410 may drive an operating system and execute applications on the operating system by processing a series of instructions. DSP 420 may generate useful data by processing a digital signal, such as a digital signal provided from communication interface 450 . The GPU 430 may generate data for an image output through the display device from image data provided from the built-in memory 440 or the memory interface 460 and may encode the image data.

The built-in memory 440 may store data necessary for the core 410 , the DSP 420 , and the GPU 430 to operate. The embedded memory 440 may include a resistive memory according to an exemplary embodiment of the present disclosure, and thus the embedded memory 440 may provide high reliability due to an accurate reference voltage.

The communication interface 450 may provide an interface for a communication network or one-to-one communication. The memory interface 460 may provide an interface to an external memory of the system-on-chip 400 , for example, a dynamic random access memory (DRAM), a flash memory, or the like.

Exemplary embodiments have been disclosed in the drawings and specification as described above. Although embodiments have been described using specific terms in the present specification, these are used only for the purpose of explaining the technical spirit of the present disclosure and not used to limit the meaning or scope of the present disclosure described in the claims. . Therefore, it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the true technical protection scope of the present disclosure should be defined by the technical spirit of the appended claims.

Claims (10)

A method of controlling a reference cell included in a resistive memory to determine values stored in a plurality of memory cells, the method comprising:
writing a first value to the plurality of memory cells;
providing monotonically increasing or monotonically decreasing reference currents to the reference cell;
reading the plurality of memory cells from each of the reference currents; and
determining a read reference current based on the read values;
The determining of the read reference current may include estimating a first distribution of resistance values corresponding to the first value of the memory cell based on the number of the first values among the read values. control method of the reference cell. The method according to claim 1,
Further comprising the step of setting the monotonically increasing or monotonically decreasing resistance values of the reference resistance connected to the reference cell and through which the reference current passes,
The reading may include reading the plurality of memory cells from each of the reference currents and resistance values of the reference resistor,
The method of controlling a reference cell further comprising determining a read reference resistance value based on the read values. delete The method according to claim 1,
The first value and the second value different from the first value correspond to low resistance values and high resistance values of the plurality of memory cells, respectively;
wherein providing the reference currents comprises providing monotonically increasing reference currents;
The estimating of the first distribution may include estimating a resistance value of a memory cell corresponding to a reference current when the number of the first values is equal to or greater than a predetermined number as a mean of the first distribution. How to control the cell. 5. The method according to claim 4,
writing the second value into the plurality of memory cells;
providing the reference currents further comprises providing monotonically decreasing reference currents;
The determining of the read reference current further includes estimating a second distribution of resistance values corresponding to the second value of the memory cell based on the number of the second values among the read values;
The estimating of the second distribution includes estimating the resistance value of the memory cell corresponding to the reference current as an average of the second distribution when the number of the second values is equal to or greater than a predetermined number. Way. 6. The method of claim 5,
The determining of the read reference current may include: a first resistance value obtained by adding a resistance value based on a standard deviation of the first distribution to an average of the first distribution, and an average of the second distribution to a standard deviation of the second distribution A reference cell control method, wherein a reference current corresponding to an intermediate value of a second resistance value obtained by subtracting a base resistance value is determined as the read reference current. 5. The method according to claim 4,
The determining of the read reference current further comprises calculating the read reference current based on a predefined function having an average of the first distribution as a factor. The method according to claim 1,
and writing control information corresponding to the read reference current into the resistive memory. A method of controlling a reference cell included in a resistive memory to determine values stored in a plurality of memory cells, the method comprising:
writing a first value to the plurality of memory cells;
setting resistance values that monotonically increase or decrease monotonically of a reference resistance connected to the reference cell and through which a reference current passes;
reading the plurality of memory cells from each of the resistance values of the reference resistor; and
determining a read reference resistance value based on the read values;
The determining of the read reference resistance value may include estimating a first distribution of resistance values corresponding to the first value of the memory cell based on the number of the first values among the read values. control method of the reference cell. A resistive memory device for receiving a reference adjustment signal, comprising:
a cell array comprising a memory cell and a reference cell, each coupled to different source lines and each coupled to different bit lines;
a current source circuit configured to provide a read current and a variable reference current to the memory cell and the reference cell respectively through the source lines in response to a read command;
an amplifier circuit configured to sense a voltage between the source lines respectively coupled to the memory cell and the reference cell; and
and a control circuit configured to control the current source circuit such that the reference current is adjusted independently of the read current according to the reference control signal.

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