TWI762718B - Resistive memory device including a reference cell and method of controlling a reference cell - Google Patents

Abstract

A method of controlling a reference cell in a resistive memory to identify values stored in a plurality of memory cells is provided. The method includes writing a first value to the plurality of memory cells, providing, to the reference cell, monotonically increasing or monotonically decreasing reference currents. The method includes reading the plurality of memory cells as each of the reference currents is provided to the reference cell, and determining a read reference current based on an aggregation of results of the reading.

Description

Resistive memory device including reference cell and method of controlling reference cell

The inventive concept relates to a resistive memory device, and more particularly, to a resistive memory device including a reference cell and a method of controlling the reference cell.

Resistive memory devices store data in memory cells that include variable resistive elements. To detect data stored in memory cells of a resistive memory device, a read current may be supplied to the memory cells, for example. The voltage generated by the read current of the memory cell and the variable resistance element can be detected.

In memory cells that store certain values, the resistance of the variable resistive element may have a distribution that may vary according to process voltage temperature (PVT) and the like. In order to accurately read the values stored in the memory cells, it may be important to accurately and instantaneously set threshold resistances that can be used to differentiate the distribution of resistances, which respectively correspond to different values.

The present inventive concept provides a resistive memory device, and more particularly, a resistive memory device capable of accurately reading a value stored in a memory cell by controlling a reference cell, and a method of controlling a reference cell.

According to one aspect of the present inventive concept, a method of controlling a reference cell included in a resistive memory to identify a value stored in a plurality of memory cells is provided. The method includes: writing a first value to a plurality of memory cells; providing a monotonically increasing or monotonically decreasing reference current to a reference cell; reading the plurality of memory cells while each of the reference currents is provided to the reference cell; and The read reference current is determined based on the read result.

According to another aspect of the present inventive concept, a method of controlling a reference cell in a resistive memory to identify a value stored in a plurality of memory cells is provided. The method includes: writing a first value to a plurality of memory cells; setting a monotonically increasing resistance or a monotonically decreasing resistance of a reference resistor connected to a reference cell, and passing a reference current through the reference resistor; reading a plurality of memory cells under each of the ; and determining a read reference resistance based on the read results.

According to another aspect of the present inventive concept, a resistive memory device configured to receive a reference adjustment signal is provided. A resistive memory device includes an array of cells that includes memory cells and reference cells. The memory cells are connected to the corresponding first source lines and the corresponding first bit lines, and the reference cells are connected to the second source lines and the second bit lines. The resistive memory device includes a current source circuit configured to provide a read current and a variable reference current to a memory cell and a reference cell, respectively, via a first source line or a second source line. The resistive memory device includes: an amplification circuit configured to detect a voltage between a first source line connected to the memory cell and a second source line connected to a reference cell; and a control circuit configured to control the current source circuit, So that the reference current can be adjusted without regard to the read current in response to the reference adjustment signal.

It should be noted that aspects of the inventive concepts described with respect to one embodiment may be incorporated into different embodiments (though not specifically described with respect thereto). That is, all embodiments and/or features of any embodiment may be combined in any manner and/or combination. These and other objects and/or aspects of the inventive concept are explained in detail in the specification set forth below.

1 is a block diagram illustrating a memory device 100 and a controller 200 according to example embodiments, and FIG. 2 is a diagram illustrating an example of communication between the memory device 100 and the controller 200 of FIG. 1 according to example embodiments timing diagram.

Referring to FIG. 1 , the memory device 100 may communicate with the controller 200 . The memory device 100 may receive a command CMD, such as a write command, a read command, and/or an address ADDR, from the controller 200, and may receive data DATA (ie, write data) and/or transfer data (ie, write data) from the controller 200. That is, read data) is sent to the controller 200 . Furthermore, as shown in FIG. 1 , the memory device 100 may receive the reference adjustment signal ADJ from the controller 200 . Although command CMD, address ADDR, data DATA, and reference adjustment signal ADJ are shown separately in FIG. 1, in some embodiments, command CMD, address ADDR, data DATA, and/or reference adjustment may be sent via the same channel at least two of the signals ADJ. As shown in FIG. 1, the memory device 100 may include a cell array 110, a current source circuit 120, a reference resistor circuit 130, an amplification circuit 140, a control circuit 150, and/or a non-volatile memory; NVM) 160. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. When preceding a list of elements, expressions such as "at least one of" and the like refer to the entire list of modified elements rather than the individual elements of the modified list.

The cell array 110 may include a plurality of memory cells M. The memory cell M may include a variable resistance element (eg, a magnetic tunnel junction (MTJ) shown in FIG. 3 ). The variable resistance element may have a resistance corresponding to the value stored in the memory cell M. FIG. Accordingly, the memory device 100 may be referred to as a resistive memory device, a resistive random access memory (RRAM) (or ReRAM), or the like. For example, by way of non-limiting example, the memory device 100 may include devices such as phase change random access memory (PRAM) or ferroelectric random access memory (FRAM) A cell array 110 of a structure, or including a cell array having a magnetic random access memory (MRAM) structure, such as a spin transfer torque-magnetic random access memory (spin transfer torque-magnetic random access memory; STT-MRAM), spin transfer torque magnetization switching RAM (Spin-RAM) and spin momentum transfer RAM (spin momentum transfer RAM; SMT-RAM) . As will be described with reference to FIG. 3, example embodiments will be described primarily with reference to MRAM, although it should be noted that example embodiments are not so limited.

Cell array 110 may include reference cells R for identifying values stored in memory cells M. FIG. For example, as shown in FIG. 1, cell array 110 may include a plurality of memory cells M and reference cells R that are typically connected to word line WLi, and thus, a plurality of memory cells that are typically connected to word line WLi M and reference cell R can be simultaneously selected by the activated word line WLi. Although only one reference cell R is shown in FIG. 1, in some embodiments, cell array 110 may include more than two reference cells connected to word line WLi.

The current source circuit 120 may provide the read current I_RD and the reference current I_REF to the cell array 110 . For example, the current source circuit 120 may provide the read current I_RD to the memory cell M and the reference current I_REF to the reference cell R. The current source circuit 120 may also adjust the reference current I_REF in response to the current control signal CC received from the control circuit 150 . An example of the current source circuit 120 will be described with reference to FIG. 6 .

The reference resistor circuit 130 may provide resistors through which the reference current I_REF passes. For example, the reference resistor circuit 130 may provide a resistor with a reference resistance R_REF between the first node N1 and the second node N2. In addition, the reference resistor circuit 130 may adjust the reference resistance R_REF according to the resistance control signal RC received from the control circuit 150 . The resistors of the reference resistor circuit 130 may have characteristics that are different from the characteristics of one or more resistors formed in the cell array 110 . In some embodiments, the resistors of the reference resistor circuit 130 may have better characteristics, such as being more sensitive to process voltage temperature (PVT) variations than one or more of the resistors formed in the cell array 110 . An example of the reference resistor circuit 130 will be described with reference to FIGS. 7A and 7B . It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, these elements should not be limited by these terms; One element is distinguished from another element. Thus, a first element discussed below could be termed a second element without departing from the scope of the inventive concept.

The amplification circuit 140 may receive the read voltage V_RD and the reference voltage V_REF, and may identify the value stored in the memory cell M based on the read voltage V_RD and the reference voltage V_REF. For example, by comparing the read voltage V_RD with the reference voltage V_REF, the amplifying circuit 140 can output a signal corresponding to the value stored in the memory cell M. The read voltage V_RD may include the voltage drop caused by the read current I_RD provided by the current source circuit 120 through the variable resistance element included in the memory cell M. FIG. In addition to including the voltage drop due to the memory cell M, the read voltage V_RD may further include the parasitic resistance of the path through which the read current I_RD passes (eg, the row decoder 170a, the source line SLj, and the bit line shown in FIG. 5A ). The voltage drop caused by the element line BLj).

Similar to the read voltage V_RD, the reference voltage V_REF may include not only the voltage drop generated when the reference current I_REF provided by the current source circuit 120 passes through the reference cell R, but also the parasitic resistance of the path passed by the reference current I_REF (eg, in FIG. 5A ). Row decoder 170a, short source line SSL, and short bit line SBL) shown in . In addition, the reference voltage V_REF may further include a voltage drop due to the reference resistor R_REF provided by the reference resistor circuit 130 . Therefore, by controlling the reference current I_REF and the reference resistance R_REF of the reference resistor circuit 130, the reference voltage V_REF can be adjusted, and the reference for identifying the value stored in the memory cell M can also be adjusted. In some embodiments, the reference resistance of the reference resistor may be monotonically increasing or monotonically decreasing. Specifically, the reference resistance may be a monotonically increasing resistance that repeatedly increases during multiple read or write cycles. In some embodiments, the reference resistance may be a monotonically decreasing resistance that decreases repeatedly during multiple read loops or write loops. This monotonically increasing or decreasing reference resistance can be, for example, a ladder sequence resistance or a linear ramp-shaped sequence resistance.

As described with reference to FIG. 5A and subsequent figures, in some embodiments, the reference cell R may be a short-circuit cell that does not include a resistor element such as a variable resistance element. Therefore, due to the characteristics of the reference resistor circuit 130, the reference voltage V_REF may be insensitive to PVT changes. As will be described with reference to FIG. 8 and subsequent figures, when the reference voltage V_REF is accurately determined, the operational reliability of the memory device 100 can be improved.

The control circuit 150 may control the current source circuit 120 and the reference resistor circuit 130 and/or access the NVM 160 by using the current control signal CC and the resistor control signal RC, respectively. In some embodiments, the control circuit 150 may generate the current control signal CC and the resistor control signal RC in response to the reference adjustment signal ADJ received from the controller 200 . For example, the control circuit 150 may increase or decrease the reference current I_REF and increase or decrease the reference resistance R_REF of the reference resistor circuit 130 based on the reference adjustment signal ADJ. Therefore, the reference voltage V_REF may be adjusted in response to the reference adjustment signal ADJ provided by the controller 200 .

In some embodiments, in order to adjust the reference voltage V_REF, one of the reference current I_REF or the reference resistance R_REF of the reference resistor circuit 130 may be fixed. For example, when the reference current I_REF is fixed, the control circuit 150 may not generate the current control signal CC, and adjust the reference resistance R_REF of the reference resistance circuit 130 by using the resistor control signal RC according to the reference adjustment signal ADJ. On the other hand, when the reference resistance R_REF of the reference resistor circuit 130 is fixed, the control circuit 150 may not generate the resistor control signal RC, and may adjust the reference current I_REF by using the current control signal CC according to the reference adjustment signal ADJ.

The NVM 160 may store data about the reference voltage V_REF. For example, NVM 160 may store data about a read reference current, which is a reference current used to read data from memory cell M, and data about a read reference resistor, the read reference The resistor is a reference resistor for reading data from the memory cell M. For example, control data corresponding to the read reference current can be written to resistive memory. In some embodiments, the control circuit 150 may write data about the reference voltage V_REF to the NVM 160 in response to a command CMD (or a set command) received from the controller 200 that commands the setting of the reference voltage V_REF, and in response to the control The command CMD (or read command) of the data read operation generates the current control signal CC and the resistance control signal RC according to the data stored in the NVM 160 . In some embodiments, NVM 160 may be omitted. For example, at least some of the memory cells M included in the cell array 110 may store data about the reference voltage V_REF and be accessed by the control circuit 150 .

Controller 200 may include reference trimmer 210 . The reference trimmer 210 may adjust the reference voltage V_REF of the memory device 100 by using the reference adjustment signal ADJ. Based on the results of reading data from the memory cell M according to the adjusted reference voltage V_REF, the reference trimmer 210 may illustrate the determination of the reference voltage V_REF, which may be the read reference voltage that will be used to read data from the memory cell M .

In some embodiments, the reference adjustment signal ADJ may be synchronized with the read command READ. That is, the reference adjustment signal ADJ may occur simultaneously with the read command READ overlapping in time, or before or following the read command READ, to be provided to the memory device 100 . For example, as shown in FIG. 2, the controller 200 may start providing the memory device 100 with the read command READ, the first address A1, and the first address A1 at time t1 by using the command CMD, the address ADDR, and the reference adjustment signal ADJ One option OP1. The control circuit 150 of the memory device 100 may generate the current control signal CC and the resistance control signal RC according to the first option OP1 , and thus may determine the reference current I_REF and the reference resistance R_REF of the reference resistor circuit 130 . According to the read command READ, the memory cell M and the reference cell R corresponding to the first address A1 can be selected. In addition, the value stored in the memory cell M can be identified by the read voltage V_RD of the memory cell M and the reference voltage V_REF according to the reference resistance R_REF of the reference resistor circuit 130 . The identified value may be provided to the controller 200 as the first output OUT1 via the data DATA. Similarly, at time t2, the memory device 100 may provide the second output OUT2 to the controller 200 in response to the controller 200's read command READ, the second address A2, and the second option OP2. In some embodiments, other than that depicted in FIG. 2, the reference adjustment signal ADJ may be synchronized with an exclusive command and provided to the memory device 100, which is a command other than the read command READ.

In some embodiments, according to the monotonically increasing or monotonically decreasing reference voltage, the reference trimmer 210 may read data from a plurality of memory cells to which predetermined values have been written and determine the read reference voltage based on the read result. Specifically, the reference voltage may be a monotonically increasing voltage that repeatedly increases during multiple read or write cycles. In some embodiments, the reference voltage may be a monotonically decreasing voltage that decreases repeatedly during multiple read loops or write loops. This monotonically increasing or decreasing reference voltage may be, for example, a staircase sequence voltage or a linear ramp-shaped sequence voltage.

As described above, by controlling the reference cell R, a precise threshold resistance of the memory cell M can be induced, as will be described later, and the value stored in the memory cell M can be accurately read. In addition, increased productivity of the memory device 100 may be provided since the precise threshold resistance is detected in real time, and self-adjusting calibration may be provided according to the operating environment of the memory device 100 .

3 is a diagram illustrating an example of the memory cell M of FIG. 1 according to example embodiments, and FIG. 4 is a graph illustrating the distribution of resistance provided by the memory cell M shown in FIG. 3 according to some example embodiments picture. Referring now to FIG. 3, a memory cell M' is shown containing a magnetic tunnel junction (MTJ) element as a variable resistance element. FIG. 4 shows the distribution of resistance for the MTJ element configured as the variable resistance element of FIG. 3 .

As shown in FIG. 3, the memory cell M' may include a variable resistance element (MTJ element) and a cell transistor CT connected in series between the bit line BLj and the source line SLj. In some embodiments, as shown in FIG. 3 , the variable resistance element (MTJ element) and the cell transistor CT may be arranged between the bit line BLj and the source line SLj as a variable resistance element (MTJ element) and Sequential connection of cell transistors CT. In some embodiments, different from that shown in FIG. 3 , the variable resistance element (MTJ element) and the cell transistor CT may be arranged between the bit line BLj and the source line SLj as the cell transistor CT and the variable resistance Sequential connection of elements (MTJ elements).

The variable resistance element (MTJ element) may include a free layer FL and a pinning layer PL, and a barrier layer BL between the free layer FL and the pinning layer PL. As marked with arrows in FIG. 3 , although the magnetization direction of the pinned layer PL may be fixed, the free layer FL may have the same or opposite magnetization to that of the pinned layer PL. When the pinned layer PL and the free layer FL have the same magnetization direction, the variable resistance element (MTJ element) may be said to be in a parallel state P. On the other hand, when the pinned layer PL and the free layer FL have different magnetization directions from each other, the variable resistance element (MTJ element) can be said to be in an anti-parallel state AP. In some embodiments, the variable resistance element (MTJ element) may further include an antiferromagnetic layer, so that the pinning layer PL may have a fixed magnetization direction.

A variable resistance element (MTJ element) that may have a low resistance R _P in a parallel state P may have a high resistance R _{AP in an anti-parallel state AP} . In the specification, it is assumed that when the variable resistance element (MTJ element) has a low resistance R _P , the memory cell M' stores '0', and when the variable resistance element (MTJ element) has a high resistance R _AP , the memory cell M''Save'1'. Also, in the specification, the resistance R _P corresponding to '0' may be referred to as a parallel resistance R _P , and the resistance R _AP corresponding to '1' may be referred to as an anti-parallel resistance R _AP . However, the various embodiments described herein are also applicable to the opposite storage situation.

Referring to FIG. 4, the resistance of the variable resistance element MTJ may have a distribution. For example, as shown in FIG. 4 , there may be a parallel resistance _RP distribution (or first distribution) between memory cells storing '0', and an anti-parallel resistance may exist between memory cells storing '1' R _AP distribution (or second distribution). In some embodiments, as depicted in FIG. 4 , the anti-parallel resistance R _AP distribution may be degraded, that is, have a higher variance than the parallel resistance R _P distribution. In other words, some values in the higher portion of the shunt resistance R _P distribution may be close to values in the lower portion of the anti-parallel resistance R _AP distribution. Furthermore, as marked with a dotted line in FIG. 4 , the distribution of the resistance of the variable resistance element (MTJ element) may be degraded for various reasons. Therefore, the range of threshold resistances R _TH used to distinguish the parallel resistance R _P distribution from the anti-parallel resistance R _AP distribution may be narrowed, and it may be important to determine an accurate threshold resistance R _TH . As will be described later with reference to FIGS. 8 to 13 , according to example embodiments, the distribution of the resistance of the variable resistance element MTJ may be estimated by controlling the reference unit R, and the threshold resistance R _TH may be determined based on the estimated distribution.

Referring again to FIG. 3 , the cell transistor CT may include a gate connected to the word line WLi, source and drain connected to the source line SLi and a variable resistance element (MTJ element), respectively. The cell transistor CT may electrically connect or separate the variable resistance element (MTJ element) from the source line SLj according to the signal applied to the word line WLi. For example, in a write operation, the cell transistor CT may be turned on to write '0' to the memory cell M', and the current flowing from the bit line BLj to the source line SLj may pass through the variable resistance element (MTJ element ) and unit transistor CT. To write '1' to memory cell M', cell transistor CT may be turned on, and current flowing from source line SLj to bit line BLj may pass through cell transistor CT and the variable resistance element (MTJ element). In a read operation, the cell transistor CT may be turned on, and the current flowing from the bit line BLj to the source line SLj or the current flowing from the source line SLj to the bit line BLj (ie, the read current I_RD) may pass through Unit transistor CT and variable resistance element (MTJ element). In the various embodiments described herein, it is assumed that read current I_RD flows from source line SLj to bit line BLj.

5A and 5B are block diagrams illustrating an example of the memory device 100 of FIG. 1 according to example embodiments. Referring now to FIGS. 5A and 5B, FIGS. 5A and 5B illustrate memory device 100a and memory device 100b, respectively, during a read operation. In the memory device 100a and the memory device 100b, the reference resistor circuit 130a and the reference resistor circuit 130b may be arranged differently from each other. Hereinafter, FIGS. 5A and 5B will be described with reference to FIG. 1 . In the descriptions of FIGS. 5A and 5B , the overlapping descriptions with those of FIG. 1 are omitted for the sake of brevity.

5A, the memory device 100a may include a cell array 110a, a current source circuit 120a, a reference resistor circuit 130a, an amplification circuit 140a, and a row decoder 170a. The cell array 110a may include memory cells M and reference cells R that are commonly connected to word line WLi. Each memory cell M can be connected to a bit line BLj and a source line SLj, and a reference cell R can be connected to a short bit line SBL and a short source line SSL. Bit line BLj, source line SLj, short bit line SBL, and short source line SSL may extend to and connect to row decoder 170a.

Memory cell M may include a variable resistance element (MTJ element) and cell transistor CT connected in series between bit line BLj and source line SLj, while reference cell R may include a short source connected to short bit line SBL and a short source The unit transistor CT of the pole line SSL. Therefore, the cell transistor CT, the short bit line SBL, and the short source line SSL of the reference cell R may be electrically short-circuited or electrically disconnected. A reference cell R that does not include a resistance element may be referred to as a short-circuit cell. In order to compensate for the voltage drop due to the bit line BLj and the source line SLj connected to the memory cell M, as shown in FIG. 5A, the reference cell R connected to the short bit line SBL and the short source line SSL can be arranged in the cell array 110a. As shown in FIG. 5A, the reference cell R may be a short-circuit cell. Therefore, the voltage drop due to the variable resistance element (MTJ element) of the memory cell M can be compared with the voltage drop due to the reference resistor circuit 130a arranged outside the cell array 110a. Not limited by the space and structure of the cell array 110, the reference resistor circuit 130a arranged outside the cell array 110a can provide a reference resistance R_REF with a wide variable range and insensitive to PVT and the like, so that a more accurate Adjust the reference voltage V_REF.

Row decoder 170a may route on bit line BLj, source line SLj, short bit line SBL, and short source line SSL according to the row address COL. The row address COL may be generated from the address ADDR received from the controller 200 of FIG. 1 . The row decoder 170a may select at least some of the memory cells and reference cells selected according to the enabled word line WLi in the cell array 110a according to the row address COL. For example, as shown in FIG. 5A, row decoder 170a may connect bit line BLj of memory cell M to negative supply voltage source VSS and connect source line SLj to current source circuit 120a. In addition, the row decoder 170a may connect the short bit line SBL of the reference cell R to the reference resistor circuit 130a and connect the short source line SSL to the current source circuit 120a. Therefore, the read current I_RD can flow through the source line SLj, the memory cell M, and the bit line BLj and toward the negative power supply voltage source VSS. The reference current I_REF may flow through the short source line SSL, the reference cell R, the short bit line SBL, and the reference resistor circuit 130a and toward the negative supply voltage source VSS.

The amplifying circuit 140a may be connected to a node through which the read current I_RD and the reference current I_REF are respectively output from the current source circuit 120a. The amplifying circuit 140a may generate the output signal Q according to the read voltage V_RD at the node and the reference voltage V_REF. The read voltage V_RD can be determined by the resistance of the variable resistance element (MTJ element) in the memory cell M and the read current I_RD, while the reference voltage V_REF can be determined by the reference resistance R_REF and the reference current I_REF. When the read voltage V_RD is higher than the reference voltage V_REF (that is, when the resistance of the variable resistance element (MTJ element) of the memory cell M is greater than the threshold resistance R _TH ), the amplifying circuit 140 a may generate a value corresponding to '1' output signal Q. When the read voltage V_RD is lower than the reference voltage V_REF (that is, when the resistance of the variable resistance element (MTJ element) of the memory cell M is smaller than the threshold resistance R _TH ), the amplifying circuit 140a may generate a voltage corresponding to '0' output signal Q.

5B, the memory device 100b may include a cell array 110b, a current source circuit 120b, a reference resistor circuit 130b, an amplification circuit 140b, and a row decoder 170bf. Compared to the memory device 100a of FIG. 5A, the memory device 100b of FIG. 5B may optionally further include a reference resistor circuit 130b disposed between the row decoder 170b and the current source circuit 120b. Therefore, the reference current I_REF may flow through the reference resistor circuit 130b, the short source line SSL, the reference cell R, and the short bit line SBL, and flow toward the negative power supply voltage source VSS. Hereinafter, example embodiments will be mainly described with reference to a situation like the memory device 100a of FIG. 5A in which the reference resistor circuit 130a is arranged between the reference cell R and the negative power supply voltage source VSS, but example embodiments are not limited thereto .

FIG. 6 is a circuit diagram illustrating the current source circuit 120 of FIG. 1 according to some example embodiments. As described above with reference to FIG. 1 , the current source circuit 120 ′ shown in FIG. 6 may generate the read current I_RD and the reference current I_REF, and when n is a positive integer, the current source circuit 120 ′ may The current control signals CC[1:n] are used to adjust the reference current I_REF.

Referring to FIG. 6, the current source circuit 120' may include a plurality of transistors P0, P1, P2 to Pn, Pr, the plurality of transistors having sources commonly connected to the positive supply voltage VDD . The plurality of transistors P0, P1, P2 to Pn, and Pr may be PMOS transistors and form a current mirror. Thus, the magnitude of the current being drawn from the positive supply voltage VDD can be determined based on the current I_0 flowing through transistor P0 and the respective sizes of the plurality of transistors P0, P1, P2 to Pn, Pr value. In some embodiments, transistor P0 and transistor Pr may have the same size. Therefore, the read current I_RD may have a magnitude that is substantially equal to the magnitude of the current I_0.

The n transistors P1 , P2 to Pn that generate the reference current I_REF may be respectively connected in series to the n transistors PS1 , PS2 to PSn controlled by the current control signal CC[1:n] . The current control signals CC[1:n] can be applied to the gates of n transistors PS1, PS2 to PSn, respectively, and thus the magnitude of the reference current I_REF can be determined by the current control signals CC[1:n] value. For example, when the transistor PS1 is turned on in response to the first current control signal CC[1] at a low level, the current through the transistor P1 may be included in the reference current I_REF. When the transistor PS1 is turned off in response to the high-level first current control signal CC[1], the current through the transistor P1 can be excluded from the reference current I_REF. The n transistors P1 , P2 through Pn may have the same size in some embodiments, and may have different sizes in some embodiments.

7A and 7B are circuit diagrams illustrating the reference resistor circuit 130 of FIG. 1 according to example embodiments. As described with reference to FIG. 1, the reference resistor circuit 130a' and the reference resistor circuit 130a'' of FIGS. 7A and 7B, respectively, may provide resistors through which the reference current I_REF passes, and when m is a positive integer, The resistance of the resistor, which is the reference resistance R_REF, may be adjusted in response to the control circuit 150a' and the resistor control signal RC[1:m] of the control circuit 150a". As described with reference to FIG. 5A , the reference resistor circuit 130a ′ of FIG. 7A and the reference resistor circuit 130a ″ of FIG. 7B may provide a reference resistor R_REF between the short source line SSL and the negative supply voltage source VSS, respectively Resistor. Hereinafter, in the descriptions of FIGS. 7A and 7B , repeated descriptions will not be given.

Referring to FIG. 7A, the reference resistor circuit 130a' between the short source line SSL and the negative supply voltage source VSS may include a plurality of resistors R1a, R2a to Rma, and are respectively connected in series to the plurality of resistors R1a , a plurality of transistors N1a from resistors R2a to Rma, transistors N2a to transistors Nma. Resistor control signals RC[1:m] may be applied to the gates of the plurality of transistors N1a, N2a to Nma, and thus the reference resistance R_REF may be determined by the resistor control signals RC[1:m] . For example, when the transistor N1a is turned on in response to the high-level first resistor control signal RC[1], the reference resistance R_REF can be determined by the first resistor R1a; when the transistor N1a is turned on in response to the low-level first resistor R1a; When the resistor controls RC[1] to turn off the transistor N1a, the reference resistance R_REF can be determined without considering the first resistor R1a. Therefore, the reference resistance R_REF of the reference resistor circuit 130a' can be determined by an equivalent circuit from among the plurality of resistors R1a, R2a and Rma by the resistor control signal RC[1:m] by connecting in parallel selected resistors to make the equivalent circuit.

7B, the reference resistor circuit 130a" may include a plurality of resistors R1b, R2b to Rmb connected in series between the short source line SSL and the negative supply voltage source VSS, and connected in parallel to the plurality of resistors, respectively. A plurality of transistors N1b, transistor N2b to transistor Nmb of resistor R1b, resistor R2b to resistor Rmb. Resistor control signals RC[1:m] may be applied to the gates of the plurality of transistors N1b, N2b to Nmb, and thus the reference resistance R_REF may be determined by the resistor control signals RC[1:m] . For example, when the transistor N1b is turned off in response to the first resistor control signal RC[1] of a low level, the reference resistor R_REF includes the resistance of the first resistor R1b; When the transistor N1b is turned on by the signal RC[1], the reference resistor R_REF may not include the resistance of the first resistor R1b when the on-resistance of the transistor N1b is close to 0. Therefore, the reference resistance R_REF of the reference resistor circuit 130a ″ can be determined by an equivalent circuit, selected by the resistor control signal RC[1:m] from the plurality of resistors R1b, R2b to Rmb by series connection resistors to make the equivalent circuit.

FIG. 8 is a flowchart illustrating a method of controlling a reference cell according to an example embodiment. As shown in FIG. 8 , the method of controlling a reference unit may include a plurality of operations S200, S400, S600, and S800. In some embodiments, in order to control the reference cell R included in the memory device 100 of FIG. 1 , the method described with reference to FIG. 8 may be performed by the controller 200 including the reference trimmer 210 . Hereinafter, FIG. 8 will be described with reference to FIG. 1 .

In operation S200, an operation of writing the same value to a plurality of memory cells may be performed. For example, writing '0' or '1' to multiple memory cells may be performed. According to the values written to the plurality of memory cells, in the following operation S400, a method of controlling the reference voltage may be determined. An example of writing '0' to a plurality of memory cells will be described later with reference to FIG. 9A , and an example of writing '1' to a plurality of memory cells will be described later with reference to FIG. 9B .

In operation S400, an operation of generating a monotonically increasing reference voltage or a monotonically decreasing reference voltage may be performed. For example, in operation _S200 , when '0' corresponding to the parallel resistance RP of the variable resistance element is written into the plurality of memory cells, a reference voltage monotonically increasing from the minimum reference voltage may be generated. On the other hand, in operation S200, when '1' corresponding to the anti-parallel resistance R _AP of the variable resistance element is written into the plurality of memory cells, a reference voltage monotonically decreasing from the maximum reference voltage may be generated.

In operation S600, an operation of reading data from a plurality of memory cells at each of the reference voltages may be performed. For example, an operation of reading data from a plurality of memory cells under monotonically increasing corresponding reference voltages may be performed, or an operation of reading data from a plurality of memory cells under monotonically decreasing corresponding reference voltages may be performed. Examples of operations S200 to S600 will be described with reference to FIGS. 9A and 9B .

In operation S800, an operation of determining a read reference voltage based on the read result may be performed. In some embodiments, the parallel resistance R of the variable resistive element can be estimated from the results of reading data from multiple memory cells written with '0' at each of a monotonically increasing reference voltage or a monotonically decreasing reference current _P distribution (or first distribution). In some embodiments, the anti-parallel resistance R _AP distribution (or second distribution). Based on at least one of the estimated distributions, a threshold resistance R _TH may be determined, from which a read reference voltage _may be determined. An example of operation S800 will be described with reference to FIGS. 10 to 13 .

FIGS. 9A and 9B are flowcharts illustrating examples of operations S200 to S600 of FIG. 8 , according to example embodiments. As described above with reference to FIG. 8 , in operation S200a of FIG. 9A and operation S200b of FIG. 9B , an operation of writing the same value to a plurality of memory cells may be performed. In operations S400a and S400b, an operation of generating a monotonically decreasing or increasing reference voltage may be performed. In operations S600a and S600b, an operation of reading data from a plurality of memory cells at each of the reference voltages may be performed. Hereinafter, FIGS. 9A and 9B will be described with reference to FIG. 1 and FIG. 4 illustrating the distribution of the resistance of the variable resistance element, and among the descriptions of FIGS. 9A and 9B , repeated descriptions will be omitted.

Referring to FIG. 9A, in operation S200a, an operation of writing '0' to a plurality of memory cells may be performed. For example, the controller 200 may send the command CMD for command writing, the addresses ADDR corresponding to the plurality of memory cells, and the data DATA including '0' to the memory device 100 . Thus, multiple memory cells may have resistances distributed similarly to the parallel resistance R _P distribution of FIG. 4 . In some embodiments, in the cell array 110, '0' may be written to multiple memory cells connected to the same word line WLi.

Operation S400a may include operation S420a and operation S440a. In operation S420a, an operation of setting a minimum reference current and a minimum reference resistance may be performed. For example, the controller 200 may send the reference adjustment signal ADJ corresponding to the minimum reference current and the minimum reference resistance to the memory device 100 . The control circuit 150 of the memory device 100 may set the reference current I_REF and the reference resistance R_REF to the minimum values by generating the current control signal CC and the resistor control signal RC in response to the reference adjustment signal ADJ, respectively. Therefore, the reference voltage V_REF determined by the reference current I_REF and the reference resistance R_REF may respectively have minimum values, and the threshold resistance R _TH corresponding to the reference voltage V_REF may be lower than the average of the parallel resistance R _P distribution.

In some embodiments, the reference current I_REF and the reference resistance R_REF may not be set to a minimum value. For example, an arbitrary reference current I_REF and an arbitrary reference resistance R_REF may be set for a reference voltage V_REF corresponding to a threshold resistance R _TH that is lower than the average of the distribution of parallel resistances _{R P} based on changes in the distribution of parallel resistances R TH number. As shown in FIG. 9A, in some embodiments, after operation S420a, operation S620a may be performed.

In operation S620a, an operation of reading data from a plurality of memory units may be performed. For example, the controller 200 may send a command CMD commanding a read operation and addresses ADDR corresponding to the plurality of memory cells to the memory device 100 . In some embodiments, as described above with reference to FIG. 2 , the command CMD and address ADDR for the read operation may be synchronized and sent to the memory device 100 with a reference adjustment signal ADJ used for The minimum reference current and minimum reference resistance in operation S420a are set. The memory device 100 may send data DATA to the controller 200, the data DATA including reading from a memory cell written to '0' by using a minimum reference voltage depending on the minimum reference current and minimum reference resistance that have been set The result of taking the data.

In operation S640a, based on the number of '0' included in the read result, an operation of determining whether to perform the read operation of the plurality of memory cells again may be performed. For example, as shown in FIG. 9A , the reference trimmer 210 of the controller 200 may compare the number of '0' included in the data DATA received from the memory device 100 with the default value 'X' (X> 0) In comparison, the number of '0' is the number of memory cells that are read as '0' from the value stored in the memory cell. When the number of '0' is equal to or greater than 'X', the operations of setting the reference current and the reference resistance and reading data from the plurality of memory cells may be stopped, and otherwise, operation S440a may be performed after operation S640a. In other words, the operation of setting the reference current I_REF and the reference resistance R_REF and the operation of reading data from a plurality of memory cells can be repeated until a certain number of memory cells are read from the plurality of memory cells in which '0' is written. '0'. In some embodiments, 'X' may be equal to the number of memory cells written with '0', and in some embodiments, 'X' may be half the number of memory cells written with '0'.

In operation S440a, an operation of setting an incrementing reference current and/or incrementing a reference resistance may be performed. For example, the controller 200 may send the reference adjustment signal ADJ corresponding to the increasing reference current and/or the increasing reference resistance to the memory device 100, and the control circuit 150 of the memory device 100 may generate current control by responding to the reference adjustment signal ADJ Signal CC and/or resistor control signal RC to set incremental reference current I_REF and incremental reference resistance R_REF. Therefore, the reference voltage V_REF can also be incremented, and the threshold resistance R _TH corresponding to the reference voltage _{V_REF} can be shifted from the parallel resistance RP distribution of FIG. 4 to the right of the graph.

When operations S440a and S600a are repeated, the threshold resistance R _TH may be shifted from the parallel resistance R _P distribution to the right of the graph of FIG. 4 according to the gradually increasing reference voltage V_REF. Therefore, since the threshold resistance R _TH migrates from the left to the right of the parallel resistance R _P distribution, the parallel resistance R _P distribution can be estimated. After operation S600a, the operation of estimating the distribution and determining the read reference voltage according to the estimated distribution will be described later with reference to FIGS. 10 to 13, such as the operation in the example of operation S800 of FIG.

Referring to FIG. 9B, in operation S200b, an operation of writing '1' to a plurality of memory cells may be performed. Thus, the plurality of memory cells may have resistance distributions similar to the anti-parallel resistance R _AP distribution of FIG. 4 .

Operation S400b may include operation S420b and operation S440b. In operation S420b, an operation of setting a maximum reference current and a maximum reference resistance may be performed. For example, the controller 200 may send the reference adjustment signal ADJ corresponding to the maximum reference current and the maximum reference resistance to the memory device 100 and the control circuit 150 of the memory device 100 . The control circuit 150 can set the maximum value of the reference current I_REF and the reference resistance R_REF by generating the current control signal CC and the reference control signal RC in response to the reference adjustment signal ADJ, respectively. Therefore, the reference voltage V_REF determined by the reference current I_REF and the reference resistance R_REF may have a maximum value, and the threshold resistance R _TH corresponding to the reference voltage V_REF may be higher than the average of the distribution of the anti-parallel resistance R _AP .

In some embodiments, the reference current I_REF and the reference resistance R_REF may not be set to the maximum value. For example, based on changes in the anti-parallel resistance R _AP distribution, the reference current I_REF and the reference resistance R_REF may be set for the reference voltage V_REF corresponding to the threshold resistance R _TH , which is higher than the anti-parallel resistance R _AP distribution may have average of. As shown in FIG. 9B, operation S620b may be performed after operation S420b.

In operation S620b, an operation of reading data from a plurality of memory units may be performed. Therefore, the memory device 100 can send data DATA to the controller 200, the data DATA including reading data from the memory cell written to '1' by using the maximum reference voltage depending on the maximum reference current and the maximum reference resistance the result of.

In operation S640b, based on the number of '1' included in the read result, an operation of determining whether to perform the read operation on the plurality of memory cells again may be performed. For example, as shown in FIG. 9B , the reference trimmer 210 of the controller 200 may compare the number of '1' included in the data DATA received from the memory device 100 with the default value 'Y' (Y> 0) In contrast, the number of '1' is the number of memory cells that are read as '1' from the value stored in the memory cell. When the number of '1' is equal to or greater than 'Y', the operation of setting the reference current and the reference resistance and the operation of reading data from the plurality of memory cells may be stopped, or otherwise, operation S440b may be performed after operation S640b. In other words, the operation of setting the reference current I_REF and the reference resistance R_REF and the operation of reading data from a plurality of memory cells can be repeated until a preset number of memory cells are read from the plurality of memory cells in which '1' is written to '1'. In some embodiments, 'Y' may be equal to the number of memory cells written with '1', and in some embodiments, 'Y' may be half the number of memory cells written with '1'.

In operation S440b, an operation of setting a decreasing reference current and/or decreasing a reference resistance may be performed. Therefore, the reference voltage V_REF can also be incremented, and the threshold resistance R _TH corresponding to the reference voltage _{V_REF} can be shifted from the parallel resistance RP distribution of FIG. 4 to the right of the graph.

When operations S440b and S600b are repeated, the threshold resistance R _TH may be shifted from the anti-parallel resistance R _AP distribution to the left according to the gradually decreasing reference voltage V_REF. Thus, similar to the embodiment of FIG. 9A , the anti-parallel resistance R _AP distribution can be estimated as the threshold resistance R _TH migrates from the right to the left of the anti-parallel resistance R _AP distribution.

10 is a flowchart illustrating an example of operation S800 of FIG. 8 according to some example embodiments, and FIG. 11 is a graph illustrating an example of an operation of determining a threshold resistance through operation S800a of FIG. 10 according to some example embodiments picture. In detail, operation S800a of FIG. 10 may be performed after the following operations: preparing the threshold resistance R _TH derived from the plurality of memory cells written with '0' as described above with reference to FIG. 9A ; and as described above with reference to FIG. 9A ; As described in 9B, the threshold resistance R _TH derived from the plurality of memory cells written with '1' is prepared. As described above with reference to FIG. 8, in operation S800a of FIG. 10, an operation of determining a read reference voltage based on a result from a read operation at each of the reference voltages may be performed.

In operation S820a, an operation of estimating the distribution of the parallel resistance R _P and the distribution of the anti-parallel resistance R _AP may be performed. For example, the threshold resistance R _TH derived from the embodiment of FIG. 9A can be estimated as the mean R _P ′ of the distribution of parallel resistances R _P . In some embodiments, when the number of memory cells to which '0's are written and from which '0's are read is relatively larger, it can be identified whether a '0' has been read from at least half of the memory cells (that is, , when 'X' in Figure 9 is half the number of memory cells that are written with '0'). In this case, the threshold resistance R _TH can be estimated as the average value of the distribution of parallel resistances R _P . 9 'X' in equals the number of memory cells that are written to '0'). In this case, the threshold resistance R _TH can be estimated as the average of the distribution of parallel resistances R _P . Similarly, the threshold resistance R _TH derived from the embodiment of FIG. 9B can be estimated as the mean R _AP ′ of the distribution of anti-parallel resistances R _AP . In some embodiments, 'Y' in FIG. 9B is the number of memory cells to which '1' is written when the number of memory cells to which '1' is written and from which '1' is read is relatively larger half. In some other embodiments, 'Y' in FIG. 9B may be equal to the number of memory cells to which '1' is written when the number of memory cells to which '1' is written and from which '1' is read is relatively smaller . Therefore, as shown in FIG. 11 , by operating _S820a , the azimuth and anti-parallel connection of the parallel resistance RP distribution can be estimated by the average number R _P ′ of the parallel resistance _{RP and the average value R AP ′} of the anti-parallel resistance R _AP The orientation of the resistance R _AP distribution. As described above, the distribution of resistance can be estimated instantaneously by estimating the mean.

[等式1]In operation S840a, an operation of calculating the threshold resistance R _TH according to the distribution of the parallel resistance R _P and the distribution of the anti-parallel resistance R _AP may be performed. In some embodiments, an offset based on the standard deviation of the estimated distribution can be applied to the mean, and the threshold resistance R _TH can be calculated from the result of applying the offset to the mean. The standard deviation can be pre-derived by testing a variable resistive element such as the MTJ of Figure 3. Since the standard deviation is applied to the estimated mean, the threshold resistance R _TH can be determined more accurately. For example, as shown in FIG. 11 , when the values a and b related to the number of cells are greater than 0, the offset a·σ _P , which is proportional to the standard deviation σ _P , can be made proportional to the difference between the parallel resistance R _P The averages R _P ' are added. In addition, an offset b·σ _AP proportional to the standard deviation σ _AP can be subtracted from the mean R _AP ′ of the anti-parallel resistances R _AP . Therefore, the threshold resistance R _TH can be calculated by a function f having as a factor the value R _P ′ + a·σ _P , the value R _AP ′ − b·σ _AP , the value R _P ′ + a·σ _P , the value R _AP ' - b·σ _AP is generated by applying standard deviation σ _A , standard deviation σ _AP to mean R _P ' and mean R _AP ', respectively. In some embodiments, the threshold resistance R _TH for reading data from a memory cell may be calculated based on [Equation 1] as written below. The read reference current may be based on the median value of the first resistance and the second resistance. The first resistance may be generated by adding the first standard resistance based on the standard deviation of the first distribution to the mean of the first distribution. The second resistance may be generated by subtracting a second standard resistance based on the standard deviation of the second distribution from the mean of the second distribution.

[Equation 1]

In operation S860a, an operation of determining a read reference current and/or a read reference resistance may be performed. For example, the reference trimmer 210 may calculate the reference voltage V_REF (ie, the read reference voltage) corresponding to the threshold resistance R _TH calculated in operation S840a, and may combine the reference current I_REF corresponding to the reference voltage V_REF with the reference resistance R_REF Determined to read reference current and read reference resistance. Information or data about the determined read reference current and read reference resistance may be sent to the control circuit 150 of the memory device 100 . The control circuit 150 may store data about the read reference current and read reference resistance in the NVM 160 as data about the read reference voltage.

12 is a flowchart illustrating operation S800 of FIG. 8 according to an example embodiment, and FIG. 13 is a graph illustrating an example of an operation of determining a threshold resistance through operation S800b of FIG. 12 . In detail, compared to operation S800a of FIG. 10 , operation S800b of FIG. 12 may use a threshold resistance R _TH determined according to a plurality of memory cells written with '0', as described above with reference to FIG. 9A . As described above with reference to FIG. 8 , in operation S800b of FIG. 12 , an operation of determining a read reference voltage based on a result of the read operation at each of the reference voltages may be performed. Hereinafter, among the descriptions of FIG. 12 , descriptions overlapping those of FIG. 10 will be omitted.

In operation S820b, an operation of estimating the distribution of the parallel resistance R _P may be performed. Similar to operation S820a of FIG. 10 , the threshold resistance R _TH derived from the example of FIG. 9A may be estimated as the mean R _P ′ of the parallel resistance distribution R _P . Therefore, as depicted in FIG. 13, the orientation of the parallel resistance distribution _RP can be estimated by the mean _RP '. In some embodiments, due to the characteristics of variable resistance elements, the anti-parallel resistance R _AP distribution may be degraded compared to the parallel resistance R _P distribution, and thus the parallel resistance R _P distribution may be used.

[等式2]In operation S840b, an operation of calculating the threshold resistance R _TH according to the distribution of the parallel resistance R _P may be performed. In some embodiments, an offset based on the standard deviation of the estimated distribution can be applied to the mean, and the threshold resistance R _TH can be calculated from the result of applying the offset to the mean. For example, as shown in FIG. 13 , when c is greater than 0, an offset c·σ _P proportional to the standard deviation σ _P may be added to the mean R _P ′ of the parallel resistances R _P . Thus, the threshold resistance R _TH can be calculated by a function g with the value R _P ′ ₊ c·σ _P as a factor by applying the standard deviation σ _P to the mean _{R P} ' to produce. In some embodiments, the threshold resistance R _TH used to read data from the memory cell may be calculated based on [Equation 2] as written below.

[Equation 2]

In operation S860b, an operation of determining a read reference current and/or a read reference resistance may be performed. For example, the reference trimmer 210 may determine the reference voltage V_REF (ie, the read reference voltage) corresponding to the threshold resistance R _TH calculated in operation S840b, and may combine the reference current I_REF corresponding to the reference voltage V_REF with the reference resistance R_REF Determined to read reference current and read reference resistance. Information or data about the determined read reference current and read reference resistance may be sent to control circuit 150 of memory device 100 , and control circuit 150 may send information or data about the read reference current and read reference resistance in NVM 160 The data is stored as data on the read reference voltage.

FIG. 14 is a block diagram of a memory device 300 according to an example embodiment. As shown in FIG. 14 , the memory device 300 may include an amplification circuit 340 , a control circuit 350 , a non-volatile memory 360 , and a reference trimmer 370 . Although not shown in FIG. 14 , the memory device 300 of FIG. 14 may include a cell array, a current source circuit, and/or a reference resistor circuit like the memory device 100 of FIG. 1 . Hereinafter, among the descriptions of FIG. 14 , descriptions overlapping those of FIG. 1 will be omitted.

Compared to the memory device 100 of FIG. 1 , the memory device 300 of FIG. 14 can receive the calibration signal CAL and further includes a reference trimmer 370 . Therefore, the memory device 300 can independently derive an accurate reference voltage in response to the calibration signal CAL, and a system including the memory device 300 can maintain the operational reliability of the memory device 300 by providing the calibration signal CAL to the memory device 300 .

The reference trimmer 370 may write the same value to a plurality of memory cells of the cell array in response to the received calibration signal CAL, and send the signal to the control circuit 350 for generating a monotonically increasing or monotonically decreasing reference voltage. The reference trimmer 370 may receive signals from the amplification circuit 340 corresponding to the values from the plurality of memory cells at each of the reference voltages, and may determine the read reference voltages based on the read results. Reference trimmer 370 may provide data about the read reference voltage to control circuit 350 , and control circuit 350 may store data about the read reference voltage in NVM 360 . Then, when the memory device 300 receives a read command, the control circuit 350 may control the reference current I_REF and/or the reference resistor R_REF to generate a reference voltage based on data about the read reference voltage stored in the NVM 360 .

15 is a block diagram illustrating a system on chip (SOC) 400 including a memory device, according to an example embodiment. SOC 400 may refer to an integrated circuit in which elements of a computing system or other electronic system are integrated. For example, as SOC 400, an application processor (AP) may include elements for the processor and other functions. As shown in FIG. 15 , the SoC 400 may include a core 410 , a digital signal processor (DSP) 420 , a graphics processing unit (GPU) 430 , an embedded memory 440 , and a communication interface 450 and memory interface 460. The elements of SoC 400 may communicate with each other via bus bar 470 .

The core 410 may process commands and control the operation of elements included in the system-on-chip 400 . For example, the core 410 may drive the operating system and execute applications in the operating system by processing a series of commands. DSP 420 may process digital signals, such as those provided by communication interface 450, to generate useful data. The GPU 430 may generate data for images output through the display device by using the image data provided by the embedded memory 440 or the memory interface 460, and may also encode the image data.

Embedded memory 440 may store data necessary for the operation of core 410 , DSP 420 and GPU 430 . The embedded memory 440 may include a resistive memory according to example embodiments, and thus, the embedded memory 440 may provide high reliability brought about by an accurate reference voltage.

Communication interface 450 may provide an interface for a communication network or one-to-one communication. Memory interface 460 may provide an interface for external memory, flash memory, and the like of SOC 400, such as dynamic random access memory (DRAM).

Although the inventive concept has been particularly shown and described with reference to embodiments of the inventive concept, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

100, 100a, 100b, 300‧‧‧Memory device 110, 110a, 110b‧‧‧Cell array 120, 120', 120a, 120b‧‧‧Current source circuit 130, 130a, 130a', 130a'', 130b‧ ‧‧Reference resistor circuit 140, 140a, 140b, 340‧‧‧Amplifying circuit 150, 150', 150a', 150a'', 350‧‧‧Control circuit 160, 360‧‧‧Non-volatile memory 170a, 170b ‧‧‧Line Decoder 200‧‧‧Controller 210, 370‧‧‧Reference Trimmer 400‧‧‧SoC 410‧‧‧Core 420‧‧‧Digital Signal Processor 430‧‧‧Graphic Processing Unit 440‧ ‧‧Embedded Memory 450‧‧‧Communication Interface 460‧‧‧Memory Interface 470‧‧‧Bus A1‧‧‧First Address A2‧‧‧Second Address ADDR‧‧‧Address ADJ‧‧ ‧Reference adjustment signals a σ _P , b σ _AP , c σ _P ‧‧‧Offset BL‧‧‧Barrier layer BLj‧‧‧Bit line CAL‧‧‧Calibration signals CC, CC[1: n]‧‧‧current control signal CC[1]‧‧‧first current control signal CMD‧‧‧command COL‧‧‧row address CT‧‧‧unit transistor DATA‧‧‧data FL‧‧‧free layer f, g‧‧‧function I_0‧‧‧current I_RD‧‧‧reading current I_REF‧‧‧reference current M, M'‧‧‧memory cell MTJ‧‧‧magnetic tunnel junction N1‧‧‧first node N1a, N1b, N2a, N2b, Nma, Nmb, P0, P1, P2, Pn, Pr, PS1, PS2, PSn‧‧‧Transistor N2‧‧‧Second Node OP1‧‧‧First Option OP2‧‧‧Second Option OUT1‧‧‧First output OUT2‧‧‧Second output PL‧‧‧Pining layer Q‧‧‧Output signal R‧‧‧Reference cell R1a, R1b, R2a, R2b, Rma, Rmb‧‧‧Resistor R _AP ‧‧‧Anti-parallel resistance R _AP '‧‧‧Average value of anti-parallel resistance RC‧‧‧Resistor control signal RC[1]‧‧‧First resistor control signal RC[1:m]‧‧‧ Resistor control signal READ‧‧‧read command R _P ‧‧‧parallel resistance R _P '‧‧‧average number of parallel resistance R_REF‧‧‧reference resistance R _TH ‧‧‧threshold resistance S200, S200a, S200b, S400, S400a, S400b, S420a, S420b, S440a, S440b, S600, S600a, S600b, S620a, S620b, S640a, S640b, S800, S800a, S800b, S820a, S820b, S840a, S840b, S860a, S8 ‧Operating SBL‧‧‧Short Bit Line SLj‧‧‧Source Line SSL‧‧‧Short Source Line t1, t2‧‧Time VDD‧‧‧Positive Supply Voltage V_RD‧‧‧Reading Voltage V_REF‧‧‧ Reference Voltage VSS‧‧‧Negative Power Supply Voltage Source WLi‧‧‧Word Line

Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG. 1 is a block diagram illustrating a memory device and a controller according to example embodiments. 2 is a timing diagram illustrating an example of communication between the memory device of FIG. 1 and a controller, according to an example embodiment. FIG. 3 is a diagram illustrating an example of the memory cell shown in FIG. 1 according to an example embodiment. FIG. 4 is a graph illustrating the distribution of resistance provided by the memory cell shown in FIG. 3 according to an example embodiment. 5A and 5B are block diagrams illustrating examples of the memory device of FIG. 1 according to example embodiments. FIG. 6 is a circuit diagram illustrating an example of the current source circuit shown in FIG. 1 according to an example embodiment. 7A and 7B are circuit diagrams illustrating examples of the reference resistor circuit shown in FIG. 1, according to example embodiments. FIG. 8 is a flowchart illustrating a method of controlling a reference cell according to an example embodiment. FIGS. 9A and 9B are flowcharts illustrating examples of operations S200 to S600 illustrated in FIG. 8 , according to example embodiments. FIG. 10 is a flowchart illustrating an example of operation S800 illustrated in FIG. 8 according to an example embodiment. FIG. 11 is a graph illustrating an example of an operation of determining a threshold resistance through operation S800a illustrated in FIG. 10 , according to example embodiments. FIG. 12 is a flowchart illustrating an example of operation S800b illustrated in FIG. 8 according to an example embodiment. FIG. 13 is a graph illustrating an example of an operation of determining a threshold resistance through operation S800b illustrated in FIG. 12 , according to example embodiments. 14 is a block diagram illustrating a memory device according to an example embodiment. 15 is a block diagram illustrating a system-on-chip including a memory device, according to an example embodiment.

100‧‧‧Memory Devices

110‧‧‧Cell Array

120‧‧‧Current Source Circuit

130‧‧‧Reference Resistor Circuit

140‧‧‧Amplifying Circuit

150‧‧‧Control circuit

160‧‧‧Non-volatile memory

200‧‧‧Controller

210‧‧‧Reference trimmer

ADDR‧‧‧address

ADJ‧‧‧reference adjustment signal

CC‧‧‧Current Control Signal

CMD‧‧‧command

DATA‧‧‧Data

I_RD‧‧‧Read Current

I_REF‧‧‧reference current

M‧‧‧memory unit

N1‧‧‧First Node

N2‧‧‧Second Node

R‧‧‧Reference Unit

RC‧‧‧resistor control signal

V_RD‧‧‧read voltage

V_REF‧‧‧reference voltage

WLi‧‧‧ word line

Claims (10)

A method of controlling a reference cell in a resistive memory to identify a value stored in a plurality of memory cells, the method comprising: writing a first value to the plurality of memory cells; providing monotonicity to the reference cell an increasing or monotonically decreasing reference current, wherein the reference cell is a short-circuit cell; while the reference current is monotonically increasing or monotonically decreasing, repeatedly reading the plurality of memory cells written as the first value; and based on The result of the repeated reading is used to determine the reading reference current. The method of claim 1 , further comprising: setting reference resistances of reference resistors associated with the reference cell, wherein some of the reference resistances correspond to the some of the reference currents, and wherein the reference resistances monotonically increase or decrease monotonically; and for each of the reference currents and the reference resistances corresponding to the reference resistors, based on reading from the plurality of memory cells A collection of the results of the data is taken to determine the read reference resistance. The method of claim 1, wherein determining the read reference current comprises: estimating, based on the number of the first values from the results of the repeated reads, corresponding to writing to the A first distribution of resistances of the first values of the plurality of memory cells. As the method described in item 3 of the scope of the application, wherein the first value and a second value different from the first value correspond to low resistance and high resistance, respectively, of the plurality of memory cells, wherein providing the reference current includes providing a monotonically increasing reference current, and wherein estimating The first distribution includes estimating based on a threshold resistance corresponding to a reference current when the number of the first values read is equal to or greater than a first threshold number of successful read operations of the first value the threshold resistance as the mean of the first distribution. The method of claim 4, further comprising: writing the second value to the plurality of memory cells, wherein providing the reference current further comprises providing a monotonically decreasing reference current, wherein determining the read Taking the reference current further comprises: estimating a second resistance corresponding to the second value written to the plurality of memory cells based on the number of the second value read in the result of the reading distribution, and wherein estimating the second distribution comprises: when the number of the second values read is equal to or greater than a second threshold number of successful read operations of the second value, based on a reference current corresponding to to estimate the threshold resistance as the mean of the second distribution. The method of claim 5, wherein determining the read reference current comprises: determining the read reference current based on a median value of a first resistance and a second resistance, wherein the read reference current is determined based on the first resistance adding a first standard resistance of the standard deviation of the distribution and the mean of the first distribution to generate the first resistance, and wherein the second resistance is generated by subtracting a second standard resistance based on the standard deviation of the second distribution from the mean of the second distribution. The method of claim 4, wherein determining the read reference current further comprises: calculating the read reference current based on a predefined function having an average of the first distribution as a factor. The method of claim 1, further comprising: writing control data corresponding to the read reference current to the resistive memory. A method of controlling a reference cell in a resistive memory to identify a value stored in a plurality of memory cells, the method comprising: writing a first value to the plurality of memory cells; setting a reference to passing a reference current Monotonically increasing or monotonically decreasing resistance of a resistor, wherein the reference current passes through the reference unit and the reference unit is a short-circuit unit; while the resistance of the reference resistor is monotonically increasing or monotonically decreasing, read and write repeatedly the plurality of memory cells being the first value; and determining a read reference resistance based on a set of results of the repeated reads. A resistive memory device configured to receive a reference conditioning signal, the resistive memory device comprising: a cell array including memory cells and reference cells, wherein the memory cells are connected to corresponding first source lines and corresponding the first element line of , and the reference in which a cell is connected to a second source line and a second bit line; a current source circuit configured to pass a read current and a variable reference current through the first source line or the first source line in response to a read command Two source lines are respectively provided to the memory cell and the reference cell; an amplification circuit is configured to detect the first source line connected to the memory cell and the second source line connected to the reference cell a voltage between source lines; and a control circuit configured to control the current source circuit such that the reference current can be adjusted in response to the reference adjustment signal regardless of the read current, wherein the The reference unit includes: a first transistor connected to the second source line and the second bit line, and having a gate connected to a word line connected to the memory cell at least one of wherein the first transistor is configured to electrically connect the second source line and the second bit line in response to the word line being activated, wherein the memory cell in One of the memory cells includes a magnetic tunnel junction (MTJ) element and a second transistor connected in series with a corresponding third source line of the first source lines connected to the memory cell and connected to to a corresponding third one of the first bit lines of the memory cell, and wherein the second transistor has a gate connected to the same word line as the reference cell.

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