TW201933353A - Resistive memory device including a reference cell and method of controlling a reference cell - Google Patents

Abstract

A method of controlling a reference cell in a resistive memory to identify values stored in a plurality of memory cells is provided. The method includes writing a first value to the plurality of memory cells, providing, to the reference cell, monotonically increasing or monotonically decreasing reference currents. The method includes reading the plurality of memory cells as each of the reference currents is provided to the reference cell, and determining a read reference current based on an aggregation of results of the reading.

Description

Resistive memory device including reference unit and method for controlling reference unit

The present inventive concept relates to a resistive memory device, and more particularly to a resistive memory device including a reference unit and a method of controlling the reference unit.

The resistive memory device stores data in a memory unit including a variable resistive element. In order to detect the data stored in the memory unit of the resistive memory device, for example, a read current can be supplied to the memory unit. The voltage generated by the read current of the memory cell and the variable resistance element can be detected.

In a memory cell that stores certain values, the resistance of the variable resistance element may have a distribution that may vary according to process voltage temperature (PVT) and the like. In order to accurately read the values stored in the memory cells, it is important to accurately and instantly set the threshold resistances that can be used to distinguish the distribution of the resistances, the distributions of which correspond to different values, respectively.

The present inventive concept provides a resistive memory device, and more particularly, a resistive memory device capable of accurately reading a value stored in a memory cell by controlling a reference unit and a method of controlling the reference unit.

In accordance with an aspect of the inventive concept, a method of controlling a reference unit included in a resistive memory to identify values stored in a plurality of memory cells is provided. The method includes: writing a first value to a plurality of memory cells; providing a monotonically increasing or monotonically decreasing reference current to the reference cells; reading the plurality of memory cells when each of the reference currents is provided to the reference cells; The read reference current is determined based on the read result.

In accordance with another aspect of the inventive concept, a method of controlling a reference unit in a resistive memory to identify values stored in a plurality of memory cells is provided. The method includes: writing a first value to a plurality of memory cells; setting a monotonically increasing resistance or a monotonically decreasing resistance of a reference resistor connected to the reference cell, and a reference current is passed through the reference resistor; a resistance at the reference resistor Reading a plurality of memory cells under each of them; and determining a read reference resistance based on the read result.

In accordance with another aspect of the inventive concept, a resistive memory device configured to receive a reference adjustment signal is provided. The resistive memory device includes an array of cells including a memory unit and a reference unit. The memory unit is connected to the corresponding first source line and the corresponding first bit line, and the reference unit is connected to the second source line and the second bit line. The resistive memory device includes a current source circuit configured to provide a read current and a variable reference current to the memory unit and the reference unit via a first source line or a second source line, respectively. The resistive memory device includes: an amplifying circuit configured to detect a voltage between a first source line connected to the memory unit and a second source line connected to the reference unit; and a control circuit configured to control the current source circuit, The reference current can be adjusted in response to the reference adjustment signal regardless of the read current.

It should be noted that aspects of the inventive concepts described with respect to one embodiment may be incorporated in various embodiments (although not specifically described herein). That is, the features of all embodiments and/or any embodiments can be combined in any manner and/or combination. These and other objects and/or aspects of the inventive concept are explained in detail in the description set forth below.

1 is a block diagram showing a memory device 100 and a controller 200 according to an example embodiment, and FIG. 2 is a diagram illustrating an example of communication between the memory device 100 of FIG. 1 and the controller 200, according to an example embodiment. Timing diagram.

Referring to FIG. 1, memory device 100 can be in communication with controller 200. The memory device 100 can receive a command CMD such as a write command, a read command, and/or an address ADDR from the controller 200, and can receive the data DATA (ie, write data) from the controller 200 and/or the data DATA ( That is, the read data is sent to the controller 200. Further, as shown in FIG. 1, the memory device 100 can receive the reference adjustment signal ADJ from the controller 200. Although the command CMD, the address ADDR, the data DATA, and the reference adjustment signal ADJ are shown separately in FIG. 1, in some embodiments, the command CMD, address ADDR, data DATA, and/or reference adjustment may be sent via the same channel. At least two of the signals ADJ. As shown in FIG. 1, the memory device 100 may include a cell array 110, a current source circuit 120, a reference resistor circuit 130, an amplifying circuit 140, a control circuit 150, and/or a non-volatile memory; NVM) 160. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items. When preceded by a list of elements, such as "at least one of" is used to describe the entire list of modified elements rather than the individual elements of the modified list.

The cell array 110 can include a plurality of memory cells M. The memory unit M may include a variable resistance element (such as a magnetic tunnel junction (MTJ) shown in FIG. 3). The variable resistance element may have a resistance corresponding to a value stored in the memory unit M. Therefore, the memory device 100 can be referred to as a resistive memory device, a resistive random access memory (RRAM) (or ReRAM), or the like. For example, as a non-limiting example, the memory device 100 can include, for example, a phase change random access memory (PRAM) or a ferroelectric random access memory (FRAM). The cell array 110 of the structure, or a cell array having a magnetic random access memory (MRAM) structure, such as a spin transfer torque-magnetic random access memory (Spin transfer torque-magnetic random access memory; STT-MRAM), spin transfer torque magnetization switching RAM (Spin-RAM) and spin momentum transfer RAM (SMT-RAM) . As will be described with reference to FIG. 3, an exemplary embodiment will be described mainly with reference to an MRAM, but it should be noted that the exemplary embodiments are not limited thereto.

The cell array 110 may include a reference cell R for identifying a value stored in the memory cell M. For example, as shown in FIG. 1, the cell array 110 may include a plurality of memory cells M and reference cells R that are typically connected to the word line WLi, and thus, a plurality of memory cells that are typically connected to the word line WLi M and the reference cell R can be simultaneously selected by the word line WLi that is activated. Although only one reference cell R is shown in FIG. 1, in some embodiments, cell array 110 can include more than two reference cells connected to word line WLi.

Current source circuit 120 can provide read current I_RD and reference current I_REF to cell array 110. For example, the current source circuit 120 can provide the read current I_RD to the memory unit M and the reference current I_REF to the reference unit R. Current source circuit 120 may also adjust reference current I_REF in response to current control signal CC received from control circuit 150. An example of the current source circuit 120 will be described with reference to FIG.

The reference resistor circuit 130 can provide a resistor through which the reference current I_REF passes. For example, the reference resistor circuit 130 can provide a resistor having a reference resistance R_REF between the first node N1 and the second node N2. Further, the reference resistor circuit 130 can adjust the reference resistance R_REF according to the resistance control signal RC received from the control circuit 150. The resistor of the reference resistor circuit 130 may have characteristics different from those of the one or more resistors formed in the cell array 110. In some embodiments, the resistors of reference resistor circuit 130 may have better characteristics, such as being more sensitive to process voltage temperature (PVT) variations than one or more of the resistors formed in cell array 110. An example of the reference resistor circuit 130 will be described with reference to FIGS. 7A and 7B. It will be understood that although the terms "first", "second", "third", etc., may be used herein to describe the various elements, these elements are not limited by these terms; in fact, these terms are used only for One component is distinguished from another component. Thus, the first element discussed below can be termed a second element without departing from the scope of the inventive concept.

The amplifying circuit 140 may receive the read voltage V_RD and the reference voltage V_REF, and may identify a value stored in the memory unit M based on the read voltage V_RD and the reference voltage V_REF. For example, by comparing the read voltage V_RD with the reference voltage V_REF, the amplifying circuit 140 can output a signal corresponding to the value stored in the memory unit M. The read voltage V_RD may include a voltage drop caused by the read current I_RD passing through a variable resistance element included in the memory unit M, which is supplied from the current source circuit 120. In addition to including the voltage drop due to the memory cell M, the read voltage V_RD may further include a parasitic resistance of the path through which the read current I_RD passes (for example, the row decoder 170a, the source line SLj, and the bit shown in FIG. 5A) The voltage drop produced by the line BLj).

Similar to the read voltage V_RD, the reference voltage V_REF may include not only the voltage drop generated when the reference current I_REF provided by the current source circuit 120 passes through the reference cell R, but also the parasitic resistance of the path passed by the reference current I_REF (for example, in FIG. 5A) The voltage drop generated by the row decoder 170a, the short source line SSL, and the short bit line SBL) shown in the figure. Further, the reference voltage V_REF may further include a voltage drop due to the reference resistance R_REF supplied from the reference resistor circuit 130. Therefore, by controlling the reference current I_REF and the reference resistance R_REF of the reference resistor circuit 130, the reference voltage V_REF can be adjusted, and a reference for identifying the value stored in the memory unit M can also be adjusted. In some embodiments, the reference resistor of the reference resistor can be monotonically increasing or monotonically decreasing. Specifically, the reference resistance can be a monotonically increasing resistance that is repeatedly raised during a plurality of read loops or write loops. In some embodiments, the reference resistance can be a monotonically decreasing resistance that is repeatedly reduced during a plurality of read loops or write loops. This monotonically increasing or decreasing reference resistance can be, for example, a step sequence resistor or a linear ramp sequence resistor.

As described with reference to FIG. 5A and subsequent figures, in some embodiments, the reference unit R may be a short-circuit unit that does not include a resistor element such as a variable resistance element. Therefore, due to the characteristics of the reference resistor circuit 130, the reference voltage V_REF may be insensitive to PVT variations. As will be described with reference to FIG. 8 and subsequent figures, the operational reliability of the memory device 100 can be improved when the reference voltage V_REF is accurately determined.

Control circuit 150 can control current source circuit 120 and reference resistor circuit 130, respectively, and/or access NVM 160 by using current control signal CC and resistor control signal RC. In some embodiments, control circuit 150 can generate current control signal CC and resistor control signal RC in response to reference adjustment signal ADJ received from controller 200. For example, control circuit 150 may increase or decrease reference current I_REF and increase or decrease reference resistance R_REF of reference resistor circuit 130 based on reference adjustment signal ADJ. Therefore, the reference voltage V_REF can be adjusted in response to the reference adjustment signal ADJ provided by the controller 200.

In some embodiments, to adjust the reference voltage V_REF, one of the reference current I_REF or the reference resistor R_REF of the reference resistor circuit 130 may be fixed. For example, when the reference current I_REF is fixed, the control circuit 150 may not generate the current control signal CC, and adjust the reference resistance R_REF of the reference resistance circuit 130 by using the resistor control signal RC according to the reference adjustment signal ADJ. On the other hand, when the reference resistance R_REF of the reference resistor circuit 130 is fixed, the control circuit 150 may not generate the resistor control signal RC, and may adjust the reference current I_REF by using the current control signal CC according to the reference adjustment signal ADJ.

The NVM 160 can store information about the reference voltage V_REF. For example, the NVM 160 can store data about reading a reference current and a reference current for reading a reference resistor, the read reference current being a reference current for reading data from the memory unit M, the read reference The resistor is a reference resistor for reading data from the memory unit M. For example, control data corresponding to the read reference current can be written to the resistive memory. In some embodiments, the control circuit 150 can write the information about the reference voltage V_REF to the NVM 160 in response to the set command CMD (or set command) of the command reference voltage V_REF received from the controller 200, and in response to the control The command CMD (or read command) of the read operation of the data is based on the data stored in the NVM 160 to generate the current control signal CC and the resistance control signal RC. In some embodiments, the NVM 160 can be omitted. For example, at least some of the memory cells M included in the cell array 110 can store data about the reference voltage V_REF and are accessed by the control circuit 150.

Controller 200 can include a reference spinner 210. The reference spinner 210 can adjust the reference voltage V_REF of the memory device 100 by using the reference adjustment signal ADJ. Based on the result of reading data from the memory unit M according to the adjusted reference voltage V_REF, the reference trimmer 210 may illustrate determining the reference voltage V_REF, which may be a read reference voltage to be used to read data from the memory unit M. .

In some embodiments, the reference adjustment signal ADJ can be synchronized with the read command READ. That is, the reference adjustment signal ADJ may occur simultaneously with the read command READ in time, or may occur before or after the read command READ to be supplied to the memory device 100. For example, as shown in FIG. 2, the controller 200 can start providing the read command READ, the first address A1, and the first to the memory device 100 at time t1 by using the command CMD, the address ADDR, and the reference adjustment signal ADJ. One option OP1. The control circuit 150 of the memory device 100 can generate the current control signal CC and the resistance control signal RC according to the first option OP1, and thus can determine the reference current I_REF and the reference resistance R_REF of the reference resistor circuit 130. According to the read command READ, the memory unit M and the reference unit R corresponding to the first address A1 can be selected. Further, the value stored in the memory unit M can be identified by the read voltage V_RD of the memory unit M and the reference voltage V_REF according to the reference resistor R_REF of the reference resistor circuit 130. The identified value can be provided to the controller 200 as the first output OUT1 via the data DATA. Similarly, at time t2, the memory device 100 can provide the second output OUT2 to the controller 200 in response to the read command READ of the controller 200, the second address A2, and the second option OP2. In some embodiments, unlike the one depicted in FIG. 2, the reference adjustment signal ADJ can be synchronized with the exclusive command and provided to the memory device 100, which is a command different from the read command READ.

In some embodiments, based on a monotonically increasing or monotonically decreasing reference voltage, the reference spinner 210 can read data from a plurality of memory cells that have been written with a predetermined value and determine a read reference voltage based on the read result. Specifically, the reference voltage may be a monotonically increasing voltage that is repeatedly raised during a plurality of read loops or write loops. In some embodiments, the reference voltage can be a monotonically decreasing voltage that is repeatedly reduced during multiple read loops or write loops. This monotonically increasing or decrementing reference voltage can be, for example, a step sequence voltage or a linear ramp sequence voltage.

As described above, by controlling the reference unit R, the precise threshold resistance of the memory unit M can be induced, as will be described later, and the value stored in the memory unit M can be accurately read. Moreover, since the accurate threshold resistance is detected on the fly, the increased productivity of the memory device 100 can be provided, and depending on the operating environment of the memory device 100, a self-adjusting calibration can be provided.

3 is a diagram illustrating an example of the memory unit M of FIG. 1 according to an example embodiment, and FIG. 4 is a graph illustrating a distribution of resistances provided by the memory unit M illustrated in FIG. 3 according to some example embodiments. Figure. Referring now to Figure 3, there is shown a memory cell M' comprising a magnetic tunnel junction (MTJ) element as a variable resistance element. 4 illustrates the distribution of resistance for an MTJ element configured as the variable resistance element of FIG.

As illustrated in FIG. 3, the memory cell M' may include a variable resistance element (MTJ element) and a cell transistor CT connected in series between the bit line BLj and the source line SLj. In some embodiments, as illustrated in FIG. 3, the variable resistance element (MTJ element) and the unit transistor CT may be a variable resistance element (MTJ element) between the bit line BLj and the source line SLj. The sequential connection of the unit transistors CT. In some embodiments, unlike the one shown in FIG. 3, the variable resistance element (MTJ element) and the unit transistor CT may be a unit transistor CT and a variable resistor between the bit line BLj and the source line SLj. The sequential connection of components (MTJ components).

The variable resistance element (MTJ element) may include a free layer FL and a pinning layer PL, and a barrier layer BL between the free layer FL and the pinning layer PL. As marked with an arrow in FIG. 3, although the magnetization direction of the pinning layer PL may be fixed, the free layer FL may have the same or opposite magnetization as the magnetization direction of the pinning layer PL. When the pinning layer PL and the free layer FL have the same magnetization direction, the variable resistance element (MTJ element) can be referred to as being in the parallel state P. On the other hand, when the pinning layer PL and the free layer FL have magnetization directions different from each other, the variable resistance element (MTJ element) can be referred to as being in the anti-parallel state AP. In some embodiments, the variable resistance element (MTJ element) may further comprise an antiferromagnetic layer such that the pinned layer PL may have a fixed magnetization direction.

The variable resistance element (MTJ element), which may have a low resistance R _P in the parallel state P, may have a high resistance R _AP in an anti-parallel state _AP . In the specification, it is assumed that when the variable resistance element (MTJ element) has a low resistance R _P , the memory unit M′ stores '0', and when the variable resistance element (MTJ element) has a high resistance R _AP , the memory unit M 'Save '1'. Further, in the specification, the resistance R _P corresponding to '0' may be referred to as a parallel resistance R _P , and the resistance R _AP corresponding to '1' may be referred to as an anti-parallel resistance R _AP . However, the various embodiments described herein are also applicable to the opposite storage scenarios.

Referring to FIG. 4, the resistance of the variable resistance element MTJ may have a distribution. For example, as shown in FIG. 4, there may be a parallel resistance R _P distribution (or first distribution) between memory cells storing '0', and an anti-parallel resistance may exist between memory cells storing '1' R _AP distribution (or second distribution). In some embodiments, as illustrated in FIG. 4, the anti-parallel resistance R _AP distribution may be degraded, that is, have a higher variance than the parallel resistance R _P distribution. In other words, some values of the higher portion of the parallel resistance R _P distribution may be close to the value in the lower portion of the anti-parallel resistance R _AP distribution. Further, as marked with a broken line in FIG. 4, the distribution of the resistance of the variable resistance element (MTJ element) may be deteriorated for various reasons. Therefore, the range of the threshold resistance R _TH for distinguishing the parallel resistance R _P distribution from the anti-parallel resistance R _AP distribution can be reduced, and determining the accurate threshold resistance R _TH can be important. As will be described later with reference to FIGS. 8 to 13, according to an exemplary embodiment, the distribution of the resistance of the variable resistance element MTJ may be estimated by controlling the reference unit R, and the threshold resistance R _TH may be determined based on the estimated distribution.

Referring again to FIG. 3, the unit transistor CT may include a gate connected to the word line WLi, a source and a drain connected to the source line SLi and the variable resistance element (MTJ element), respectively. The unit transistor CT may electrically connect or separate the variable resistance element (MTJ element) from the source line SLj according to a signal applied to the word line WLi. For example, in a write operation, the cell transistor CT may be turned on to write '0' to the memory cell M', and the current flowing from the bit line BLj to the source line SLj may pass through the variable resistance element (MTJ element) ) and unit transistor CT. In order to write '1' to the memory cell M', the cell transistor CT may be turned on, and the current flowing from the source line SLj to the bit line BLj may pass through the cell transistor CT and the variable resistance element (MTJ element). In the read operation, the cell transistor CT may be turned on, and a current flowing from the bit line BLj to the source line SLj or a current flowing from the source line SLj to the bit line BLj (ie, the read current I_RD) may pass Unit transistor CT and variable resistance element (MTJ element). In the various embodiments described herein, it is assumed that the read current I_RD flows from the source line SLj to the bit line BLj.

5A and 5B are block diagrams illustrating examples of the memory device 100 of FIG. 1 in accordance with an example embodiment. Referring now to Figures 5A and 5B, Figures 5A and 5B illustrate memory device 100a and memory device 100b, respectively, during a read operation. In the memory device 100a and the memory device 100b, the reference resistor circuit 130a and the reference resistor circuit 130b may be arranged differently from each other. Hereinafter, FIG. 5A and FIG. 5B will be described with reference to FIG. 1. In the description of FIGS. 5A and 5B, the description overlapping with the description of FIG. 1 is omitted for the sake of brevity.

Referring to FIG. 5A, the memory device 100a may include a cell array 110a, a current source circuit 120a, a reference resistor circuit 130a, an amplification circuit 140a, and a row decoder 170a. The cell array 110a may include a memory cell M and a reference cell R that are commonly connected to the word line WLi. Each of the memory cells M can be connected to the bit line BLj and the source line SLj, and the reference cell R can be connected to the short bit line SBL and the short source line SSL. The bit line BLj, the source line SLj, the short bit line SBL, and the short source line SSL may extend to the row decoder 170a and be connected to the row decoder 170a.

The memory unit M may include a variable resistance element (MTJ element) and a unit transistor CT connected in series between the bit line BLj and the source line SLj, and the reference unit R may include a connection to the short bit line SBL and the short source Cell CT of the line SSL. Therefore, the unit transistor CT, the short bit line SBL, and the short source line SSL of the reference unit R can be electrically short-circuited or electrically disconnected. The reference unit R that does not include a resistive element may be referred to as a short-circuit unit. In order to compensate for the voltage drop caused by the bit line BLj and the source line SLj connected to the memory cell M, as shown in FIG. 5A, the reference cell R connected to the short bit line SBL and the short source line SSL may be used. It is arranged in the cell array 110a. As illustrated in FIG. 5A, the reference unit R may be a short circuit unit. Therefore, the voltage drop caused by the variable resistance element (MTJ element) of the memory unit M can be compared with the voltage drop caused by the reference resistor circuit 130a disposed outside the cell array 110a. Without being limited by the space and structure of the cell array 110, the reference resistor circuit 130a disposed outside the cell array 110a can provide a reference resistor R_REF having a wide variable range and being insensitive to PVT and the like, so that it can be more accurately Adjust the reference voltage V_REF.

The row decoder 170a can route on the bit line BLj, the source line SLj, the short bit line SBL, and the short source line SSL according to the row address COL. The row address COL can be generated by the address ADDR received from the controller 200 of FIG. The row decoder 170a may select at least some of the memory unit and the reference unit according to the row address COL, the memory unit and the reference unit being selected according to the activated word line WLi in the cell array 110a. For example, as illustrated in FIG. 5A, the row decoder 170a may connect the bit line BLj of the memory cell M to the negative supply voltage source VSS and the source line SLj to the current source circuit 120a. Further, the row decoder 170a may connect the short bit line SBL of the reference unit R to the reference resistor circuit 130a and connect the short source line SSL to the current source circuit 120a. Therefore, the read current I_RD can flow through the source line SLj, the memory cell M, and the bit line BLj toward the negative supply voltage source VSS. The reference current I_REF may pass through the short source line SSL, the reference unit R, the short bit line SBL, and the reference resistor circuit 130a, and flow toward the negative supply voltage source VSS.

The amplifying circuit 140a is connectable to the node, and the read current I_RD and the reference current I_REF are respectively output from the current source circuit 120a through the node. The amplifying circuit 140a can generate the output signal Q according to the read voltage V_RD at the node and the reference voltage V_REF. The read voltage V_RD can be determined by the resistance of the variable resistance element (MTJ element) in the memory unit M and the read current I_RD, while the reference voltage V_REF can be determined by the reference resistor R_REF and the reference current I_REF. When the read voltage V_RD is higher than the reference voltage V_REF (that is, when the resistance of the variable resistance element (MTJ element) of the memory unit M is greater than the threshold resistance R _TH ), the amplifying circuit 140a may generate a corresponding value corresponding to '1' Output signal Q. When the read voltage V_RD is lower than the reference voltage V_REF (that is, when the resistance of the variable resistance element (MTJ element) of the memory unit M is smaller than the threshold resistance R _TH ), the amplification circuit 140a may generate a corresponding value corresponding to '0' Output signal Q.

Referring to FIG. 5B, the memory device 100b may include a cell array 110b, a current source circuit 120b, a reference resistor circuit 130b, an amplification circuit 140b, and a row decoder 170bf. The memory device 100b of FIG. 5B may optionally further include a reference resistor circuit 130b disposed between the row decoder 170b and the current source circuit 120b, as compared to the memory device 100a of FIG. 5A. Therefore, the reference current I_REF can pass through the reference resistor circuit 130b, the short source line SSL, the reference cell R, and the short bit line SBL, and flow toward the negative supply voltage source VSS. Hereinafter, an example embodiment will be described mainly with reference to a case similar to the memory device 100a of FIG. 5A in which the reference resistor circuit 130a is disposed between the reference cell R and the negative supply voltage source VSS, but the exemplary embodiment is not limited thereto. .

FIG. 6 is a circuit diagram of the current source circuit 120 of FIG. 1 in accordance with some example embodiments. As described above with reference to FIG. 1, the current source circuit 120' shown in FIG. 6 can generate the read current I_RD and the reference current I_REF, and when n is a positive integer, the current source circuit 120' can be according to the control circuit 150' The current control signal CC[1:n] adjusts the reference current I_REF.

Referring to FIG. 6, the current source circuit 120' may include a plurality of transistors P0, a transistor P1, a transistor P2 to a transistor Pn, and a transistor Pr having a source commonly connected to a positive supply voltage VDD. . The plurality of transistors P0, the transistors P1, the transistors P2 to the transistors Pn, and the transistors Pr may be PMOS transistors and form a current mirror. Therefore, the amplitude of the current being extracted from the positive power supply voltage VDD can be determined according to the current I_0 flowing through the transistor P0 and the corresponding sizes of the plurality of transistors P0, the transistor P1, the transistor P2 to the transistor Pn, and the transistor Pr. value. In some embodiments, the transistor P0 and the transistor Pr may have the same size. Therefore, the read current I_RD can have a magnitude substantially equivalent to the magnitude of the current I_0.

The n transistors P1, P2 to Pn generating the reference current I_REF may be respectively connected in series and connected to the n transistors PS1, PS2 to PSn controlled by the current control signals CC[1:n] . The current control signals CC[1:n] can be applied to the gates of the n transistors PS1, PS2 to PSn, respectively, and thus the amplitude of the reference current I_REF can be determined by the current control signal CC[1:n] value. For example, when the transistor PS1 is turned on in response to the low level first current control signal CC[1], the current through the transistor P1 may be included in the reference current I_REF. When the transistor PS1 is turned off in response to the high level first current control signal CC[1], the current through the transistor P1 can be excluded from the reference current I_REF. The n transistor P1, the transistor P2 to the transistor Pn may have the same size in some embodiments, and may have different sizes in some embodiments.

7A and 7B are circuit diagrams illustrating the reference resistor circuit 130 of FIG. 1 according to an example embodiment. As described with reference to FIG. 1, the reference resistor circuit 130a' and the reference resistor circuit 130a'' of FIGS. 7A and 7B may respectively provide a resistor through which the reference current I_REF passes, and when m is a positive integer, The resistance of the resistor can be adjusted in response to the resistor control signal RC[1:m] of the control circuit 150a' and the control circuit 150a'', which is the reference resistor R_REF. As described with reference to FIG. 5A, the reference resistor circuit 130a' of FIG. 7A and the reference resistor circuit 130a'' of FIG. 7B may provide a reference resistance R_REF between the short source line SSL and the negative supply voltage source VSS, respectively. Resistor. Hereinafter, in the description of FIGS. 7A and 7B, a repeated description will not be given.

Referring to FIG. 7A, the reference resistor circuit 130a' between the short source line SSL and the negative supply voltage source VSS may include a plurality of resistors R1a, resistors R2a to Rma, and are connected in series to the plurality of resistors R1a, respectively. a plurality of transistors N1a of the resistor R2a to the resistor Rma, and a transistor N2a to the transistor Nma. The resistor control signal RC[1:m] can be applied to the gates of the plurality of transistors N1a, the transistors N2a to the transistors Nma, and thus the reference resistor R_REF can be determined by the resistor control signal RC[1:m] . For example, when the transistor N1a is turned on in response to the high-level first resistor control signal RC[1], the reference resistor R_REF can be determined by the first resistor R1a; when the first response is to the low level When the resistor controls RC[1] and turns off the transistor N1a, the reference resistor R_REF can be determined without considering the first resistor R1a. Therefore, the reference resistor R_REF of the reference resistor circuit 130a' can be determined by an equivalent circuit, and the resistor control signal RC[1:m] is connected from the plurality of resistors R1a and R2a to the resistor Rma through the parallel connection. A resistor is selected to fabricate the equivalent circuit.

Referring to FIG. 7B, the reference resistor circuit 130a'' may include a plurality of resistors R1b, resistors R2b to resistors Rmb connected in series between the short source line SSL and the negative supply voltage source VSS, and are respectively connected in parallel to the plurality of resistors R1b, The resistor R1b, the resistor R2b to the plurality of transistors N1b of the resistor Rmb, and the transistor N2b to the transistor Nmb. The resistor control signal RC[1:m] can be applied to the gates of the plurality of transistors N1b, transistor N2b to the transistor Nmb, and thus the reference resistor R_REF can be determined by the resistor control signal RC[1:m] . For example, when the transistor N1b is turned off in response to the low-level first resistor control signal RC[1], the reference resistor R_REF includes the resistance of the first resistor R1b; when the first resistor is controlled in response to the high level When the transistor RC[1] is turned on and the transistor N1b is turned on, the reference resistor R_REF may not include the resistance of the first resistor R1b when the on-resistance of the transistor N1b is close to zero. Therefore, the reference resistor R_REF of the reference resistor circuit 130a'' can be determined by an equivalent circuit, and the resistor control signal RC[1:m] is selected from the plurality of resistors R1b and R5b to the resistor Rmb by series connection. Resistors to make the equivalent circuit.

FIG. 8 is a flow chart illustrating a method of controlling a reference unit, according to an example embodiment. As shown in FIG. 8, the method of controlling the reference unit may include a plurality of operations S200, S400, S600, and S800. In some embodiments, to control the reference unit R included in the memory device 100 of FIG. 1, the method described with reference to FIG. 8 may be performed by the controller 200 including the reference spinner 210. Hereinafter, FIG. 8 will be described with reference to FIG. 1.

In operation S200, an operation of writing the same value to a plurality of memory cells may be performed. For example, an operation of writing '0' or '1' to a plurality of memory cells can be performed. According to the value written to the plurality of memory cells, in the following operation S400, a method of controlling the reference voltage can be determined. An example of writing '0' to a plurality of memory cells will be described later with reference to FIG. 9A, and an example of writing '1' to a plurality of memory cells will be described later with reference to FIG. 9B.

In operation S400, an operation of generating a monotonically increasing reference voltage or a monotonically decreasing reference voltage may be performed. For example, in operation S200, when '0' corresponding to the parallel resistance R _P of the variable resistance element is written to the plurality of memory cells, a reference voltage monotonically increasing from the minimum reference voltage may be generated. On the other hand, in operation S200, when '1' corresponding to the anti-parallel resistance R _AP of the variable resistance element is written to the plurality of memory cells, a reference voltage monotonically decreasing from the maximum reference voltage may be generated.

In operation S600, an operation of reading data from a plurality of memory cells under each of the reference voltages may be performed. For example, an operation of reading data from a plurality of memory cells at a monotonically increasing corresponding reference voltage may be performed, or an operation of reading data from a plurality of memory cells at a monotonically decreasing corresponding reference voltage may be performed. An example of operations S200 to S600 will be described with reference to FIGS. 9A and 9B.

In operation S800, an operation of determining a read reference voltage based on the read result may be performed. In some embodiments, the parallel resistance R of the variable resistance element can be estimated based on the result of reading data from a plurality of memory cells written to '0' at each of the monotonically increasing reference voltage or the monotonically decreasing reference current. _P distribution (or first distribution). In some embodiments, the anti-parallel resistance R _AP distribution can be estimated based on the result of reading data from a plurality of memory cells written to '1' at each of the monotonically decreasing reference voltage or the monotonically increasing reference current (or Second distribution). Based on at least one of the estimated distributions, a threshold resistance _RTH can be determined, and the read reference voltage can be determined based on the threshold resistance _RTH . An example of operation S800 will be described with reference to FIGS. 10 to 13.

9A and 9B are flowcharts illustrating an example of operations S200 through S600 of FIG. 8 according to an example embodiment. As described above with reference to FIG. 8, in operation S200a of FIG. 9A and operation S200b of FIG. 9B, an operation of writing the same value to a plurality of memory cells can be performed. In operations S400a and S400b, an operation of generating a monotonically decreasing or increasing reference voltage may be performed. In operations S600a and S600b, an operation of reading data from a plurality of memory cells under each of the reference voltages may be performed. Hereinafter, FIG. 9A and FIG. 9B will be described with reference to FIG. 1 and FIG. 4 showing the distribution of the resistance of the variable resistance element, and among the descriptions of FIGS. 9A and 9B, the repeated description will be omitted.

Referring to FIG. 9A, in operation S200a, an operation of writing '0' to a plurality of memory cells may be performed. For example, the controller 200 may transmit a command CMD for command writing, an address ADDR corresponding to a plurality of memory cells, and a material DATA including '0' to the memory device 100. Thus, a plurality of memory units may have a resistance similar to the resistance of a parallel distribution of R 4 _P distribution. In some embodiments, in the cell array 110, '0' can be written to a plurality of memory cells connected to the same word line WLi.

Operation S400a may include operation S420a and operation S440a. In operation S420a, an operation of setting a minimum reference current and a minimum reference resistance may be performed. For example, the controller 200 can transmit a reference adjustment signal ADJ corresponding to the minimum reference current and the minimum reference resistance to the memory device 100. The control circuit 150 of the memory device 100 can set the reference current I_REF and the reference resistance R_REF to a minimum value, respectively, by generating a current control signal CC and a resistor control signal RC in response to the reference adjustment signal ADJ. Therefore, the reference voltage V_REF determined by the reference current I_REF and the reference resistance R_REF may have a minimum value, respectively, and the threshold resistance R _TH corresponding to the reference voltage V_REF may be lower than the average of the parallel resistance R _P distribution.

In some embodiments, the reference current I_REF and the reference resistance R_REF may not be set to a minimum value. For example, based on a change in the distribution of the parallel resistance R _P , an arbitrary reference current I_REF and an arbitrary reference resistance R_REF may be set for the reference voltage V_REF corresponding to the threshold resistance R _TH , which is lower than the average of the parallel resistance R _P distribution number. As shown in FIG. 9A, in some embodiments, after operation S420a, operation S620a may be performed.

In operation S620a, an operation of reading data from a plurality of memory cells may be performed. For example, the controller 200 may transmit a command CMD for command read operation and an address ADDR corresponding to a plurality of memory units to the memory device 100. In some embodiments, as described above with respect to FIG. 2, the command CMD and address ADDR for the read operation can be synchronized with the reference adjustment signal ADJ and sent to the memory device 100, the reference adjustment signal ADJ being used for The minimum reference current and the minimum reference resistance in operation S420a are set. The memory device 100 can transmit the data DATA to the controller 200, the material DATA including reading from the memory unit written to '0' by using the minimum reference voltage depending on the minimum reference current and the minimum reference resistance that have been set. Take the results of the data.

In operation S640a, based on the number of '0's included in the read result, an operation of determining whether to perform the read operation of the plurality of memory cells can be performed. For example, as illustrated in FIG. 9A, the reference spinner 210 of the controller 200 can count the number of '0's included in the material DATA received from the memory device 100 with a preset value of 'X' (X> 0) In comparison, the number of '0's is the number of memory cells read as '0' from the value stored in the memory unit. When the number of '0' is equal to or larger than 'X', the operation of setting the reference current and the reference resistance and reading data from the plurality of memory cells may be stopped, and otherwise, operation S440a may be performed after operation S640a. In other words, the operation of setting the reference current I_REF and the reference resistor R_REF and the operation of reading data from a plurality of memory cells can be repeatedly performed until a certain number of memory cells are read from a plurality of memory cells written to '0' '0'. In some embodiments, 'X' may be equal to the number of memory cells being written to '0', and in some embodiments, 'X' may be half the number of memory cells being written to '0'.

In operation S440a, an operation of setting an increment reference current and/or incrementing a reference resistance may be performed. For example, the controller 200 can transmit a reference adjustment signal ADJ corresponding to the incremental reference current and/or the incremental reference resistance to the memory device 100, and the control circuit 150 of the memory device 100 can generate current control by responding to the reference adjustment signal ADJ. Signal CC and/or resistor control signal RC to set incremental reference current I_REF and incremental reference resistor R_REF. Therefore, the reference voltage V_REF can also be incremented, and the threshold resistance R _TH corresponding to the reference voltage V_REF can migrate from the parallel resistance R _P distribution of FIG. 4 to the right of the graph.

When the operation is repeated operation S440a and S600a, gradually increasing according to the reference voltage V_REF, the threshold resistance R _TH may migrate from the shunt resistor R _P to the right distribution graph of FIG. 4. Thus, since the threshold resistance R _TH migrated from the left to the right in parallel with the resistor R _P distribution, it is possible to estimate the distribution of the parallel resistance R _P. After operation S600a, the operation of estimating the distribution and determining the read reference voltage according to the estimated distribution, such as the operation in the example of operation S800 of FIG. 8, will be described later with reference to FIGS. 10 through 13.

Referring to FIG. 9B, in operation S200b, an operation of writing '1' to a plurality of memory cells may be performed. Thus, a plurality of memory cells can have a similar distribution of resistance to the anti-parallel resistance R _AP distribution of FIG.

Operation S400b may include operation S420b and operation S440b. In operation S420b, an operation of setting a maximum reference current and a maximum reference resistance may be performed. For example, the controller 200 can transmit the reference adjustment signal ADJ corresponding to the maximum reference current and the maximum reference resistance to the memory device 100 and the control circuit 150 of the memory device 100. The control circuit 150 can set the maximum values of the reference current I_REF and the reference resistance R_REF, respectively, by generating the current control signal CC and the reference control signal RC in response to the reference adjustment signal ADJ. Therefore, the reference voltage V_REF determined by the reference current I_REF and the reference resistance R_REF may have a maximum value, and the threshold resistance R _TH corresponding to the reference voltage V_REF may be higher than the average of the anti-parallel resistance R _AP distribution.

In some embodiments, the reference current I_REF and the reference resistance R_REF may not be set to a maximum value. For example, based on a change in the anti-parallel resistance R _AP distribution, a reference current I_REF and a reference resistance R_REF may be set for a reference voltage V_REF corresponding to the threshold resistance R _TH , the threshold resistance being higher than the anti-parallel resistance R _AP distribution may have average value. As illustrated in FIG. 9B, operation S620b may be performed after operation S420b.

In operation S620b, an operation of reading data from a plurality of memory cells may be performed. Therefore, the memory device 100 can transmit the data DATA to the controller 200, and the data DATA includes reading data from the memory unit written to '1' by using the maximum reference voltage depending on the maximum reference current and the maximum reference resistance. the result of.

In operation S640b, based on the number of '1's included in the read result, an operation of determining whether to perform the read operation on the plurality of memory cells can be performed. For example, as illustrated in FIG. 9B, the reference spinner 210 of the controller 200 can count the number of '1's included in the material DATA received from the memory device 100 with a preset value of 'Y' (Y> 0) In comparison, the number of '1's is the number of memory cells read as '1' from the value stored in the memory unit. When the number of '1' is equal to or greater than 'Y', the operation of setting the reference current and the reference resistance and the operation of reading data from the plurality of memory cells may be stopped, or otherwise operation S440b may be performed after operation S640b. In other words, the operation of setting the reference current I_REF and the reference resistor R_REF and the operation of reading data from a plurality of memory cells can be repeatedly performed until a predetermined number of memory cells are read from a plurality of memory cells written to '1' Go to '1'. In some embodiments, 'Y' may be equal to the number of memory cells being written to '1', and in some embodiments, 'Y' may be half the number of memory cells being written to '1'.

In operation S440b, an operation of setting the decrementing reference current and/or decrementing the reference resistance may be performed. Therefore, the reference voltage V_REF can also be incremented, and the threshold resistance R _TH corresponding to the reference voltage V_REF can migrate from the parallel resistance R _P distribution of FIG. 4 to the right of the graph.

When the operation is repeated operation S440b and S600b, the reference voltage in accordance with the gradually decreasing V_REF, the threshold resistance R _TH may be distributed from anti-parallel resistors R _AP migrate to the left. Therefore, similar to the embodiment of FIG. 9A, since the threshold resistance R _TH migrates from the right to the left of the anti-parallel resistance R _AP distribution, the anti-parallel resistance R _AP distribution can be estimated.

FIG. 10 is a flow chart illustrating an example of operation S800 of FIG. 8 according to some example embodiments, and FIG. 11 is a graph illustrating an example of an operation of determining a threshold resistance by operation S800a of FIG. 10, according to some example embodiments. Figure. In detail, operation S800a of FIG. 10 may be performed after the following operations: preparing the threshold resistance R _TH derived from the plurality of memory cells written to '0' as described above with reference to FIG. 9A; and As described at 9B, a threshold resistance R _TH derived from a plurality of memory cells written to '1' is prepared. As described above with reference to FIG. 8, in operation S800a of FIG. 10, an operation of determining the read reference voltage based on the result from the read operation under each of the reference voltages may be performed.

In operation S820a, an operation of estimating the parallel resistance R _P distribution and the anti-parallel resistance R _AP distribution may be performed. For example, the threshold resistance R _TH derived from the embodiment of FIG. 9A can be estimated as the average number R _P ' of the parallel resistance R _P distribution. In some embodiments, when the number of memory cells that are written to '0' and reads '0' from it is relatively larger, it can be identified whether '0' is read from at least half of the memory cells (ie, When 'X' in Fig. 9 is half of the number of memory cells written to '0'). In this case, the threshold resistance R _TH can be estimated as the average value of the parallel resistance R _P distribution. In some embodiments, when the number of memory cells that are written to '0' and read '0' from it is relatively small, it can be identified whether '0' has been read from all memory cells (that is, when Figure 9 The 'X' in the middle is equal to the number of memory cells written to '0'). In this case, the threshold resistance R _TH can be estimated as the average of the parallel resistance R _P distribution. Similarly, the threshold resistance R _TH derived from the embodiment of FIG. 9B can be estimated as the average number R _AP ' of the anti-parallel resistance R _AP distribution. In some embodiments, when the number of memory cells that are written to '1' and read '1' therefrom is relatively larger, 'Y' in FIG. 9B is the number of memory cells written to '1' half. In some other embodiments, when the number of memory cells that are written to '1' and read '1' therefrom is relatively smaller, 'Y' in FIG. 9B may be equal to the number of memory cells being written to '1' . Therefore, as illustrated in FIG. 11, by operating S820a, the azimuth and anti-parallel of the parallel resistance R _P distribution can be estimated by the average number R _P ' of the parallel resistance R _P and the average value R _AP ' of the anti-parallel resistance R _AP . The orientation of the resistance R _AP distribution. As described above, the distribution of the resistance can be estimated instantaneously by estimating the average.

In operation S840a, the distribution can be calculated operating threshold resistance R _TH according to the distribution of the parallel resistance R _P and antiparallel the resistance R _AP. In some embodiments, an offset based on the standard deviation of the estimated distribution may be applied to the average, and the threshold resistance _RTH may be calculated from the result of applying the offset to the average. The standard deviation can be pre-derived by testing a variable resistance element (such as the MTJ of Figure 3). Since the standard deviation is applied to the estimated average value, the threshold resistance R _TH can be determined more accurately. For example, depicted in Figure 11, when the value associated with the number of units a and b is greater than 0, and the standard deviation σ _P can proportional to offset a · σ _P shunt resistor for R _P corresponds The average number R _P ' is added. Furthermore, 'by subtracting the standard deviation σ _AP is proportional to the offset b · σ _AP from the average resistance R _AP R _AP in the anti-parallel. Therefore, the threshold resistance R _TH can be calculated by a function f having a value R _P ' + a·σ _P as a factor and a value R _AP ' - b·σ _AP , the value R _P ' + a·σ _P , value R _AP ' - b·σ _AP is generated by applying the standard deviation σ _A and the standard deviation σ _AP to the average number R _P ' and the average number R _AP ', respectively. In some embodiments, the threshold resistance R _{TH for} reading data from the memory unit can be calculated based on [Equation 1] written as follows. The read reference current may be based on a median of the first resistance and the second resistance. The first resistance can be generated by adding a first standard resistance based on the standard deviation of the first distribution to an average of the first distribution. The second resistance can be generated by subtracting a second standard resistance based on the standard deviation of the second distribution from the average of the second distribution. [Equation 1]

In operation S860a, an operation of determining the read reference current and/or reading the reference resistance may be performed. For example, the reference spinner 210 can calculate a reference voltage V_REF (ie, a read reference voltage) corresponding to the threshold resistance R _TH calculated in operation S840a, and can reference the reference current I_REF and the reference resistor R_REF corresponding to the reference voltage V_REF. Determined to read the reference current and read the reference resistor. Information or data regarding the determined read reference current and read reference resistance may be sent to the control circuit 150 of the memory device 100. The control circuit 150 may store data regarding the read reference current and the read reference resistance in the NVM 160 as information on the read reference voltage.

FIG. 12 is a flowchart illustrating operation S800 of FIG. 8 according to an example embodiment, and FIG. 13 is a graph illustrating an example of an operation of determining a threshold resistance by operation S800b of FIG. In detail, FIG. 10 as compared to operation S800a, S800b 12 illustrating the operation of the threshold may be used to determine the resistance R _TH is written according to '0' a plurality of memory cells, as described above with reference to FIG 9A. As described above with reference to FIG. 8, in operation S800b of FIG. 12, an operation of determining the read reference voltage based on the result of the read operation under each of the reference voltages may be performed. Hereinafter, among the description of FIG. 12, a description overlapping with the description of FIG. 10 will be omitted.

In operation S820b, an operation of estimating the distribution of the parallel resistance R _P may be performed. Similar to operation S820a of FIG. 10, the threshold resistance R _TH derived from the example of FIG. 9A can be estimated as the average number R _P ' of the parallel resistance distribution R _P . Therefore, as illustrated in FIG. 13, the orientation of the parallel resistance distribution R _P can be estimated by the average number R _P '. In some embodiments, due to the characteristics of the variable resistance element, the anti-parallel resistance R _AP distribution may be degraded compared to the parallel resistance R _P distribution, and thus the parallel resistance R _P distribution may be used.

In operation S840b, an operation of calculating the threshold resistance R _TH according to the parallel resistance R _P distribution may be performed. In some embodiments, an offset based on the standard deviation of the estimated distribution may be applied to the average, and the threshold resistance _RTH may be calculated from the result of applying the offset to the average. For example, as illustrated in FIG. 13, when c is greater than 0, the offset c·σ _P proportional to the standard deviation σ _{P may} be added to the average number R _P ' of the parallel resistance R _P . Accordingly, as a factor the value of R _P '+ g c · σ _P function to calculate the threshold resistance R _TH, the value of R _P' by having a + c · σ _P by the average standard deviation σ _P R _P applied 'To produce. In some embodiments, the threshold resistance _RTH used to read data from the memory unit can be calculated based on [Equation 2] as written below. [Equation 2]

In operation S860b, an operation of determining a read reference current and/or reading a reference resistance may be performed. For example, the reference spinner 210 may determine a reference voltage V_REF corresponding to the threshold resistance R _TH calculated in operation S840b (ie, read the reference voltage), and may reference the reference current I_REF and the reference resistor R_REF corresponding to the reference voltage V_REF. Determined to read the reference current and read the reference resistor. Information or data regarding the determined read reference current and read reference resistance may be sent to the control circuit 150 of the memory device 100, and the control circuit 150 may be related to the read reference current and the read reference resistor in the NVM 160. The data is stored as information about reading the reference voltage.

FIG. 14 is a block diagram of a memory device 300, in accordance with an example embodiment. As shown in FIG. 14, the memory device 300 can include an amplification circuit 340, a control circuit 350, a non-volatile memory 360, and a reference spinner 370. Although not shown in FIG. 14, the memory device 300 of FIG. 14 may include a cell array, a current source circuit, and/or a reference resistance circuit like the memory device 100 of FIG. Hereinafter, in the description of FIG. 14, a description overlapping with the description of FIG. 1 will be omitted.

Compared to the memory device 100 of FIG. 1, the memory device 300 of FIG. 14 can receive the calibration signal CAL and further include the reference spinner 370. Therefore, the memory device 300 can independently derive an accurate reference voltage in response to the calibration signal CAL, and the system including the memory device 300 can maintain the operational reliability of the memory device 300 by providing the calibration signal CAL to the memory device 300. .

The reference spinner 370 can write the same value to the plurality of memory cells of the cell array in response to the received calibration signal CAL and send the signal to the control circuit 350 for generating a monotonically increasing or monotonically decreasing reference voltage. The reference spinner 370 can receive a signal from the amplifying circuit 340 that corresponds to a value from a plurality of memory cells at each of the reference voltages, and can determine the read reference voltage based on the read result. The reference spinner 370 can provide information about the read reference voltage to the control circuit 350, and the control circuit 350 can store information about the read reference voltage in the NVM 360. Then, when the memory device 300 receives the read command, the control circuit 350 can control the reference current I_REF and/or the reference resistor R_REF to generate the reference voltage based on the data on the read reference voltage stored in the NVM 360.

FIG. 15 is a block diagram showing a system on chip (SOC) 400 including a memory device, according to an example embodiment. SOC 400 may refer to an integrated circuit in which components of a computing system or other electronic system are integrated. For example, as the SOC 400, an application processor (AP) may include components for the processor and other functions. As shown in FIG. 15, the system single chip 400 may include a core 410, a digital signal processor (DSP) 420, a graphics processing unit (GPU) 430, an embedded memory 440, and a communication interface. 450 and memory interface 460. Elements of system single wafer 400 may be in communication with each other via bus bar 470.

Core 410 can process commands and control the operation of the components contained in system single wafer 400. For example, core 410 can drive a system of operations and execute applications in the operating system by processing a series of commands. The DSP 420 can process digital signals to produce useful data, such as digital signals provided by the communication interface 450. The GPU 430 can generate data for an image output through the display device by using image data provided by the embedded memory 440 or the memory interface 460, and can also encode the image material.

Embedded memory 440 can store data necessary for operation of core 410, DSP 420, and GPU 430. The embedded memory 440 can include a resistive memory according to an example embodiment, and thus, the embedded memory 440 can provide high reliability brought by an accurate reference voltage.

Communication interface 450 can provide an interface for communication networks or one-to-one communication. The memory interface 460 can provide an interface for external memory, flash memory, and the like of the SOC 400, such as a dynamic random access memory (DRAM).

While the present invention has been particularly shown and described with reference to the embodiments of the present invention, it is understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

100, 100a, 100b, 300‧‧‧ memory devices

110, 110a, 110b‧‧‧ unit array

120, 120', 120a, 120b‧‧‧ current source circuit

130, 130a, 130a', 130a'', 130b‧‧‧ reference resistor circuit

140, 140a, 140b, 340‧‧‧ amplifying circuit

150, 150', 150a', 150a'', 350‧‧‧ control circuit

160, 360‧‧‧ non-volatile memory

170a, 170b‧‧‧ row decoder

200‧‧‧ controller

210, 370‧‧‧ reference spinner

400‧‧‧ system single chip

410‧‧‧ core

420‧‧‧Digital Signal Processor

430‧‧‧Graphic Processing Unit

440‧‧‧ embedded memory

450‧‧‧Communication interface

460‧‧‧ memory interface

470‧‧ ‧ busbar

A1‧‧‧ first address

A2‧‧‧ second address

ADDR‧‧‧ address

ADJ‧‧‧ reference adjustment signal

a·σ _P , b·σ _AP , c·σ _P ‧‧‧ offset

BL‧‧‧ barrier layer

BLj‧‧‧ bit line

CAL‧‧‧ calibration signal

CC, CC[1:n]‧‧‧ current control signals

CC[1]‧‧‧First current control signal

CMD‧‧‧ Order

COL‧‧‧ address

CT‧‧‧ unit transistor

DATA‧‧‧Information

FL‧‧‧ free layer

f, g‧‧‧ function

I_0‧‧‧current

I_RD‧‧‧Read current

I_REF‧‧‧reference current

M, M'‧‧‧ memory unit

MTJ‧‧‧ magnetic tunnel junction

N1‧‧‧ first node

N1a, N1b, N2a, N2b, Nma, Nmb, P0, P1, P2, Pn, Pr, PS1, PS2, PSn‧‧‧ transistor

N2‧‧‧ second node

OP1‧‧‧ first option

OP2‧‧‧ second option

OUT1‧‧‧ first output

OUT2‧‧‧ second output

PL‧‧‧ pinned layer

Q‧‧‧Output signal

R‧‧‧ reference unit

R1a, R1b, R2a, R2b, Rma, Rmb‧‧‧ resistors

R _AP ‧‧‧anti-parallel resistance

Average value of R _AP '‧‧‧ anti-parallel resistance

RC‧‧‧Resistor control signal

RC[1]‧‧‧First resistor control signal

RC[1:m]‧‧‧ resistor control signal

READ‧‧‧ read command

R _P ‧‧‧Parallel resistance

R _P '‧‧‧Average of shunt resistors

R_REF‧‧‧ reference resistor

R _TH ‧‧‧threshold resistance

S200, S200a, S200b, S400, S400a, S400b, S420a, S420b, S440a, S440b, S600, S600a, S600b, S620a, S620b, S640a, S640b, S800, S800a, S800b, S820a, S820b, S840a, S840b, S860a, S860b‧‧‧ operation

SBL‧‧‧ short bit line

SLj‧‧‧ source line

SSL‧‧‧Short source line

T1, t2‧‧‧ time

VDD‧‧‧ positive supply voltage

V_RD‧‧‧Read voltage

V_REF‧‧‧reference voltage

VSS‧‧‧Negative power supply voltage source

WLi‧‧‧ character line

Embodiments of the inventive concept will be more clearly understood from the following detailed description of the embodiments of the invention. FIG. 1 is a block diagram showing a memory device and a controller according to an example embodiment. 2 is a timing diagram showing an example of communication between the memory device of FIG. 1 and a controller, according to an example embodiment. FIG. 3 is a diagram showing an example of a memory unit shown in FIG. 1 according to an example embodiment. 4 is a graph depicting a distribution of electrical resistance provided by the memory unit shown in FIG. 3, according to an example embodiment. 5A and 5B are block diagrams illustrating an example of the memory device of FIG. 1 according to an example embodiment. FIG. 6 is a circuit diagram illustrating an example of the current source circuit illustrated in FIG. 1 according to an example embodiment. 7A and 7B are circuit diagrams illustrating an example of a reference resistor circuit shown in FIG. 1 according to an example embodiment. FIG. 8 is a flow chart illustrating a method of controlling a reference unit, according to an example embodiment. 9A and 9B are flowcharts illustrating an example of operations S200 through S600 illustrated in FIG. 8 according to an example embodiment. FIG. 10 is a flow chart showing an example of operation S800 illustrated in FIG. 8 according to an example embodiment. FIG. 11 is a graph illustrating an example of an operation of determining a threshold resistance by operation S800a illustrated in FIG. 10, according to an example embodiment. FIG. 12 is a flow chart showing an example of operation S800b illustrated in FIG. 8 according to an example embodiment. FIG. 13 is a graph illustrating an example of an operation of determining a threshold resistance by operation S800b illustrated in FIG. 12, according to an example embodiment. FIG. 14 is a block diagram illustrating a memory device, according to an example embodiment. 15 is a block diagram of a system single wafer including a memory device, in accordance with an example embodiment.

Claims (10)

A method of controlling a reference unit in a resistive memory to identify values stored in a plurality of memory cells, the method comprising: writing a first value to the plurality of memory cells; providing monotony to the reference cells a reference current that is incremented or monotonically decremented; the plurality of memory cells are read when each of the reference currents is supplied to the reference unit; and the read reference current is determined based on a result of the reading. The method of claim 1, further comprising: setting a reference resistance of a reference resistor associated with the reference unit, wherein some of the reference resistors correspond to the reference through the reference resistor Some of the reference currents, and wherein the reference resistors are monotonically increasing or monotonically decreasing; and for reading each of the reference currents and the corresponding reference resistors in the reference resistors based on reading from the plurality of memory cells A set of results of the data is taken to determine the read reference resistance. The method of claim 1, wherein determining the read reference current comprises: estimating, based on the number of the first values from the read the result, corresponding to writing to the plurality A first distribution of electrical resistance of the first value of the memory cells. The method of claim 3, wherein the first value and the second value different from the first value respectively correspond to a low resistance and a high resistance of the plurality of memory cells, wherein the providing The reference current includes providing a monotonically increasing reference current, and wherein estimating the first distribution comprises: when the number of the read first values is equal to or greater than a first threshold number of successful read operations of the first value The threshold resistance as an average of the first distribution is estimated based on a threshold resistance corresponding to a reference current. The method of claim 4, further comprising: writing the second value to the plurality of memory cells, wherein providing the reference current further comprises providing a monotonically decreasing reference current, wherein the reading is determined Taking the reference current further includes estimating a second resistance corresponding to the second value written to the plurality of memory cells based on the number of the second values read in the read result The distribution, and wherein estimating the second distribution comprises: when the number of the read second values is equal to or greater than a second threshold number of successful read operations of the second value, based on a reference current The threshold resistance is used to estimate the threshold resistance as an average of the second distribution. The method of claim 5, wherein determining the read reference current comprises: determining the read reference current based on a median value of the first resistance and the second resistance, wherein a first standard resistance of the standard deviation of the distribution is added to the average of the first distribution to generate the first resistance, and wherein the subtraction is based on the average by subtracting the average from the second distribution The second standard resistance of the standard deviation of the two distributions produces the second resistance. The method of claim 4, wherein determining the read reference current further comprises: calculating the read reference current based on a predefined function having an average of the first distribution as a factor. The method of claim 1, further comprising: writing control data corresponding to the read reference current to the resistive memory. A method of controlling a reference unit in a resistive memory to identify a value stored in a plurality of memory units, the method comprising: writing a first value to the plurality of memory units; setting a correlation with the reference unit a monotonically increasing or monotonically decreasing resistance of the associated reference resistor, and a reference current is passed through the reference resistor; the plurality of memory cells are read for each of the resistors of the reference resistor; and based on the reading A collection of results to determine the read reference resistance. A resistive memory device configured to receive a reference adjustment signal, the resistive memory device comprising: a cell array comprising a memory unit and a reference unit, wherein the memory unit is coupled to a corresponding first source line and corresponding a first bit line, and wherein the reference cell is coupled to the second source line and the second bit line; the current source circuit is configured to respond to the read command to read current and variable reference current Provided to the memory unit and the reference unit via the first source line or the second source line, respectively; an amplifying circuit configured to detect the first source line connected to the memory unit And a voltage between the second source line connected to the reference unit; and a control circuit configured to control the current source circuit such that the read may be ignored in response to the reference adjustment signal The reference current is adjusted in the case of current.