CN109935273B

CN109935273B - Circuit for screening MTJ (magnetic tunnel junction) resistance

Info

Publication number: CN109935273B
Application number: CN201711376514.7A
Authority: CN
Inventors: 夏文斌; 戴瑾; 刘慧博
Original assignee: Shanghai Ciyu Information Technologies Co Ltd
Current assignee: Shanghai Ciyu Information Technologies Co Ltd
Priority date: 2017-12-19
Filing date: 2017-12-19
Publication date: 2020-11-10
Anticipated expiration: 2037-12-19
Also published as: CN109935273A

Abstract

The invention discloses a circuit for screening MTJ (magnetic tunnel junction) resistance, which comprises a signal control circuit, a parallel circuit, a current mirror and a reference resistance unit, wherein the signal control circuit is connected with the current mirror; the parallel circuit is at least a two-way circuit, the parallel circuit is a secondary circuit of the current mirror, the parallel circuit is connected with the signal control circuit, the circuit is opened and closed according to a control signal of the signal control circuit, and the parallel circuit is compared with the reference resistance unit, so that the proportion of the current mirror is controlled, and the MTJ resistance is screened. The invention can screen out the MTJ resistance too close to the reference resistance, and improve the reading accuracy of the MRAM. Meanwhile, the circuit can be well compatible with an original circuit without additional circuit design.

Description

Circuit for screening MTJ (magnetic tunnel junction) resistance

Technical Field

The invention belongs to the memory circuit design in the field of semiconductor chip memories, and particularly relates to a circuit for screening MTJ (magnetic tunnel junction) resistance.

Background

Magnetic Random Access Memory (MRAM) is an emerging non-volatile memory technology. It has high read-write speed and high integration and can be written repeatedly for unlimited times. MRAM can be read and written at random as SRAM/DRAM, and can permanently retain data after power failure as Flash memory

MRAM has very good economy and performance, and its unit capacity occupies silicon area which is much more advantageous than SRAM, and also more advantageous than NOR Flash which is often used in such chips, and much more advantageous than embedded NOR Flash. The MRAM read-write time delay is close to the best SRAM, and the power consumption is the best in various memories and storage technologies; MRAM is compatible with standard CMOS semiconductor technology, DRAM and Flash are incompatible with standard CMOS semiconductor technology; the MRAM can also be integrated with the logic circuit in one chip.

MRAM is based on MTJ (magnetic tunnel junction) architecture. Consisting of two layers of ferromagnetic material sandwiching a very thin layer of non-ferromagnetic insulating material, as shown in fig. 1: the lower layer of ferromagnetic material is a reference layer with a fixed magnetization direction and the upper layer of ferromagnetic material is a memory layer with a variable magnetization direction, which may be parallel or anti-parallel to the fixed magnetization layer. Due to quantum physical effects, current can pass through the middle tunnel barrier layer, but the resistance of the MTJ is related to the magnetization direction of the variable magnetization layer. The former case has a low resistance and the latter case has a high resistance.

The process of reading the MRAM is to measure the resistance of the MTJ. Writing MRAM uses a relatively new STT-MRAM technology to write through MTJs using a stronger current than reading. A bottom-up current places the variable magnetization layer in a direction parallel to the fixed layer, and a top-down circuit places it in an anti-parallel direction.

In MRAM circuits, MTJ resistance is measured, typically by using a current mirror to which a reference resistance is compared to obtain the MTJ state. The reference resistance may be the MTJ resistance or other resistances. When the two currents of the current mirror respectively pass through the reference resistor and the MTJ resistance, a voltage difference at a corresponding position is generated, and then the amplified signal is output to obtain stored data.

The resistance values of the high resistance state and the low resistance state of the MTJ in an ideal state are constant values, and if the average value of the resistance values is taken as the resistance value of the reference resistor, the two resistance states can be clearly distinguished. However, in actual production, due to the influence of various process conditions, the high resistance state and the low resistance state of the MTJ are normally distributed, as shown in fig. 2. This may cause some MTJ resistance values in low resistance states to be very close to the reference resistance value, even higher than the reference resistance value, and the final read value may have a large probability of error. A similar situation exists for the high resistance state. Moreover, the reference resistance itself is normally distributed, which also results in a certain probability of reading error.

Fig. 3 shows a schematic diagram of a MTJ resistance sensing circuit of the prior art, using a current mirror, where P0 is proportional to the channel Width of P1, such that Rref0 × Wp0/Wp1 in comparison to Rmtj, where Wp0 and Wp1 are the channel widths (Width) of P0 and P1, respectively.

If Rmtj < Rref, V1 becomes small, the stored data can be obtained by amplifying the V0, V1 signals. When the MTJ resistance is selected, if the MTJ resistance is too close to the reference resistance, which may result in a read error, the amplifier circuit cannot stably obtain the correct state even in a factory when the difference between V0 and V1 is small. If the low resistance of the MTJ is higher than the reference resistance and the high resistance is lower than the reference resistance, the written state is completely opposite to the read result.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a circuit for screening MTJ resistances, which performs pre-screening on MTJ resistances by equivalently changing reference resistances by controlling the current mirror ratio, and pre-excludes MTJ resistances having resistance values close to the reference resistances, thereby improving the read accuracy of MRAM.

In order to achieve the above object, the present invention provides a circuit for screening MTJ resistances, the screening circuit including a signal control circuit, a parallel circuit, a current mirror, and a reference resistance unit; the parallel circuit is at least a two-way circuit, the parallel circuit is a secondary circuit of the current mirror, the parallel circuit is connected with the signal control circuit, the circuit is opened and closed according to a control signal of the signal control circuit, the proportion of the current mirror is controlled, and the MTJ resistance is screened by comparing with the reference resistance unit.

Further, the parallel circuit is a three-way parallel circuit, wherein one way is a main way, the other two ways are auxiliary ways, the main way and the auxiliary way are opened to be in a normal working mode, the main way and the auxiliary way are opened to be in a screening low-resistance state, and only the main way is opened to be in a screening high-resistance state.

Further, the signal control circuit is composed of NMOS T2 and T3:

if only one path of the T2/T3 is opened, the parallel circuit is in a normal working mode;

if T2/T3 is all on or all off, the parallel circuit enters a screening mode:

if T2/T3 is completely opened, the parallel circuit enters a high-resistance state and low-resistance screening mode;

if T2/T3 is all closed, the parallel circuit enters a low-resistance state high-resistance screening mode.

Further, the reference resistance unit is formed by parallel multi-path resistances Ref0, … and RefN.

Further, Ref0, …, RefN of the reference resistance unit are MTJ resistances.

Furthermore, the screening circuit further comprises a Pre Charge circuit, and the Pre Charge circuit is used for Pre-charging the circuit for screening the MTJ resistance, so that the screening circuit can compare and output the MTJ resistance more quickly.

Further, the channel width of the PMOS of the multi-way parallel circuit is an exponential multiple of 2.

The screening circuit disclosed by the invention can screen out the MTJ resistance which is too close to the reference resistance, and the reading accuracy of the MRAM is improved. Meanwhile, the screening circuit can be well compatible with an original circuit without additional circuit design.

Drawings

FIG. 1 is a schematic diagram of a prior art MTJ.

FIG. 2 is a diagram illustrating the distribution of prior art MTJ resistance and reference resistance.

FIG. 3 is a prior art read MRAM resistance diagram.

FIG. 4 is a circuit diagram illustrating the MTJ resistance screening according to a preferred embodiment of the invention.

Detailed Description

The following detailed description of the preferred embodiments of the present invention is provided to enable those skilled in the art to more readily understand the advantages and features of the present invention, and to clearly and unequivocally define the scope of the present invention.

As shown in fig. 4, a circuit for screening MTJ resistance includes a signal control circuit 1, a parallel circuit 2, a current mirror 3, and a reference resistance unit 4.

The parallel circuit 2 is a secondary circuit of the current mirror 3 and is used for controlling the proportion of the current mirror 3; the parallel circuit 2 has at least two paths, which can be multiple paths, when the parallel circuit 2 is a three-path parallel circuit, one path is a main path, the other two paths are auxiliary paths, the main path and the auxiliary path are opened to be in a normal working mode, the main path and the auxiliary path are opened to be in a screening low-resistance state, and only the main path is opened to be in a screening high-resistance state.

The reference resistance unit is formed by parallel multi-path resistances Ref0, … and RefN, wherein Ref0, … and RefN can be MTJ resistances or other resistances. RrefX ═ Rref0// Rref1// …// Rref 1.

The signal control circuit 1 is used for controlling the opening and closing of the parallel circuit 2; the signal control circuit 1 is composed of NMOS T2, T3; if only one path of T2/T3 is opened, the parallel circuit 2 is in a normal working mode. Assuming that T2 is on and T3 is off, Rref ═ RrefX (Wp2+ Wp0)/Wp1, where Wp0, Wp1 and Wp2 are the channel widths (Width) of P0, P1 and P1, respectively. And comparing Rmtj with Rref to obtain stored data.

If T2/T3 are all on or all off, the parallel circuit 2 enters the screening mode, which is a preprocessing mode. Before entering a screening mode, writing a determined state into the MTJ resistance to be tested, then entering the screening mode, reading the MTJ resistance value, comparing the MTJ resistance value with the written state, if the MTJ resistance value is the same as the written state, indicating that the MTJ resistance value passes the screening, and if the MTJ resistance value is different from the written state, indicating that the MTJ resistance value does not pass the screening and needs to be removed.

T2/T3 are all turned on, and the parallel circuit 2 enters a high-resistance state low-resistance screening mode: namely, for the MTJ with high resistance state, the screening removal with low resistance state is performed. A high resistance state is written to the test MTJ. At this time, Rref' ═ RrefX (Wp3+ Wp2+ Wp0)/Wp1, where Wp0, Wp1, Wp2 and Wp3 are the channel widths (Width) of P0, P1, P2 and P3, respectively. Rref 'is greater than Rref at which time Rmtj requires a higher value to be greater than Rref' so that the circuit outputs the correct state. If the value of Rmtj is close to Rref 'or less than Ref', the output state of the circuit is a low resistance state which is inconsistent with the written state, the MTJ can be considered not to meet the requirement, and other circuits are needed to isolate the MTJ for bad bit.

When the T2/T3 is completely closed, the parallel circuit 2 enters a low-resistance state high-resistance screening mode.

The multi-path parallel circuit 2 can flexibly screen the MTJs with different resistance ranges, and the channel width of the PMOS of the multi-path control parallel circuit 2 can be exponentially multiplied by 2, that is, m is 1,2,4, and 8. The channel width of the PMOS tube can be adjusted in an equal proportion or in an unequal proportion.

In the embodiment of the present invention, a Pre Charge circuit 5 may be further included, the Pre Charge circuit 5 is connected between V0 and V1, and the screening circuit may perform comparison output more quickly in order to precharge the circuit for screening the MTJ resistance.

The foregoing detailed description of the preferred embodiments of the invention has been presented. It should be understood that numerous modifications and variations could be devised by those skilled in the art in light of the present teachings without departing from the inventive concepts. Therefore, the technical solutions available to those skilled in the art through logic analysis, reasoning and limited experiments based on the prior art according to the concept of the present invention should be within the scope of protection defined by the claims.

Claims

1. A circuit for screening MTJ resistance is characterized in that the screening circuit comprises a signal control circuit, a parallel circuit, a current mirror and a reference resistance unit; the parallel circuit is at least a two-way circuit, the parallel circuit is a secondary circuit of the current mirror, the parallel circuit is connected with the signal control circuit, the circuit is opened and closed according to a control signal of the signal control circuit, the proportion of the current mirror is controlled, and the MTJ resistance is screened by comparing with the reference resistance unit.

2. The circuit for screening MTJ resistance of claim 1 wherein the parallel circuit is a three-way parallel circuit, one of which is a main circuit and the other two of which are auxiliary circuits, and wherein turning on the main circuit and one of the auxiliary circuits is a normal operating mode, turning on the main circuit and two of the auxiliary circuits is a screening low resistance state, and turning on only the main circuit is a screening high resistance state.

3. The circuit for screening MTJ resistance of claim 2, wherein the signal control circuit is comprised of NMOS T2 and T3:

if T2/T3 is all on or all off, the parallel circuit enters a screening mode:

if T2/T3 is completely closed, the parallel selection circuit enters a low-resistance state high-resistance screening mode.

4. The circuit for screening MTJ resistances according to claim 1, wherein the reference resistance unit is formed by parallel connection of multiple resistances Ref0, …, RefN.

5. The circuit for screening MTJ resistance of claim 4, in which Ref0, …, RefN of the reference resistance cell is an MTJ resistance.

6. The circuit for screening MTJ resistances according to claim 1, wherein the screening circuit further comprises a Pre Charge circuit for precharging the circuit for screening MTJ resistances to make the screening circuit perform comparison output faster.

7. The circuit for screening MTJ resistances of any of claims 1 to 6, where the channel width of the PMOS of the parallel circuit is 2ⁿWherein n is a non-negative integer.