KR20170026114A - 트랜잭션 기반 하이브리드 메모리 모듈 - Google Patents
트랜잭션 기반 하이브리드 메모리 모듈 Download PDFInfo
- Publication number
- KR20170026114A KR20170026114A KR1020160085591A KR20160085591A KR20170026114A KR 20170026114 A KR20170026114 A KR 20170026114A KR 1020160085591 A KR1020160085591 A KR 1020160085591A KR 20160085591 A KR20160085591 A KR 20160085591A KR 20170026114 A KR20170026114 A KR 20170026114A
- Authority
- KR
- South Korea
- Prior art keywords
- memory
- dram
- cache
- controller
- flash
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
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Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0253—Garbage collection, i.e. reclamation of unreferenced memory
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0656—Data buffering arrangements
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7211—Wear leveling
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201562210939P | 2015-08-27 | 2015-08-27 | |
| US62/210,939 | 2015-08-27 | ||
| US14/947,145 US20170060434A1 (en) | 2015-08-27 | 2015-11-20 | Transaction-based hybrid memory module |
| US14/947,145 | 2015-11-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20170026114A true KR20170026114A (ko) | 2017-03-08 |
Family
ID=58104058
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020160085591A Ceased KR20170026114A (ko) | 2015-08-27 | 2016-07-06 | 트랜잭션 기반 하이브리드 메모리 모듈 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US20170060434A1 (enExample) |
| JP (1) | JP2017045457A (enExample) |
| KR (1) | KR20170026114A (enExample) |
| CN (1) | CN106484628A (enExample) |
| TW (1) | TW201710910A (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102560109B1 (ko) * | 2023-03-20 | 2023-07-27 | 메티스엑스 주식회사 | 바이트 어드레서블 장치 및 이를 포함하는 컴퓨팅 시스템 |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10482013B2 (en) * | 2014-09-30 | 2019-11-19 | Hewlett Packard Enterprise Development Lp | Eliding memory page writes upon eviction after page modification |
| US10387315B2 (en) * | 2016-01-25 | 2019-08-20 | Advanced Micro Devices, Inc. | Region migration cache |
| US9830086B2 (en) * | 2016-03-03 | 2017-11-28 | Samsung Electronics Co., Ltd. | Hybrid memory controller for arbitrating access to volatile and non-volatile memories in a hybrid memory group |
| US11080185B2 (en) | 2017-06-15 | 2021-08-03 | Rambus Inc. | Hybrid memory module |
| KR102319189B1 (ko) | 2017-06-21 | 2021-10-28 | 삼성전자주식회사 | 스토리지 장치, 이를 포함하는 스토리지 시스템 및 스토리지 장치의 동작 방법 |
| CN107844436B (zh) * | 2017-11-02 | 2021-07-16 | 郑州云海信息技术有限公司 | 一种缓存中脏数据的组织管理方法、系统及存储系统 |
| KR102101622B1 (ko) * | 2017-12-06 | 2020-04-17 | 주식회사 멤레이 | 메모리 제어 장치 및 이를 포함하는 컴퓨팅 디바이스 |
| US10929291B2 (en) * | 2017-12-06 | 2021-02-23 | MemRay Corporation | Memory controlling device and computing device including the same |
| CN108052296B (zh) * | 2017-12-30 | 2021-02-19 | 惠龙易通国际物流股份有限公司 | 一种数据读取方法、设备及计算机存储介质 |
| US10990463B2 (en) | 2018-03-27 | 2021-04-27 | Samsung Electronics Co., Ltd. | Semiconductor memory module and memory system including the same |
| KR102538679B1 (ko) | 2018-04-06 | 2023-06-02 | 삼성전자주식회사 | 메모리 시스템 및 메모리 시스템의 동작 방법 |
| US10977198B2 (en) * | 2018-09-12 | 2021-04-13 | Micron Technology, Inc. | Hybrid memory system interface |
| CN111399750B (zh) * | 2019-01-03 | 2023-05-26 | 慧荣科技股份有限公司 | 闪存数据写入方法及计算机可读取存储介质 |
| US11199991B2 (en) | 2019-01-03 | 2021-12-14 | Silicon Motion, Inc. | Method and apparatus for controlling different types of storage units |
| CN109960471B (zh) * | 2019-03-29 | 2022-06-03 | 深圳大学 | 数据存储方法、装置、设备以及存储介质 |
| KR20220086785A (ko) * | 2020-12-16 | 2022-06-24 | 삼성전자주식회사 | 트랜잭션 가속기의 동작 방법. 트랜잭션 가속기를 포함하는 컴퓨팅 장치의 동작 방법, 그리고 트랜잭션 가속기를 포함하는 컴퓨팅 장치 |
| US12656954B2 (en) * | 2023-03-21 | 2026-06-16 | Micron Technology, Inc. | Compute express link DRAM + NAND system solution |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101085406B1 (ko) * | 2004-02-16 | 2011-11-21 | 삼성전자주식회사 | 불 휘발성 메모리를 제어하기 위한 컨트롤러 |
| JP2006127110A (ja) * | 2004-10-28 | 2006-05-18 | Canon Inc | Dramメモリアクセス制御手法、および手段 |
| US8397013B1 (en) * | 2006-10-05 | 2013-03-12 | Google Inc. | Hybrid memory module |
| US20070136523A1 (en) * | 2005-12-08 | 2007-06-14 | Bonella Randy M | Advanced dynamic disk memory module special operations |
| US7716411B2 (en) * | 2006-06-07 | 2010-05-11 | Microsoft Corporation | Hybrid memory device with single interface |
| US7730268B2 (en) * | 2006-08-18 | 2010-06-01 | Cypress Semiconductor Corporation | Multiprocessor system having an input/output (I/O) bridge circuit for transferring data between volatile and non-volatile memory |
| US7554855B2 (en) * | 2006-12-20 | 2009-06-30 | Mosaid Technologies Incorporated | Hybrid solid-state memory system having volatile and non-volatile memory |
| JP2011118469A (ja) * | 2009-11-30 | 2011-06-16 | Toshiba Corp | メモリ管理装置およびメモリ管理方法 |
| US8612809B2 (en) * | 2009-12-31 | 2013-12-17 | Intel Corporation | Systems, methods, and apparatuses for stacked memory |
| JP2011198133A (ja) * | 2010-03-19 | 2011-10-06 | Toshiba Corp | メモリシステムおよびコントローラ |
| CN102289414A (zh) * | 2010-06-17 | 2011-12-21 | 中兴通讯股份有限公司 | 内存数据保护装置及方法 |
| JP2012033047A (ja) * | 2010-07-30 | 2012-02-16 | Toshiba Corp | 情報処理装置、メモリ管理装置、メモリ管理方法、及びプログラム |
| WO2013048493A1 (en) * | 2011-09-30 | 2013-04-04 | Intel Corporation | Memory channel that supports near memory and far memory access |
| US9063864B2 (en) * | 2012-07-16 | 2015-06-23 | Hewlett-Packard Development Company, L.P. | Storing data in presistent hybrid memory |
| US9367262B2 (en) * | 2013-02-26 | 2016-06-14 | Seagate Technology Llc | Assigning a weighting to host quality of service indicators |
| CN104346293B (zh) * | 2013-07-25 | 2017-10-24 | 华为技术有限公司 | 混合内存的数据访问方法、模块、处理器及终端设备 |
-
2015
- 2015-11-20 US US14/947,145 patent/US20170060434A1/en not_active Abandoned
-
2016
- 2016-05-23 TW TW105115915A patent/TW201710910A/zh unknown
- 2016-07-06 KR KR1020160085591A patent/KR20170026114A/ko not_active Ceased
- 2016-08-23 JP JP2016162674A patent/JP2017045457A/ja active Pending
- 2016-08-26 CN CN201610738928.9A patent/CN106484628A/zh active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102560109B1 (ko) * | 2023-03-20 | 2023-07-27 | 메티스엑스 주식회사 | 바이트 어드레서블 장치 및 이를 포함하는 컴퓨팅 시스템 |
| US11940910B1 (en) | 2023-03-20 | 2024-03-26 | Metisx Co., Ltd. | Byte-addressable device and computing system including same |
| US12277057B2 (en) | 2023-03-20 | 2025-04-15 | Xcena Inc. | Byte-addressable device and computing system including same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106484628A (zh) | 2017-03-08 |
| US20170060434A1 (en) | 2017-03-02 |
| JP2017045457A (ja) | 2017-03-02 |
| TW201710910A (zh) | 2017-03-16 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
St.27 status event code: A-0-1-A10-A12-nap-PA0109 |
|
| PG1501 | Laying open of application |
St.27 status event code: A-1-1-Q10-Q12-nap-PG1501 |
|
| A201 | Request for examination | ||
| PA0201 | Request for examination |
St.27 status event code: A-1-2-D10-D11-exm-PA0201 |
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| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
St.27 status event code: A-1-2-D10-D21-exm-PE0902 |
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| E601 | Decision to refuse application | ||
| PE0601 | Decision on rejection of patent |
St.27 status event code: N-2-6-B10-B15-exm-PE0601 |
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| R18 | Changes to party contact information recorded |
Free format text: ST27 STATUS EVENT CODE: A-3-3-R10-R18-OTH-X000 (AS PROVIDED BY THE NATIONAL OFFICE) |
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| R18-X000 | Changes to party contact information recorded |
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| R18 | Changes to party contact information recorded |
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| R18-X000 | Changes to party contact information recorded |
St.27 status event code: A-3-3-R10-R18-oth-X000 |
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| R18 | Changes to party contact information recorded |
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