TW201710910A - 交易式混合記憶體模組及其操作方法 - Google Patents

交易式混合記憶體模組及其操作方法 Download PDF

Info

Publication number
TW201710910A
TW201710910A TW105115915A TW105115915A TW201710910A TW 201710910 A TW201710910 A TW 201710910A TW 105115915 A TW105115915 A TW 105115915A TW 105115915 A TW105115915 A TW 105115915A TW 201710910 A TW201710910 A TW 201710910A
Authority
TW
Taiwan
Prior art keywords
memory
dram
cache
controller
flash
Prior art date
Application number
TW105115915A
Other languages
English (en)
Chinese (zh)
Inventor
張牧天
鄭宏忠
牛迪民
Original Assignee
三星電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三星電子股份有限公司 filed Critical 三星電子股份有限公司
Publication of TW201710910A publication Critical patent/TW201710910A/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0253—Garbage collection, i.e. reclamation of unreferenced memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7211—Wear leveling

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
TW105115915A 2015-08-27 2016-05-23 交易式混合記憶體模組及其操作方法 TW201710910A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201562210939P 2015-08-27 2015-08-27
US14/947,145 US20170060434A1 (en) 2015-08-27 2015-11-20 Transaction-based hybrid memory module

Publications (1)

Publication Number Publication Date
TW201710910A true TW201710910A (zh) 2017-03-16

Family

ID=58104058

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105115915A TW201710910A (zh) 2015-08-27 2016-05-23 交易式混合記憶體模組及其操作方法

Country Status (5)

Country Link
US (1) US20170060434A1 (enExample)
JP (1) JP2017045457A (enExample)
KR (1) KR20170026114A (enExample)
CN (1) CN106484628A (enExample)
TW (1) TW201710910A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI741357B (zh) * 2018-09-12 2021-10-01 美商美光科技公司 用於記憶體操作之運算系統及其操作方法

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10482013B2 (en) * 2014-09-30 2019-11-19 Hewlett Packard Enterprise Development Lp Eliding memory page writes upon eviction after page modification
US10387315B2 (en) * 2016-01-25 2019-08-20 Advanced Micro Devices, Inc. Region migration cache
US9830086B2 (en) * 2016-03-03 2017-11-28 Samsung Electronics Co., Ltd. Hybrid memory controller for arbitrating access to volatile and non-volatile memories in a hybrid memory group
US11080185B2 (en) 2017-06-15 2021-08-03 Rambus Inc. Hybrid memory module
KR102319189B1 (ko) 2017-06-21 2021-10-28 삼성전자주식회사 스토리지 장치, 이를 포함하는 스토리지 시스템 및 스토리지 장치의 동작 방법
CN107844436B (zh) * 2017-11-02 2021-07-16 郑州云海信息技术有限公司 一种缓存中脏数据的组织管理方法、系统及存储系统
KR102101622B1 (ko) * 2017-12-06 2020-04-17 주식회사 멤레이 메모리 제어 장치 및 이를 포함하는 컴퓨팅 디바이스
US10929291B2 (en) * 2017-12-06 2021-02-23 MemRay Corporation Memory controlling device and computing device including the same
CN108052296B (zh) * 2017-12-30 2021-02-19 惠龙易通国际物流股份有限公司 一种数据读取方法、设备及计算机存储介质
US10990463B2 (en) 2018-03-27 2021-04-27 Samsung Electronics Co., Ltd. Semiconductor memory module and memory system including the same
KR102538679B1 (ko) 2018-04-06 2023-06-02 삼성전자주식회사 메모리 시스템 및 메모리 시스템의 동작 방법
CN111399750B (zh) * 2019-01-03 2023-05-26 慧荣科技股份有限公司 闪存数据写入方法及计算机可读取存储介质
US11199991B2 (en) 2019-01-03 2021-12-14 Silicon Motion, Inc. Method and apparatus for controlling different types of storage units
CN109960471B (zh) * 2019-03-29 2022-06-03 深圳大学 数据存储方法、装置、设备以及存储介质
KR20220086785A (ko) * 2020-12-16 2022-06-24 삼성전자주식회사 트랜잭션 가속기의 동작 방법. 트랜잭션 가속기를 포함하는 컴퓨팅 장치의 동작 방법, 그리고 트랜잭션 가속기를 포함하는 컴퓨팅 장치
KR102560109B1 (ko) 2023-03-20 2023-07-27 메티스엑스 주식회사 바이트 어드레서블 장치 및 이를 포함하는 컴퓨팅 시스템
US12656954B2 (en) * 2023-03-21 2026-06-16 Micron Technology, Inc. Compute express link DRAM + NAND system solution

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101085406B1 (ko) * 2004-02-16 2011-11-21 삼성전자주식회사 불 휘발성 메모리를 제어하기 위한 컨트롤러
JP2006127110A (ja) * 2004-10-28 2006-05-18 Canon Inc Ｄｒａｍメモリアクセス制御手法、および手段
US8397013B1 (en) * 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US20070136523A1 (en) * 2005-12-08 2007-06-14 Bonella Randy M Advanced dynamic disk memory module special operations
US7716411B2 (en) * 2006-06-07 2010-05-11 Microsoft Corporation Hybrid memory device with single interface
US7730268B2 (en) * 2006-08-18 2010-06-01 Cypress Semiconductor Corporation Multiprocessor system having an input/output (I/O) bridge circuit for transferring data between volatile and non-volatile memory
US7554855B2 (en) * 2006-12-20 2009-06-30 Mosaid Technologies Incorporated Hybrid solid-state memory system having volatile and non-volatile memory
JP2011118469A (ja) * 2009-11-30 2011-06-16 Toshiba Corp メモリ管理装置およびメモリ管理方法
US8612809B2 (en) * 2009-12-31 2013-12-17 Intel Corporation Systems, methods, and apparatuses for stacked memory
JP2011198133A (ja) * 2010-03-19 2011-10-06 Toshiba Corp メモリシステムおよびコントローラ
CN102289414A (zh) * 2010-06-17 2011-12-21 中兴通讯股份有限公司 内存数据保护装置及方法
JP2012033047A (ja) * 2010-07-30 2012-02-16 Toshiba Corp 情報処理装置、メモリ管理装置、メモリ管理方法、及びプログラム
WO2013048493A1 (en) * 2011-09-30 2013-04-04 Intel Corporation Memory channel that supports near memory and far memory access
US9063864B2 (en) * 2012-07-16 2015-06-23 Hewlett-Packard Development Company, L.P. Storing data in presistent hybrid memory
US9367262B2 (en) * 2013-02-26 2016-06-14 Seagate Technology Llc Assigning a weighting to host quality of service indicators
CN104346293B (zh) * 2013-07-25 2017-10-24 华为技术有限公司 混合内存的数据访问方法、模块、处理器及终端设备

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI741357B (zh) * 2018-09-12 2021-10-01 美商美光科技公司 用於記憶體操作之運算系統及其操作方法

Also Published As

Publication number Publication date
CN106484628A (zh) 2017-03-08
KR20170026114A (ko) 2017-03-08
US20170060434A1 (en) 2017-03-02
JP2017045457A (ja) 2017-03-02

Similar Documents

Publication Publication Date Title
US20170060434A1 (en) Transaction-based hybrid memory module
KR101636634B1 (ko) 프로세서로부터 메모리 서브시스템으로 데이터를 지능적으로 플러싱하기 위한 시스템 및 방법
JP5580894B2 (ja) Ｔｌｂプリフェッチング
US10628326B2 (en) Logical to physical mapping
US11604735B1 (en) Host memory buffer (HMB) random cache access
US10552045B2 (en) Storage operation queue
US20130275699A1 (en) Special memory access path with segment-offset addressing
US11733932B2 (en) Data management on memory modules
US11016905B1 (en) Storage class memory access
US11836092B2 (en) Non-volatile storage controller with partial logical-to-physical (L2P) address translation table
TW202238395A (zh) 二階主要記憶體階層式管理技術
US11561902B2 (en) Cache operations in a hybrid dual in-line memory module
US11573743B2 (en) Pointer dereferencing within memory sub-system
EP3757800A1 (en) Memory system, computing system, and methods thereof
CN114253461B (zh) 混合通道存储设备
EP4328755B1 (en) Systems, methods, and apparatus for accessing data in versions of memory pages
US12449974B2 (en) Memory compression with improved lookup table scheme
JP2007048296A (ja) 複数のアドレス・キャッシュ・エントリーを無効にする方法、装置およびシステム
US20150026394A1 (en) Memory system and method of operating the same