KR20160129221A - Display device - Google Patents

Abstract

An embodiment of the present invention relates to a display device capable of reducing the number of input and output pins in a timing controller. According to one embodiment of the present invention, the display device includes a timing controller for receiving driving timing information through a serial clock (SCL) signal and a serial data (SDA) signal. The timing controller receives the SCL signal through a first pin and receives the SDA signal through a second pin, generates first and second timing control signals based on the SCL signal and the SDA signal, and outputs the first timing control signal through the first pin and outputs the second timing control signal through the second pin.

Description

Display device {DISPLAY DEVICE}

An embodiment of the present invention relates to a display device.

2. Description of the Related Art [0002] As an information-oriented society develops, there have been various demands for a display device for displaying images. Recently, a liquid crystal display (LCD), a plasma display panel (PDP) Various display devices such as an OLED (Organic Light Emitting Diode) are being utilized.

The display device includes a display panel, a gate driver, a data driver, and a timing controller. The display panel includes a plurality of pixels formed at intersections of the data lines, the gate lines, the data lines and the gate lines, and supplied with the data voltages of the data lines when the gate signals are supplied to the gate lines. The pixels emit light at a predetermined brightness according to the data voltages. The gate driver supplies gate signals to the gate lines. The data driver includes a source driver IC (hereinafter referred to as " IC ") that supplies data voltages to the data lines. The timing controller controls the operation timing of the gate driver and the data driver.

When the power of the display device is turned on, the timing controller receives information stored in the EEPROM by performing I ² C communication with an EEPROM (electrically erasable programmable read-only memory) through an SCL (serial clock) signal and an SDA . The timing controller outputs control signals for controlling the gate driver and the data driver based on the information input from the EEPROM.

In recent years, since a high-resolution display device such as UHD (ultra high definition, 3840 × 2160) has been introduced, the number of control signals of the timing controller is also increasing. In this case, since the number of input / output pins of the timing controller increases, there is a problem that the cost of the timing controller increases due to an increase in size of the timing controller.

Embodiments of the present invention provide a display device capable of reducing the number of input / output pins of a timing controller.

A display device according to an embodiment of the present invention includes a timing controller that receives driving timing information through an SCL signal and an SDA signal. Wherein the timing controller receives the SCL signal through a first pin and receives the SDA signal through a second pin, generates first and second timing control signals based on the SCL signal and the SDA signal, And outputs the first timing control signal through the first pin and the second timing control signal through the second pin.

A display device according to another embodiment of the present invention includes a display panel, a gate driver, a data driver, a memory, and a timing controller. The display panel includes gate lines, data lines, and pixels provided in an intersection region of the gate lines and the data lines. The gate driver supplies gate signals to the gate lines. The data driver supplies data voltages to the data lines. The memory stores a gate control signal for driving the gate driver and timing information of a data control signal for driving the data driver. Wherein the timing controller receives the timing information from the memory via the first pin and receives the SDA signal via the second pin, and controls the gate control signal and the data control signal based on the SCL signal and the SDA signal, And outputs a first timing control signal of the gate control signal and the data control signal through the first pin and a second timing control signal of the gate control signal and the data control signal to the second pin Lt; / RTI >

The exemplary embodiment of the present invention is characterized by receiving the SCL signal and the SDA signal through the first and second pins during the first period and outputting the first and second timing control signals generated according to the SCL signal and the SDA signal during the first period, And second pins. As a result, the embodiment of the present invention not only receives the SCL signal and the SDA signal using the first and second pins, but also outputs the first and second timing control signals, The pins used for outputting the control signals can be deleted. In other words, the embodiment of the present invention can reduce the number of input / output pins of the timing controller, thereby preventing a problem that the cost of the timing controller is increased due to an increase in the size of the timing controller in the high-resolution display device.

1 is an exemplary view showing a display device according to an embodiment of the present invention.
FIG. 2 is an exemplary view showing a lower substrate, source drive ICs, source soft films, a source circuit board, a control circuit board, and a timing controller, an EEPROM, and a power supply of a display device according to an embodiment of the present invention.
FIG. 3 is an exemplary view showing the pixel of FIG. 1; FIG.
Figure 4 is another exemplary view showing the pixel of Figure 1;
5 is a block diagram showing a memory, a timing controller, and a level shifter.
FIG. 6 is a detailed block diagram of a timing controller according to a first embodiment of the present invention; FIG.
7 is a flowchart showing an output of an input / output control signal of an input / output control unit of a timing controller according to an embodiment of the present invention.
FIG. 8 is a waveform diagram showing an example of signals input / output through the first and second pins of the timing controller of FIG. 6; FIG.
9 is a detailed block diagram of a timing controller according to a second embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

Where the terms "comprises," "having," "consisting of," and the like are used in this specification, other portions may be added as long as "only" is not used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the case of a description of a temporal relationship, for example, if the temporal relationship is described by 'after', 'after', 'after', 'before', etc., May not be continuous unless they are not used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

The terms "X-axis direction "," Y-axis direction ", and "Z-axis direction" should not be construed solely by the geometric relationship in which the relationship between them is vertical, It may mean having directionality.

It should be understood that the term "at least one" includes all possible combinations from one or more related items. For example, the meaning of "at least one of the first item, the second item and the third item" means not only the first item, the second item or the third item, but also the second item and the second item among the first item, May refer to any combination of items that may be presented from more than one.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other, partially or wholly, technically various interlocking and driving, and that the embodiments may be practiced independently of each other, It is possible.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an exemplary view showing a display device according to an embodiment of the present invention. 2 is an exemplary view showing a lower substrate, source drive ICs, source flexible films, a source circuit board, a control circuit board, and a timing controller, an EEPROM, and a power supply unit of a display device according to an embodiment of the present invention.

The display device according to the embodiment of the present invention may include any display device for supplying data voltages to the pixels by line scanning which supplies the gate signals to the gate lines G1 to Gn. For example, the display device according to an exemplary embodiment of the present invention may be applied to a liquid crystal display (LCD), an organic light emitting display, a field emission display, an electrophoresis display).

1 and 2, a display device according to an embodiment of the present invention includes a display panel 10, a gate driver 11, a data driver 20, a timing controller 30, a memory 40, And a shifter 50.

The display panel 10 includes an upper substrate and a lower substrate. A display area DA including data lines (D1 to Dm, m is a positive integer of 2 or more), gate lines (G1 to Gn, n is a positive integer of 2 or more), and pixels (P) . The pixel P may be connected to any one of the data lines D1 to Dm and the gate lines G1 to Gn. Accordingly, the pixel P receives the data voltage of the data line when the gate signal is supplied to the gate line, and emits light at a predetermined brightness according to the supplied data voltage.

When the display device is implemented as a liquid crystal display device, each of the pixels P may include a transistor T, a pixel electrode 11, and a storage capacitor Cst as shown in FIG. The transistor T is connected to the gate of the gate line Gk at a jth (j is a positive integer satisfying 1? J? M) in response to the gate signal of the k-th gate line Gk (k is a positive integer satisfying 1? And supplies the data voltage of the data line Dj to the pixel electrode 11. [ Each of the pixels P drives the liquid crystal of the liquid crystal layer 13 by an electric field generated by a potential difference between the data voltage supplied to the pixel electrode 11 and the common voltage supplied to the common electrode 12 The amount of light transmitted from the backlight unit can be adjusted. The common electrode 12 receives a common voltage from the common voltage line VcomL and the backlight unit is disposed below the display panel 10 to irradiate the display panel 10 with uniform light. The storage capacitor Cst is provided between the pixel electrode 11 and the common electrode 12 to keep the voltage difference between the pixel electrode 11 and the common electrode 12 constant.

3, each of the pixels P includes an organic light emitting diode (OLED), a scan transistor ST, a driving transistor DT, and a storage capacitor Cst can do. The scan transistor ST supplies the data voltage of the jth data line Dj to the gate electrode of the driving transistor DT in response to the gate signal of the kth gate line Gk. The driving transistor DT controls the driving current flowing from the high potential voltage line VDDL to the organic light emitting diode OLED according to the data voltage supplied to the gate electrode. The organic light emitting diode OLED is provided between the driving transistor DT and the low potential voltage line VSSL and emits light at a predetermined brightness according to the driving current. The storage capacitor Cst may be provided between the gate electrode of the driving transistor DT and the high potential voltage line VDDL in order to keep the voltage of the gate electrode of the driving transistor DT constant.

The gate driver 11 is connected to the gate lines G1 to Gn to supply gate signals. Specifically, the gate driving unit 11 receives the gate control signal GCS ', generates gate signals according to the gate control signal GCS, and supplies the gate signals to the gate lines G1 to Gn.

The display panel 10 may be divided into a display area DA and a non-display area NDA. The display area DA is an area where pixels P are provided to display an image. The non-display area NDA is an area provided in the periphery of the display area DA, and is an area where no image is displayed.

The gate driver 11 may be provided in the non-display area NDA by a gate driver in panel (GIP) scheme. 1, the gate driver 11 is provided on one side of the display area DA, but the present invention is not limited thereto. For example, the gate driver 11 may be provided on both sides of the display area DA.

Alternatively, the gate driver 11 may include a plurality of gate drive integrated circuits (hereinafter referred to as "ICs "), and the gate drive ICs may be mounted on the gate flexible films. Each of the gate flexible films may be a tape carrier package or a chip on film. The gate flexible films can be attached to the non-display area NDA of the display panel 10 by a TAB (tape automated bonding) method using an anisotropic conductive film, 0.0 > G1-Gn. ≪ / RTI >

The data driver 20 is connected to the data lines D1 to Dm. The data driver 20 receives the digital video data DATA and the data control signal DCS from the timing controller 30 and converts the digital video data DATA into analog data voltages in accordance with the data control signal DCS do. The data driver 20 supplies the analog data voltages to the data lines D1 to Dm. The data driver 20 may include one source driver IC or a plurality of source driver ICs.

Each of the source drive ICs 21 may be made of a drive chip. Each of the source drive ICs 21 may be mounted on the source flexible film 60. Each of the source flexible films 60 may be embodied as a tape carrier package or a chip-on film and may be bent or bent. Each of the source flexible films 60 may be attached to the non-display area of the display panel 10 in a TAB manner using an anisotropic conductive film, whereby the source drive ICs 21 are connected to the data lines D1 to Dm, Lt; / RTI >

In addition, the source flexible films 60 may be attached on a source printed circuit board 70. FIG. The source printed circuit boards 70 may be flexible printed circuit boards that can be bent or bent. The source printed circuit boards 70 may be provided in one or more than one.

The timing controller 30 receives video data (DATA) and timing signals (TS) from an external system board (not shown). The timing signals may include a vertical sync signal, a horizontal sync signal, a data enable signal, and a dot clock. The timing controller 30 receives driving timing information from the memory 40 via a serial clock (SCL) signal (SCL) and a serial data (SDA) signal (SDA).

The timing controller 30 controls the operation timing of the data driver 20 and the gate control signal GCS for controlling the operation timing of the gate driver 11 based on the timing signals TS and the drive timing information And generates a data control signal DCS.

When the gate driver 11 is provided in the GIP scheme, the gate clock signals supplied to the gate driver 11 are generated in the level shifter 50 using an on-clock signal and an off-clock signal, And may be generated using an on-clock signal and an off-clock signal.

When the gate clock signals are generated in the level shifter 50, the gate control signal GCS may include a start signal, an on-clock signal, and an off-clock signal. The start signal is a signal for controlling the start of the output of the gate driver 11. The on-clock signal and the off-clock signal are clock signals for generating gate clock signals supplied to the gate driver 11. [ For example, the gate clock signal may be routed in synchronization with the rising edge or the falling edge of the on clock signal, and the gate clock signal may be polled in synchronization with the rising edge or the falling edge of the off clock signal. The rising edge means a period in which the on-clock signal and the off-clock signal rise from the first logic voltage to the second logic voltage. The falling edge means the period during which the on-clock signal and the off-clock signal fall from the second logic voltage to the first logic voltage.

When the gate clock signals are generated in the timing controller 30, the gate control signal GCS may include a start signal and a gate clock signal. In this case, the gate clock signals are generated in the timing controller using an on-clock signal and an off-clock signal.

Alternatively, when the gate driver 11 is provided in the TAB scheme, the gate control signal GCS may include a gate start signal, gate shift clocks, and a gate enable signal.

The timing controller 30 supplies the video data DATA and the data control signal DCS to the data driver 20. The timing controller 30 supplies the gate control signal GCS to the level shifter 50.

The memory 40 stores driving timing information for the timing controller 30 to drive the display device such as the information necessary for generating the gate control signal GCS and the data control signal DCS. When the display device is powered on, the memory 40 performs I ² C communication with an electrically erasable programmable read-only memory (EEPROM) through an SCL (serial clock) signal and an SDA (serial data) To the controller (30). Thus, the timing controller 30 can generate the gate control signal GCS, the data control signal DCS, and the like in accordance with the driving timing information. The memory 40 may be an electrically erasable programmable read-only memory (EEPROM).

The level shifter 50 generates the gate clock signals using the on-clock signal and the off-clock signal when the gate control signal GCS includes the start signal, the on-clock signal, and the off-clock signal. The level shifter 50 also changes the swing widths of the start signal and the gate clock signals from the first logic voltage and the second logic voltage to the gate low voltage and the gate high voltage.

When the gate control signal GCS includes the start signal and the gate clock signals or includes the gate start signal, the gate shift clocks, and the gate output enable signal, the level shifter 50 outputs the gate control signal GCS, The width is changed from the first logic voltage and the second logic voltage to the gate low voltage and the gate high voltage.

When the timing controller 30 generates the gate control signal GCS swinging at the gate low voltage and the gate high voltage, there is a problem that the power consumption increases. Therefore, the timing controller 30 generates the gate control signal GCS swinging between the first logic voltage and the second logic voltage having a small swing width, and uses the level shifter 50 to control the gate control signal GCS Change the swing width.

The level shifter 50 supplies the gate drive unit 11 with the gate control signal GCS 'whose swing width is changed.

The timing controller 30, the memory 40 and the level shifter 50 may be mounted on the control printed circuit board 90 as shown in FIG. The control printed circuit board 90 and the source printed circuit board 70 may be connected through a flexible circuit board 80 such as a flexible flat cable (FFC) or a flexible printed circuit (FPC).

5 is a block diagram showing a memory, a timing controller, and a level shifter. 5, the first and second pins TP1 and TP2 of the timing controller 30 and the first and second pins MP1 and MP2 of the memory 40 connected to the first and second pins TP1 and TP2 and the level shifter The first and second pins LP1 and LP2 are shown.

5, the first pin TP1 of the timing controller 30 is connected to the first pin MP1 of the memory 40 and the first pin LP1 of the level shifter 50. The SCL signal SCL transmitted from the first pin MP1 of the memory 40 is input to the first pin TP1 of the timing controller 30. [ The second pin TP2 of the timing controller 30 is connected to the second pin MP2 of the memory 40 and the second pin LP2 of the level shifter 50. [ The SDA signal SDA transmitted from the second pin MP2 of the memory 40 is input to the second pin TP2 of the timing controller 30. [

The timing controller 30 receives driving timing information of the memory 40 through the SCL signal SCL and the SDA signal SDA input to the first and second pins TP1 and TP2. The timing controller 30 may generate driving timing control signals such as a gate control signal GCS and a data control signal DCS according to driving timing information.

The SCL signal SCL is also input to the first pin LP1 of the level shifter 50 because the first pin LP1 of the level shifter 50 is also connected to the first pin MP1 of the memory 40 do. Since the second pin LP2 of the level shifter 50 is also connected to the second pin MP2 of the memory 40, the SDA signal SDA is also input to the second pin LP2 of the level shifter 50 do. However, since the SCL signal SCL and the SDA signal SDA are signals that are not related to the operation of the level shifter 50, the level shifter 50 operates even if the SCL signal SCL and the SDA signal SDA are input Do not.

And outputs the first timing control signal, which is one of the driving timing control signals, to the first pin LP1 of the level shifter 50 through the first pin TP1 of the timing controller 30. [ And outputs the second timing control signal, which is another one of the drive timing control signals, to the second pin LP2 of the level shifter 50 through the second pin TP2 of the timing controller 30. [ The level shifter 50 receives the first and second timing control signals through the first and second pins LP1 and LP2. For example, the first timing control signal may be an on-clock signal and the second timing control signal may be an off-clock signal. In this case, the level shifter 50 may generate the gate clock signals according to the first and second timing control signals, and the clock output pins CP1 to CPr, r, To the gate driver (11).

The first pin MP1 of the memory 40 is also connected to the first pin LP1 of the level shifter 50 so that the first timing MP1 of the level shifter 40 also receives the first timing control signal do. Since the second pin MP2 of the memory 40 is also connected to the second pin LP2 of the level shifter 50, the second timing control signal is also input to the second pin MP2 of the memory 40 . However, since the first and second timing control signals are signals irrelevant to the I ² C communication, the memory 40 does not transmit any signals even if the first and second timing control signals are input.

As described above, the timing controller 30 according to the embodiment of the present invention not only receives the SCL signal and the SDA signal from the memory 40 via the first and second pins, but also drives the level shifter 50 And may output first and second timing control signals corresponding to the timing control signals. As a result, the timing controller 30 according to the embodiment of the present invention can reduce either of the pins receiving the SCL signal and the SDA signal and the pins outputting the driving timing control signals. Therefore, the embodiment of the present invention can reduce the number of input / output pins of the timing controller, thereby preventing a problem that the cost of the timing controller is increased due to an increase in the size of the timing controller in the high-resolution display device.

6 is a detailed block diagram illustrating a timing controller according to the first embodiment of the present invention. 6, the timing controller 30 according to the first embodiment of the present invention includes an input / output control unit 31, a timing control signal supply unit 32, first and second OR gate circuits OR1 and OR2, First to fourth transistors T1 to T4, an inverter INV2, and first and second pins TP1 and TP2. In FIG. 6, the input / output control unit 31, the timing control signal supply unit 32, the first and second logic gate circuits OR1 and OR2, the first to fourth transistors T1 to T4, the inverter INV2, and the first and second pins TP1 and TP2.

Referring to FIG. 6, the input / output control unit 31 includes first and second input terminals IN1 and IN2 and an output terminal OUT1. Since the first input terminal IN1 of the input / output control unit 31 is connected to the first pin TP1, the SCL signal SCL is input to the first input terminal IN1. Since the second input terminal IN2 of the input / output control unit 31 is connected to the second pin TP2, the SDA signal SDA is input to the second input terminal IN2. The output terminal OUT1 of the input / output control unit 31 outputs the input / output control signal IOCS. The output terminal OUT1 of the input / output control unit 31 is connected to the control electrodes of the first and second transistors T1 and T2 and the inverter INV1.

The input / output control unit 31 may control the gate-off voltage Voff during the first period t1 during which the SCL signal SCL and the SDA signal SDA are input to the first and second pins TP1 and TP2, And outputs the input / output control signal IOCS. The gate off voltage Voff is a voltage capable of turning off the first to fourth transistors when supplied to the control electrodes of the first to fourth transistors. The SCL signal SCL and the SDA signal SDA each swing at the first logic voltage LV1 and the second logic voltage LV2 as shown in Fig.

When the input of the SCL signal SCL and the SDA signal SDA is completed by the first and second pins TP1 and TP2 as shown in FIG. 7, the input / output control unit 31 outputs a signal for a predetermined period, for example, X Output control signal IOCS of the gate-on voltage Von during the second period t2 after the positive integer ms. The gate-on voltage Von is a voltage capable of turning on the first to fourth transistors when supplied to the control electrodes of the first to fourth transistors. The predetermined period of X ms can be appropriately set through a preliminary experiment.

The timing control signal supply unit 32 includes first and second input terminals IN3 and IN4 and first and second output terminals OUT2 and OUT3. Since the first input terminal IN3 of the timing control signal supply unit 32 is connected to the first pin TP1, the SCL signal SCL is input to the first input terminal IN3. Since the second input terminal IN4 of the timing control signal supply unit 32 is connected to the second pin TP2, the SDA signal SDA is input to the second input terminal IN4. The first output terminal OUT2 of the timing control signal supply unit 32 outputs the first timing control signal TCS1. The first output terminal OUT2 of the timing control signal supply section 32 is connected to the first input terminal of the first OR gate circuit OR1. The second output terminal OUT3 of the timing control signal supply unit 32 outputs the second timing control signal TCS2. The second output terminal OUT3 of the timing control signal supply section 32 is connected to the first input terminal of the second OR gate circuit OR2.

The timing control signal supply unit 32 supplies the first logic voltage V1 during the first period t1 during which the SCL signal SCL and the SDA signal SDA are input to the first and second pins TP1 and TP2. 1 timing control signal TCS1 and the second timing control signal TCS2. The timing control signal supply unit 32 supplies a predetermined period of time, for example, X ms, after the input of the SCL signal SCL and the SDA signal SDA to the first and second pins TP1 and TP2, And outputs the first timing control signal TCS1 and the second timing control signal TCS2 of the second logic voltage V2 during the second period t2.

The first OR gate circuit OR1 receives a signal input to the first pin TP1 through the third transistor T3 and a signal output to the first output terminal OUT2 of the timing control signal supply section 32, And outputs it. The second OR gate circuit OR2 receives the signal input to the second pin TP2 through the fourth transistor T4 and the signal output to the second output terminal OUT3 of the timing control signal supply section 32, And outputs it.

The first transistor T1 is turned on by the output signal of the output terminal OUT1 of the input / output control unit 31 to electrically connect the first pin TP1 and the output terminal of the first OR gate circuit OR1 . The first transistor T1 includes a control electrode, first and second electrodes, a control electrode connected to the inverter INV1, a first electrode connected to the output terminal of the first OR gate circuit OR1, And the second electrode is connected to the first fin P1.

The second transistor T2 is turned on by the output signal of the output terminal OUT1 of the input / output control unit 31 to electrically connect the second pin TP2 and the output terminal of the second OR gate circuit OR2 . The second transistor T2 includes a control electrode, first and second electrodes, a control electrode connected to the inverter INV1, a first electrode connected to the output terminal of the second OR gate circuit OR2, And the second electrode is connected to the second fin P2.

The third transistor T3 is turned on by the output signal of the inverter INV1 to electrically connect the first pin TP1 and the input terminal of the first OR gate circuit OR1. The third transistor T3 includes a control electrode, first and second electrodes, the control electrode is connected to the inverter INV1, the first electrode is connected to the second input terminal of the first OR gate circuit OR1 And the second electrode is connected to the first fin P1.

The fourth transistor T4 is turned on by the output signal of the inverter INV1 to electrically connect the second pin TP2 and the input terminal of the second OR gate circuit OR2. The fourth transistor T4 includes a control electrode, first and second electrodes, the control electrode is connected to the inverter INV1, and the first electrode is connected to the second input terminal of the second OR gate circuit OR2 And the second electrode is connected to the second pin P2.

The inverter INV1 is connected between the control electrodes of the third and fourth transistors T3 and T4 and the output terminal OUT1 of the input / output control unit 31. [ The inverter INV1 inverts the input / output control signal IOCS output to the output terminal OUT1 of the input / output control unit 31 and outputs it to the control electrodes of the third and fourth transistors T3 and T4. The turn-on of the first and second transistors T1 and T2 and the turn-on of the third and fourth transistors T3 and T4 by the inverter INV1 can be reversely controlled. That is, when the first and second transistors T1 and T2 are turned on, the third and fourth transistors T3 and T4 are turned off and the first and second transistors T1 and T2 are turned off. The third and fourth transistors T3 and T4 can be controlled to be turned on.

Hereinafter, a method of controlling signals input to and output from the first and second pins TP1 and TP2 and input / output signals of the timing controller 30 according to the first embodiment of the present invention will be described in detail with reference to FIGS. I will look at it. 8, S_P1 denotes a signal input / output to the first pin TP1, and S_P2 denotes a signal input / output to / from the second pin TP2.

First, the SCL signal SCL and the SDA signal SDA from the memory 40 are input to the first and second pins TP1 and TP2 of the timing controller 30 during the first period t1 . The input / output control unit 31 of the timing controller 30 is connected to the first and second pins TP1 and TP2 and receives the SCL signal SCL and the SDA signal SDA. The SCL signal SCL and the SDA signal SDA swing at the first logic voltage LV1 and the second logic voltage LV2 as shown in Fig. The input / output control unit 31 outputs the input / output control signal IOCS of the gate off voltage Voff to the output terminal OUT1 when the SCL signal SCL and the SDA signal SDA are inputted. (S101 and S102 in Fig. 7)

The first and second transistors T1 and T2 are turned off by the input / output control signal IOCS of the gate off voltage Voff. The output terminal of the first OR gate circuit OR1 and the first pin TP1 are electrically disconnected due to the turn-off of the first transistor T1 and the second terminal T2 is turned off due to the turn- The OR gate circuit OR2 and the second pin TP2 are electrically disconnected.

Since the input / output control signal IOCS of the gate off voltage Voff is inverted by the inverter INV1 and supplied to the control electrodes of the third and fourth transistors T3 and T4 with the gate-on voltage Von, 3 and the fourth transistors T3 and T4 are turned on. The second input terminal of the first OR gate circuit OR1 and the first pin TP1 are electrically connected due to the turn-on of the third transistor T3. Due to the turn-on of the fourth transistor T4, the second input terminal of the second OR gate circuit OR2 and the second pin TP2 are electrically connected.

The timing control signal supply section 32 is electrically connected to the first and second pins TP1 and TP2 due to the turn-on of the third and fourth transistors T3 and T4. The timing control signal supply unit 32 is connected to the first and second pins TP1 and TP2 and receives the SCL signal SCL and the SDA signal SDA. The timing control signal supply unit 32 generates the first and second timing signals TCS1 and TCS2 in accordance with the drive timing information input from the SCL signal SCL and the SDA signal SDA. The timing control signal supply unit 32 outputs the first timing control signal TCS1 to the first output terminal OUT2 and the second timing control signal TCS2 to the second output terminal OUT2.

The first OR gate circuit OR1 performs an OR operation on the SCL signal SCL input to the input terminals and the first timing control signal TCS1 and outputs the result to the output terminal. However, since the first transistor T1 is turned off and the output terminal of the first OR gate circuit OR1 is not connected to the first pin TP1, no signal is output to the first pin TP1.

The second OR gate circuit OR2 performs an OR operation on the SDA signal SDA input to the input terminals and the second timing control signal TCS2 and outputs the result to the output terminal. However, since the second transistor T2 is turned off and the output terminal of the second OR gate circuit OR2 is not connected to the second pin TP2, no signal is output to the second pin TP2.

As described above, the embodiment of the present invention outputs the input / output control signal IOCS of the gate off voltage Voff when the SCL signal SCL and the SDA signal SDA are input during the first period t1 . The first and second transistors T1 and T2 are turned off by the input / output control signal IOCS of the gate-off voltage Voff and are supplied to the output terminals of the first and second OR gates OR1 and OR2 And the first and second pins TP1 and TP2, respectively. The third and fourth transistors T3 and T4 are turned on by the input / output control signal IOCS of the gate-on voltage Von inverted by the inverter so that the first and second OR gates OR1, OR2 to the first and second pins TP1 and TP2, respectively. As a result, the embodiment of the present invention can receive the SCL signal (SCL) and the SDA signal (SDA) to the first and second pins TP1 and TP2 during the first period t1.

Second, the input / output control unit 31 outputs the input / output control signal IOCS of the gate-on voltage Von after X ms when the input of the SCL signal SCL and the SDA signal SDA from the memory 40 is completed do. Xms is a period during which the SCL signal SCL and SDA signal SDA input to the first and second pins TP1 and TP2 during the first period t1 and the first and second pins The first and second timing control signals TCS1 and TCS2 output to the first and second timing control signals TP1 and TP2 may be set appropriately through a preliminary experiment so that they do not overlap with each other. (S103 and S104 in Fig. 7)

The first and second transistors T1 and T2 are turned on by the input / output control signal IOCS of the gate-on voltage Von. The output terminal of the first OR gate circuit OR1 is electrically connected to the first pin TP1 due to the turn-on of the first transistor T1 and the second terminal T2 is turned on due to the turn- The OR gate circuit OR2 and the second pin TP2 are electrically connected.

The input / output control signal IOCS of the gate-on voltage Von is inverted by the inverter INV1 and supplied to the control electrodes of the third and fourth transistors T3 and T4 at the gate-off voltage Voff, 3 and the fourth transistors T3 and T4 are turned off. The second input terminal of the first OR gate circuit OR1 and the first pin TP1 are electrically disconnected due to the turn-off of the third transistor T3. The second input terminal of the second OR gate circuit OR2 and the second pin TP2 are electrically disconnected due to the turn-off of the fourth transistor T4.

The timing control signal supply section 32 is not connected to the first and second pins TP1 and TP2 due to the turn-off of the third and fourth transistors T3 and T4. The timing control signal supply unit 32 outputs a first timing control signal TCS1 generated in accordance with the SCL signal SCL and the SDA signal SDA during the first period t1 to the first output terminal OUT2, And outputs the second timing control signal TCS2 to the second output terminal OUT2.

The first OR gate circuit OR1 performs an OR operation between the signal input from the first pin TP1 and the first timing control signal TCS1. The output terminal of the first OR gate circuit OR1 is connected to the first pin TP1 due to the turn-on of the first transistor T1. The second input terminal of the first OR gate circuit OR1 is not connected to the first pin TP1 due to the turn-off of the third transistor T3. Therefore, the first OR gate circuit OR1 outputs the first timing control signal TCS1 to the first pin TP1.

The second OR gate circuit OR2 performs an OR operation between the signal input from the second pin TP2 and the second timing control signal TCS2. Due to the turn-on of the second transistor T2, the output terminal of the second OR gate circuit OR2 is connected to the second pin TP2. Due to the turn-off of the fourth transistor T4, the second input terminal of the second OR gate circuit OR2 is not connected to the second pin TP2. Therefore, the second OR gate circuit OR2 outputs the second timing control signal TCS2 to the second pin TP2.

As described above, in the embodiment of the present invention, when input of the SCL signal SCL and the SDA signal SDA from the memory 40 is completed, the input / output control signal IOCS of the gate- . The first and second transistors T1 and T2 are turned on by the input / output control signal IOCS of the gate-on voltage Von to turn on the output terminals of the first and second OR gates OR1 and OR2 And the first and second pins TP1 and TP2, respectively. The third and fourth transistors T3 and T4 are turned on by the input / output control signal IOCS of the gate-on voltage Von inverted by the inverter so that the first and second OR gates OR1, OR2 and the first and second pins TP1 and TP2, respectively. As a result, the embodiment of the present invention can output the first and second timing signals TCS1 and TCS2 to the first and second pins TP1 and TP2 during the second period t2.

The SCL signal SCL and the SDA signal SDA are input to the first and second pins TP1 and TP2 during the first period t1 and the SCL signal SCL and the SDA signal SDA are input to the first and second pins TP1 and TP2, The first and second timing control signals TCS1 and TCS2 generated in accordance with the control signal SDA are supplied to the first and second timing control signals TCS1 and TCS2 during the second period t2, (TP1, TP2). As a result, the embodiment of the present invention not only receives the SCL signal (SCL) and the SDA signal (SDA) using the first and second pins TP1 and TP2, but also receives the first and second timing control signals (TCS1, TCS2), it is possible to delete the pins used for outputting the first and second timing control signals TCS1, TCS2. In other words, the embodiment of the present invention can reduce the number of input / output pins of the timing controller, thereby preventing a problem that the cost of the timing controller is increased due to an increase in the size of the timing controller in the high-resolution display device.

9 is a detailed block diagram of a timing controller according to a second embodiment of the present invention. Referring to FIG. 9, the timing controller 30 according to the second embodiment of the present invention includes an input / output control unit 31, a timing control signal supply unit 32, first and second multiplexers MUX1 and OR2, Second transistors T1 and T2, an inverter INV2, and first and second pins TP1 and TP2. The input / output control unit 31, the timing control signal supply unit 32, and the first and second transistors T1 and T2 shown in FIG. 9 are substantially the same as those described with reference to FIG. Therefore, the detailed description of the input / output control unit 31, the timing control signal supply unit 32, and the first and second transistors T1 and T2 shown in FIG. 9 will be omitted.

The first multiplexer MUX1 receives the SCL signal SCL input to the first pin P1 according to the inversion signal of the input / output control signal IOCS and the first output terminal OUT2 of the timing control signal supply unit 32 And outputs the first timing control signal TCS1. For example, the first multiplexer MUX1 outputs the SCL signal SCL input to the first pin P1 when the inversion signal of the input / output control signal IOCS is the gate-on voltage Von, And outputs the first timing control signal TCS1 when the inversion signal of the input / output control signal IOCS is the gate-off voltage Voff.

The second multiplexer MUX2 receives the SDA signal SDA input to the second pin P2 and the second output terminal OUT3 of the timing control signal supply unit 32 in accordance with the inversion signal of the input / And the second timing control signal TCS2 outputted from the second timing control signal TCS2. For example, the second multiplexer MUX2 outputs the SDA signal SDA input to the second pin P2 when the inversion signal of the input / output control signal IOCS is the gate-on voltage Von, And outputs the second timing control signal TCS2 when the inversion signal of the input / output control signal IOCS is the gate-off voltage Voff.

The inverter INV2 is connected between the first and second multiplexers MUX1 and MUX2 and the output terminal OUT1 of the input / output control unit 31. [ The inverter INV2 inverts the input / output control signal IOCS output to the output terminal OUT1 of the input / output control unit 31 and outputs it to the first and second multiplexers MUX1 and MUX2.

The method of controlling signals input to and output from the first and second pins TP1 and TP2 and the input / output signals of the timing controller 30 according to the second embodiment of the present invention shown in FIG. 8, and are substantially the same as those described above.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 11: gate driver
20: Data driver 21: Source drive IC
30: Timing controller 31: I /
32: Timing control signal supply unit 40: Memory
50: level shifter 60: source flexible film
70: source printed circuit board 80: control printed circuit board
90: Flexible circuit board

Claims (9)

And a timing controller for receiving driving timing information through the SCL signal and the SDA signal,
Wherein the timing controller receives the SCL signal through a first pin and receives the SDA signal through a second pin, generates first and second timing control signals based on the SCL signal and the SDA signal, And outputs the first timing control signal through the first pin and the second timing control signal through the second pin. The method according to claim 1,
Wherein the SCL signal and the SDA signal are input to the first and second pins during a first period and first and second timing control signals are output to the first and second pins during a second period. 3. The method of claim 2,
The first period is ended, and the second period starts after X (X is a positive integer) ms. The method according to claim 1,
And a memory for storing the driving timing information and outputting the driving timing information to the timing controller through the SCL signal and the SDA signal. 5. The method of claim 4,
A display panel including gate lines, data lines, and pixels provided at intersections of the gate lines and the data lines;
A gate driver for supplying gate signals to the gate lines; And
And a data driver for supplying data voltages to the data lines. 6. The method of claim 5,
And a level shifter for outputting clock signals having swing widths of a gate low voltage and a gate high voltage based on the first and second timing control signals. 6. The method of claim 5,
And a level shifter for changing a voltage swing width of the first and second timing control signals from a first logic voltage and a second logic voltage to a gate low voltage and a gate high voltage. 8. The method according to claim 6 or 7,
And the timing controller outputs the first and second timing control signals to the level shifter through the first and second pins. A display panel including gate lines, data lines, and pixels provided at intersections of the gate lines and the data lines;
A gate driver for supplying gate signals to the gate lines;
A data driver for supplying data voltages to the data lines;
A memory for storing a gate control signal for driving the gate driver and timing information for a data control signal for driving the data driver; And
Receiving the timing information from the memory via the first pin and receiving the SDA signal through the second pin, generating the gate control signal and the data control signal based on the SCL signal and the SDA signal A first timing control signal of the gate control signal and the data control signal through the first pin and a second timing control signal of the gate control signal and the data control signal through the second pin A display device comprising a timing controller.

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