KR20120072707A - Display device and driving method thereof - Google Patents

Abstract

PURPOSE: A display device and driving method thereof are provided to reduce costs by using an individual EEPROM. CONSTITUTION: A host system(140) outputs image data and timing signals. A timing controller(130) outputs timing control signals, and the timing control signals control the operation of a display panel. A memory element(150) stores operation information of a display device and optional information and outputs driving information to a host system and the optional information to the timing controller.

Description

DISPLAY DEVICE AND DRIVING METHOD THEREOF}

The present invention relates to a display device and a driving method thereof.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms. Recently, a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting diode are being developed. Various flat panel display devices such as organic light emitting diodes (OLEDs) are utilized.

The display device includes a display panel for displaying an image, a data driving circuit for supplying a data voltage to data lines of the display panel, and a gate driving circuit for sequentially supplying a gate pulse (or scan pulse) to the gate lines of the display panel. And a timing controller for controlling the operation timing of the driving circuits. The timing controller receives image data RGB, vertical synchronization signal Vsync, horizontal synchronization signal Hsync, data enable signal DE, and clock signal CLK from the host system. A signal for controlling the operation timing is generated and output.

The host system serially communicates with a memory device located on an interface board and receives EDID (Extended Display Identification Data) information stored in the memory device. In this case, a read only memory (ROM), in particular, an electrically erasable programmable ROM (EEPROM) may be used as the memory device. EDID information refers to information for driving the display device, such as the resolution of the display device, the frequency of the vertical synchronization signal Vsync, and the frequency of the horizontal synchronization signal Hsync. The host system uses image data RGB, vertical sync signal Vsync, horizontal sync signal Hsync, data enable signal DE, and clock signal CLK based on the EDID information received from the EEPROM. Output to the timing controller.

The timing controller serially communicates with the EEPROM located on the printed circuit board to receive option information for driving the display device stored in the memory device. The option information includes a look-up table for driving an over driving circuit. The timing controller reflects option information received from the EEPROM and outputs timing control signals.

In summary, the host system receives EDID information from the EEPROM located on the interface board, and the timing controller receives option information for driving the display device from the EEPROM located on the printed circuit board. Conventionally, since the host system and the timing controller use the EEPROM separately, there is a problem of cost loss.

The present invention provides a display device and a driving method thereof which can reduce cost by using one EEPROM.

A display device of the present invention includes a host system for outputting image data and timing signals; A timing controller receiving the image data and the timing signals from the host system and outputting timing control signals for controlling driving of a display panel; And store driving information of a display device, and option information for driving the display device, and serially communicate with the host system to output driving information of the display device to the host system, and serially communicate with the timing controller. A memory element for outputting option information to the timing controller, wherein the host system is in serial communication with the memory element and between the time the host system outputs the image data and the timing signals to the timing controller, And the timing controller is in serial communication with the memory element.

The driving method of the display device of the present invention stores driving information of the display device and option information for driving the display device, and serially communicates with the host system to output the drive information of the display device to the host system, and a timing controller. Serially communicating with the outputting the option information to the timing controller; Outputting image data and timing signals from the host system; And receiving the image data and the timing signals from the host system, and outputting timing control signals for controlling driving of a display panel, wherein the time when the host system is in serial communication and the host system are the timing controllers. The timing controller is in serial communication with the memory device between the time of outputting the image data and the timing signals.

In the present invention, the timing controller serially communicates with the EEPROM at an extra time between the time when the host system is in serial communication with the EEPROM and when the host system outputs the image data and timing signals to the timing controller. As a result, the present invention can reduce costs by using one EEPROM.

1 is a block diagram schematically illustrating a display device according to an exemplary embodiment of the present invention.
2 is a block diagram illustrating a host system, a timing controller, and an EEPROM according to an embodiment of the present invention.
3 is a waveform diagram showing a serial clock and serial data as a serial communication interface.
4A and 4B are waveform diagrams showing serial communication control signals according to the first and second embodiments of the present invention.
5A and 5B are diagrams of simulation results showing a serial clock according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

The names of the components used in the following description are selected in consideration of the ease of preparation of the specification, and may be different from the names of the actual products.

1 is a block diagram schematically illustrating a display device according to an exemplary embodiment of the present invention. Referring to FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a display panel 10, a gate driver 110, a data driver 120, a timing controller 130, and a host system 140. do. The display panel 10 includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), an inorganic electroluminescent device and an organic light emitting diode device. The display panel may be implemented as a display panel of a flat panel display device such as an electroluminescence device (EL) including an organic light emitting diode (OLED) and an electrophoresis display device (EPD). Hereinafter, the display panel 10 will be described based on the implementation of the liquid crystal display device.

The display panel 10 displays an image under the control of the timing controller 130. The display panel 10 includes a thin film transistor (“TFT”) substrate and a color filter substrate. A liquid crystal layer is formed between the TFT substrate and the color filter substrate. On the TFT substrate, the data lines D and the gate lines G (or scan lines) are formed to cross each other on the lower glass substrate, and are defined by the data lines D and the gate lines G. The liquid crystal cells are arranged in a matrix form in the formed cell regions. The TFT formed at the intersection of the data lines D and the gate lines G transmits the data voltage supplied through the data lines D to the pixel electrode of the liquid crystal cell in response to a gate pulse from the gate line G. Will be delivered. For this purpose, the gate electrode of the TFT is connected to the gate line G, and the source electrode is connected to the data line D. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell and the storage capacitor. The storage capacitor maintains the data voltage transferred to the pixel electrode for a predetermined time until the next data voltage comes in. The common voltage is supplied to the common electrode facing the pixel electrode.

The color filter substrate includes a black matrix and a color filter formed on the upper glass substrate. The common electrode is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and a horizontal electric field such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode. The driving method is formed on the lower glass substrate together with the pixel electrode.

An upper polarizer is attached to the upper glass substrate of the display panel 10, and a lower polarizer is attached to the lower glass substrate. The light transmission axis of the upper polarizer and the light transmission axis of the lower polarizer are perpendicular to each other. In addition, an alignment film for setting a pre-tilt angle of the liquid crystal is formed on the upper glass substrate and the lower glass substrate. A spacer is formed between the upper glass substrate and the lower glass substrate of the display panel 10 to maintain a cell gap of the liquid crystal layer. The liquid crystal mode of the display panel 10 may be implemented in any of the liquid crystal modes as well as the above-described TN mode, VA mode, IPS mode, and FFS mode.

When the display panel 10 is implemented as a liquid crystal display, a backlight unit is required. The backlight unit includes a light source, a light guide plate (or a diffusion plate), a plurality of optical sheets, and the like, which light up according to a driving current supplied from the backlight unit driver. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit. The light sources of the backlight unit may include one of a hot cathode fluorescent lamp (HCFL), a cold cathode fluorescent lamp (CCFL), an external electrode fluorescent lamp (EEFL), a light emitting diode (LED), or two or more light sources. .

The backlight unit driver generates a driving current for turning on light sources of the backlight unit. The backlight unit driver turns on / off a driving current supplied to the light sources under the control of the timing controller 130. The timing controller 130 outputs the backlight control data in which the backlight brightness and the lighting timing are adjusted according to the global / local dimming signal (DIM) input from the host system 140 in the SPI (Serial Peripheral Interface) data format to the backlight unit driver. do.

The data driver 120 includes a plurality of source drive integrated circuits (ICs). The source drive ICs convert the image data RGB input from the timing controller 130 into positive / negative gamma compensation voltages to generate positive / negative analog data voltages. Positive / negative analog data voltages output from the source drive ICs are supplied to the data lines of the display panel 10.

The gate driver 110 includes a plurality of gate drive ICs each including a shift register, a level shifter for converting an output signal of the shift register into a swing width suitable for driving a TFT of a liquid crystal cell, an output buffer, and the like. The gate driver 110 sequentially supplies gate pulses synchronized with the data voltage to the gate lines G of the display panel 10 under the control of the timing controller.

The timing controller 130 may be configured to output image data RGB, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, a clock signal CLK, and the like output from the host system 140. The gate driver control signal is output to the gate driver 110 based on the signals, and the data driver control signal is output to the data driver 120. The gate driver control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (Gate Output Enable, GOE), and the like. The gate start pulse GSP controls the timing of the first gate pulse. The gate shift clock GSC is a clock signal for shifting the gate start pulse GSP. The gate shift clock GSC is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output timing of the gate driver 110.

The data driver control signal includes a source start pulse (SSP), a source sampling clock (SSC), a source output enable signal (SOE), a polarity control signal (POL), and the like. . The source start pulse SSP controls the data sampling start time of the data driver 120. The source sampling clock is a clock signal that controls the sampling operation of the data driver 120 based on the rising or falling edge. If the digital video data to be input to the data driver 120 is transmitted using a mini LVDS (Low Voltage Differential Signaling) interface standard, the source start pulse SSP and the source sampling clock SSC may be omitted. The polarity control signal POL inverts the polarity of the data voltage output from the data driver 120 every L (L is a natural number) horizontal period period. The source output enable signal SOE controls the output timing of the data driver 120.

The host system 140 supplies the image data RGB and the timing signals Vsync, Hsync, DE, and CLK to the timing controller 130.

2 is a block diagram illustrating a host system, a timing controller, and an EEPROM according to an embodiment of the present invention. 3 is a waveform diagram showing a serial clock and serial data as a serial communication interface. 2 will be described with reference to FIG. 3.

2, the timing controller 130, and host system 140, each of ^{I 2 C (Inter-Integrated Circuit} ) and send and receive data with the memory device via the serial communication means, such as. In this case, a read only memory (ROM), in particular, an electrically erasable programmable ROM (EEPROM) 150 may be used. In addition, I ² C is a method of transmitting and receiving data using serial data (SDA) and serial clock (SCL).

Each of the timing controller 130 and the host system 140 bidirectionally communicates with the EEPROM 150 through the serial clock SCL and the serial data SDA. Specifically, the host system 140 receives EDID (Extended Display Identification Data) information stored in the EEPROM 150 through serial communication. EDID information refers to driving information of the display device such as the resolution of the display device, the frequency of the vertical synchronization signal Vsync, and the frequency of the horizontal synchronization signal Hsync. The timing controller 130 receives option information for driving the display device stored in the EEPROM 150 through serial communication. The option information includes look-up table information for driving an over driving circuit, timing signal information when driving a dual gate start pulse (GSP), and the like.

Referring to FIG. 3, the serial clock SCL is a clock signal having a predetermined frequency, and the serial data SDA is a signal for transmitting data having predetermined bits. The predetermined bit may be implemented with 8 bits. Data transmission of the serial data SDA is controlled by the serial clock SCL and the serial data SDA. As shown in FIG. 3, when the serial data SDA rises in the section where the serial clock SCL is at the high logic level H, the data transmission of the serial data SDA starts (START). When the serial data SDA is polled in the section where the serial clock SCL is the high logic level H, the data transmission of the serial data SDA is stopped (STOP). In addition, one data information is transmitted by a pair of serial clocks SCL and serial data SDA. By connecting a pair of serial clocks (SCL) and serial data (SDA) in parallel, several data information can be transmitted at once.

The serial clock SCL line of the host system 140 is connected to the EEPROM 150 by switching of the first transistor T1, and the serial data SDA line is connected to the EEPROM 150 by switching of the second transistor T2. 150). The serial clock SCL line of the timing controller 130 is connected to the EEPROM 150 by switching of the third transistor T3, and the serial data SDA line of the timing controller 130 is the fourth transistor T4. It is connected to the EEPROM 150 by switching of.

The host system 140 bidirectionally communicates with the EEPROM 150 through the serial data SDA of the serial data SDA line and the serial clock SCL of the serial clock SCL line. The serial clock SCL line of the host system 140 is connected to the first transistor T1 so that the EEPROM only when the first transistor T1 is turned on in response to the serial communication control signal C _SC of a high logic level. Serial communication with 150. The gate electrode of the first transistor T1 is connected to the serial communication control signal C _SC line, the source electrode (or drain electrode) is connected to the first node N1, and the drain electrode (or source electrode) is the host. It is connected to the serial clock (SCL) line of system 140. The serial data (SDA) line of the host system 140 is connected to the second transistor T2 and the EEPROM 150 only when the second transistor T2 is turned on in response to the serial communication control signal C _SC . Serial communication. The gate electrode of the second transistor T2 is connected to the serial communication control signal C _SC line, the source electrode (or drain electrode) is connected to the second node N2, and the drain electrode (or source electrode) is the host. It is connected to the serial data (SDA) line of the system 140.

The timing controller 130 bidirectionally communicates with the EEPROM 150 through the serial data SDA of the serial data SDA line and the serial clock SCL of the serial clock SCL line. The serial clock SCL line of the timing controller 130 is connected to the third transistor T3 and the EEPROM 150 only when the third transistor T3 is turned on in response to the serial communication control signal C _SC . Serial communication. The gate electrode of the third transistor T3 is connected to the serial communication control signal C _SC line, the source electrode (or the drain electrode) is connected to the series clock SCL line of the timing controller 130, and the drain electrode ( Or a source electrode) is connected to the first node N1. The serial data (SDA) line of the timing controller 130 is connected to the fourth transistor T4 and the EEPROM 150 only when the fourth transistor T4 is turned on in response to the serial communication control signal C _SC . Serial communication. The gate electrode of the fourth transistor T4 is connected to the serial communication control signal (C _SC ) line, the source electrode (or the drain electrode) is connected to the series data (SDA) line of the timing controller 130, and the drain electrode ( Or a source electrode) is connected to the second node N2.

The serial communication control signal C _SC is generated from the timing controller 130 to switch on / off of the first to fourth transistors T1 to T4, thereby performing serial communication between the host system 140 and the EEPROM 150. And serial communication between the timing controller 130 and the EEPROM 150. First and second transistors (T1, T2) the gate electrode, the serial communication control signals (C _SC) in is input as it is, the third and fourth transistors (T3, T4) the gate electrode, the serial communication control signals (C _SC of ) Is inputted. The inverter Inv outputs a signal obtained by inverting the serial communication control signal C _SC generated from the timing controller 130 to the gate electrodes of the third and fourth transistors T3 and T4.

The timing controller 130 is mounted on a control-printed circuit board, and the host system 140 is mounted on a system board. The EEPROM 150 is mounted on an interface board. The interface board is connected to the host system 140 to supply the image data RGB to the timing controller 130 through an interface such as a low voltage differential signaling (LVDS) interface and a transition minimized differential signaling (TMDS) interface. do. The interface board may be included in the system board.

Hereinafter, a method of serial communication between the timing controller 130 and the host system 140 with the EEPROM 150 will be described with reference to FIGS. 4A and 4B.

4A and 4B are waveform diagrams showing serial communication control signals according to the first and second embodiments of the present invention. 4A and 4B, t1 denotes a time when the host system 140 serially communicates with the EEPROM 150, t2 denotes a time when the timing controller 130 communicates serially with the EEPROM 150, and t3 denotes a host system ( The timing controller 130 outputs timing signals such as image data RGB, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a clock signal CLK to the timing controller 130. It's time. According to the present invention, the time t1 when the host system 140 performs serial communication with the EEPROM 150 and the time t3 when the host system 140 outputs image data RGB and timing signals to the timing controller 130 are described. The timing controller 130 serially communicates with the EEPROM 150 using the extra time (t2 time) existing between the < RTI ID = 0.0 >

Referring to FIG. 4A, the serial communication control signal C _SC according to the first embodiment of the present invention is generated at the high logic level H for t1 time and at the low logic level L for t2 and t3 time. do.

During the t1 time, the serial communication control signal C _SC of the high logic level H is input to the gate electrodes of the first and second transistors T1 and T2 and the serial communication control signal of the low logic level L C _SC is input to the gate electrodes of the third and fourth transistors T3 and T4. Accordingly, since the first transistor T1 and the second transistor T2 are turned on in response to the serial communication control signal C _SC of the high logic level H, the host system 140 may turn on the serial clock SCL. And serial communication with EEPROM 150 via serial data (SDA). However, since the third transistor T3 and the fourth transistor T4 are turned off in response to the serial communication control signal C _SC of the low logic level L, the timing controller 130 may turn off the serial clock SCL. And serial communication with EEPROM 150 via serial data (SDA).

During the t2 time, the serial communication control signal C _SC of the low logic level L is input to the gate electrodes of the first and second transistors T1 and T2 and the serial communication control signal of the high logic level H C _SC is input to the gate electrodes of the third and fourth transistors T3 and T4. Accordingly, since the third transistor T3 and the second transistor T4 are turned on in response to the serial communication control signal C _SC of the high logic level H, the timing controller 130 may turn on the serial clock SCL. And serial communication with EEPROM 150 via serial data (SDA). However, since the first transistor T1 and the second transistor T2 are turned off in response to the serial communication control signal C _SC of the low logic level L, the host system 140 may turn off the serial clock SCL. And serial communication with EEPROM 150 via serial data (SDA).

During the t3 time period, the host system 140 transmits the image data RGB, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DE, and the clock signal CLK to the timing controller 130. Output timing signals, and the timing controller 130 outputs signals for controlling timing of the gate driver 110 and the data driver 120 based on the input timing signals. Accordingly, the timing controller 130 and the host system 140 do not serially communicate with the EEPROM 150 regardless of the serial communication control signal C _SC .

Referring to FIG. 4B, the serial communication control signal C _SC according to the second embodiment of the present invention is generated at the high logic level H for t1 and t3 times and at the low logic level L for t2 time. do.

During the t1 time, the serial communication control signal C _SC of the high logic level H is input to the gate electrodes of the first and second transistors T1 and T2 and the serial communication control signal of the low logic level L C _SC is input to the gate electrodes of the third and fourth transistors T3 and T4. Accordingly, since the first transistor T1 and the second transistor T2 are turned on in response to the serial communication control signal C _SC of the high logic level H, the host system 140 may turn on the serial clock SCL. And serial communication with EEPROM 150 via serial data (SDA). However, since the third transistor T3 and the fourth transistor T4 are turned off in response to the serial communication control signal C _SC of the low logic level L, the timing controller 130 may turn off the serial clock SCL. And serial communication with EEPROM 150 via serial data (SDA).

During the t2 time, the serial communication control signal C _SC of the low logic level L is input to the gate electrodes of the first and second transistors T1 and T2 and the serial communication control signal of the high logic level H C _SC is input to the gate electrodes of the third and fourth transistors T3 and T4. Accordingly, since the third transistor T3 and the fourth transistor T4 are turned on in response to the serial communication control signal C _SC of the high logic level H, the timing controller 130 may turn on the serial clock SCL. And serial communication with EEPROM 150 via serial data (SDA). However, since the first transistor T1 and the second transistor T2 are turned off in response to the serial communication control signal C _SC of the low logic level L, the host system 140 may turn off the serial clock SCL. And serial communication with EEPROM 150 via serial data (SDA).

During the t3 time period, the host system 140 transmits the image data RGB, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DE, and the clock signal CLK to the timing controller 130. Output timing signals, and the timing controller 130 outputs signals for controlling timing of the gate driver 110 and the data driver 120 based on the input timing signals. Accordingly, the timing controller 130 and the host system 140 do not serially communicate with the EEPROM 150 regardless of the serial communication control signal C _SC .

5A and 5B are diagrams of simulation results showing a serial clock according to an embodiment of the present invention. FIG. 5B is an enlarged view illustrating a time in which the timing controller 130 serially communicates with the EEPROM 150 at time t2 of FIG. 5A.

t1 is the time when the host system 140 serially communicates with the EEPROM 150, t2 is the time when the timing controller 130 is in serial communication with the EEPROM 150, and t3 is the host system 140 with the timing controller 130. It is a time for outputting timing signals such as the image data RGB, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DE, and the clock signal CLK.

At time t1, since the host system 140 serially communicates with the EEPROM 150, a serial clock SCL is generated between the host system 140 and the EEPROM 150 as shown in FIG. 5A.

At time t2, since the timing controller 130 communicates in series with the EEPROM 150, a serial clock SCL is generated between the timing controller 130 and the EEPROM 150 as shown in FIG. 5B.

At time t3, since neither the timing controller 130 nor the host system 140 communicate with the EEPROM 150 in series, the serial clock SCL does not occur as shown in FIG. 5A.

As described above, in the present invention, the time t1 when the host system 140 performs serial communication with the EEPROM 150 and the host system 140 transmits image data RGB and timing signals to the timing controller 130. To output, the timing controller 130 serially communicates with the EEPROM 150 using an extra time (t2 time) existing between the times t3. As a result, the present invention can reduce costs by using one EEPROM.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

10: display panel 110: gate driver
120: data driver 130: timing controller
140: host system 150: EEPROM

Claims (8)

A host system for outputting image data and timing signals;
A timing controller receiving the image data and the timing signals from the host system and outputting timing control signals for controlling driving of a display panel; And
Drive information of a display device and option information for driving the display device, and serially communicate with the host system to output drive information of the display device to the host system, and serially communicate with the timing controller A memory device for outputting information to the timing controller,
The timing controller is in serial communication with the memory device between the time when the host system is in serial communication with the memory device and when the host system outputs the image data and the timing signals to the timing controller. Display. The method of claim 1,
And the timing controller and the host system each communicate bidirectionally with the memory device through a serial clock and serial data. The method of claim 2,
A serial clock line of the host system is connected with the memory device by switching of a first transistor, a serial data line of the host system is connected with the memory device by switching of a second transistor,
And the serial clock line of the timing controller is connected to the memory device by switching of a third transistor, and the serial data line of the timing controller is connected to the memory device by switching of a fourth transistor. The method of claim 3, wherein
The timing controller,
And switching on and off of the first to fourth transistors to control serial communication between the host system and the memory device and serial communication between the timing controller and the memory device. The method of claim 4, wherein
The serial communication control signal,
And at a high logic level when the host system is in serial communication with the memory device and at a low logic level when the timing controller is in serial communication with the memory device. The method of claim 5, wherein
The host system,
Serial communication with the memory device using a serial clock only when the first transistor is turned on in response to a high logic level of the serial communication control signal,
And serial communication using the serial data with the memory device only when the second transistor is turned on in response to a high logic level of the serial communication control signal. The method of claim 5, wherein
The timing controller,
Serial communication with the memory device using a serial clock only when the third transistor is turned on in response to a high logic level of the serial communication control signal,
And serially communicating with the memory device using serial data only when the fourth transistor is turned on in response to a high logic level of the serial communication control signal. Drive information of a display device and option information for driving the display device, and serially communicate with a host system to output drive information of the display device to the host system, and serially communicate with the timing controller to display the option information. Outputting to a timing controller;
Outputting image data and timing signals from the host system; And
Receiving the image data and the timing signals from the host system and outputting timing control signals for controlling driving of a display panel;
Wherein the timing controller is in serial communication with the memory device between the time when the host system is in serial communication and when the host system outputs the image data and the timing signals to the timing controller. Driving method.

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