KR20160018781A - 카메라 제어 인터페이스 확장 버스 - Google Patents

카메라 제어 인터페이스 확장 버스 Download PDF

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Publication number
KR20160018781A
KR20160018781A KR1020167000592A KR20167000592A KR20160018781A KR 20160018781 A KR20160018781 A KR 20160018781A KR 1020167000592 A KR1020167000592 A KR 1020167000592A KR 20167000592 A KR20167000592 A KR 20167000592A KR 20160018781 A KR20160018781 A KR 20160018781A
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KR
South Korea
Prior art keywords
symbols
serial bus
wire serial
sequence
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020167000592A
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English (en)
Korean (ko)
Inventor
쇼이치로 센고쿠
조지 앨런 와일리
조셉 청
Original Assignee
퀄컴 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 퀄컴 인코포레이티드 filed Critical 퀄컴 인코포레이티드
Publication of KR20160018781A publication Critical patent/KR20160018781A/ko
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Information Transfer Systems (AREA)
  • Dc Digital Transmission (AREA)
  • Multimedia (AREA)
KR1020167000592A 2013-06-12 2014-06-12 카메라 제어 인터페이스 확장 버스 Withdrawn KR20160018781A (ko)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US201361834151P 2013-06-12 2013-06-12
US61/834,151 2013-06-12
US201361836777P 2013-06-19 2013-06-19
US61/836,777 2013-06-19
US201361886002P 2013-10-02 2013-10-02
US61/886,002 2013-10-02
US14/302,359 2014-06-11
US14/302,359 US9639499B2 (en) 2013-06-12 2014-06-11 Camera control interface extension bus
PCT/US2014/042182 WO2014201289A1 (en) 2013-06-12 2014-06-12 Camera control interface extension bus

Publications (1)

Publication Number Publication Date
KR20160018781A true KR20160018781A (ko) 2016-02-17

Family

ID=52020259

Family Applications (2)

Application Number Title Priority Date Filing Date
KR1020167000592A Withdrawn KR20160018781A (ko) 2013-06-12 2014-06-12 카메라 제어 인터페이스 확장 버스
KR1020167000593A Active KR101790900B1 (ko) 2013-06-12 2014-06-12 카메라 제어 인터페이스 확장 버스

Family Applications After (1)

Application Number Title Priority Date Filing Date
KR1020167000593A Active KR101790900B1 (ko) 2013-06-12 2014-06-12 카메라 제어 인터페이스 확장 버스

Country Status (8)

Country Link
US (4) US9582457B2 (enExample)
EP (2) EP3008610B1 (enExample)
JP (2) JP2016528588A (enExample)
KR (2) KR20160018781A (enExample)
CN (2) CN105283862B (enExample)
CA (2) CA2911404A1 (enExample)
TW (1) TWI607318B (enExample)
WO (2) WO2014201293A1 (enExample)

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US10713199B2 (en) * 2017-06-27 2020-07-14 Qualcomm Incorporated High bandwidth soundwire master with multiple primary data lanes
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US12347508B2 (en) 2021-02-12 2025-07-01 Nvidia Corp. Error detection pin encoding scheme to avoid maximum transitions and further improve signal integrity on high speed graphic memory interfaces
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Also Published As

Publication number Publication date
EP3008609A1 (en) 2016-04-20
JP6257757B2 (ja) 2018-01-10
US9639499B2 (en) 2017-05-02
US20140372642A1 (en) 2014-12-18
EP3008610A1 (en) 2016-04-20
WO2014201289A1 (en) 2014-12-18
CA2911404A1 (en) 2014-12-18
US9552325B2 (en) 2017-01-24
EP3008610B1 (en) 2017-08-30
US20140372643A1 (en) 2014-12-18
TW201506634A (zh) 2015-02-16
EP3008609B1 (en) 2017-08-30
JP2016528589A (ja) 2016-09-15
TWI607318B (zh) 2017-12-01
CA2911401A1 (en) 2014-12-18
US9582457B2 (en) 2017-02-28
US9811499B2 (en) 2017-11-07
CN105283863A (zh) 2016-01-27
CN105283862A (zh) 2016-01-27
CN105283862B (zh) 2018-08-14
JP2016528588A (ja) 2016-09-15
KR101790900B1 (ko) 2017-10-26
WO2014201293A1 (en) 2014-12-18
US20170220518A1 (en) 2017-08-03
US20140372644A1 (en) 2014-12-18
KR20160019103A (ko) 2016-02-18

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Date Code Title Description
PA0105 International application

Patent event date: 20160108

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid