CN105283862B - 用于数据通信的方法和装置 - Google Patents

用于数据通信的方法和装置 Download PDF

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Publication number
CN105283862B
CN105283862B CN201480033472.5A CN201480033472A CN105283862B CN 105283862 B CN105283862 B CN 105283862B CN 201480033472 A CN201480033472 A CN 201480033472A CN 105283862 B CN105283862 B CN 105283862B
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CN
China
Prior art keywords
serial bus
symbols
wire serial
sequence
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201480033472.5A
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English (en)
Chinese (zh)
Other versions
CN105283862A (zh
Inventor
S·森戈库
G·A·威利
J·张
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
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Qualcomm Inc
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Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN105283862A publication Critical patent/CN105283862A/zh
Application granted granted Critical
Publication of CN105283862B publication Critical patent/CN105283862B/zh
Expired - Fee Related legal-status Critical Current
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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Information Transfer Systems (AREA)
  • Dc Digital Transmission (AREA)
  • Multimedia (AREA)
CN201480033472.5A 2013-06-12 2014-06-12 用于数据通信的方法和装置 Expired - Fee Related CN105283862B (zh)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US201361834151P 2013-06-12 2013-06-12
US61/834,151 2013-06-12
US201361836777P 2013-06-19 2013-06-19
US61/836,777 2013-06-19
US201361886002P 2013-10-02 2013-10-02
US61/886,002 2013-10-02
US14/302,359 2014-06-11
US14/302,359 US9639499B2 (en) 2013-06-12 2014-06-11 Camera control interface extension bus
PCT/US2014/042182 WO2014201289A1 (en) 2013-06-12 2014-06-12 Camera control interface extension bus

Publications (2)

Publication Number Publication Date
CN105283862A CN105283862A (zh) 2016-01-27
CN105283862B true CN105283862B (zh) 2018-08-14

Family

ID=52020259

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201480033581.7A Pending CN105283863A (zh) 2013-06-12 2014-06-12 相机控制接口扩展总线
CN201480033472.5A Expired - Fee Related CN105283862B (zh) 2013-06-12 2014-06-12 用于数据通信的方法和装置

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN201480033581.7A Pending CN105283863A (zh) 2013-06-12 2014-06-12 相机控制接口扩展总线

Country Status (8)

Country Link
US (4) US9639499B2 (enExample)
EP (2) EP3008610B1 (enExample)
JP (2) JP2016528588A (enExample)
KR (2) KR101790900B1 (enExample)
CN (2) CN105283863A (enExample)
CA (2) CA2911401A1 (enExample)
TW (1) TWI607318B (enExample)
WO (2) WO2014201293A1 (enExample)

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US20150100711A1 (en) * 2013-10-07 2015-04-09 Qualcomm Incorporated Low power camera control interface bus and devices
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US10139875B2 (en) 2014-02-20 2018-11-27 Qualcomm Incorporated Farewell reset and restart method for coexistence of legacy and next generation devices over a shared multi-mode bus
US9852104B2 (en) 2014-02-20 2017-12-26 Qualcomm Incorporated Coexistence of legacy and next generation devices over a shared multi-mode bus
US9710423B2 (en) * 2014-04-02 2017-07-18 Qualcomm Incorporated Methods to send extra information in-band on inter-integrated circuit (I2C) bus
US9734121B2 (en) 2014-04-28 2017-08-15 Qualcomm Incorporated Sensors global bus
US10417172B2 (en) 2014-04-28 2019-09-17 Qualcomm Incorporated Sensors global bus
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KR20170126904A (ko) * 2015-03-11 2017-11-20 퀄컴 인코포레이티드 공유 멀티 모드 버스 상에서 레거시 및 차세대 디바이스들의 공존을 위한 페어웰 리셋 및 재시작 방법
US9996483B2 (en) * 2015-04-10 2018-06-12 Qualcomm Incorporated N-base numbers to physical wire states symbols translation method
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US20170371830A1 (en) * 2016-06-28 2017-12-28 Qualcomm Incorporated Accelerated i3c master stop
US20180062887A1 (en) * 2016-08-24 2018-03-01 Qualcomm Incorporated Using full ternary transcoding in i3c high data rate mode
US10713199B2 (en) * 2017-06-27 2020-07-14 Qualcomm Incorporated High bandwidth soundwire master with multiple primary data lanes
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US10657094B2 (en) 2018-03-29 2020-05-19 Nvidia Corp. Relaxed 433 encoding to reduce coupling and power noise on PAM-4 data buses
US10599606B2 (en) 2018-03-29 2020-03-24 Nvidia Corp. 424 encoding schemes to reduce coupling and power noise on PAM-4 data buses
US10768228B2 (en) * 2018-04-05 2020-09-08 Nxp B.V. Communication circuitry integrity assessment
US10623200B2 (en) 2018-07-20 2020-04-14 Nvidia Corp. Bus-invert coding with restricted hamming distance for multi-byte interfaces
TWI741417B (zh) * 2019-11-28 2021-10-01 旺玖科技股份有限公司 積體電路匯流排即時偵測連接狀態的裝置及方法
WO2021117646A1 (ja) * 2019-12-12 2021-06-17 ソニーセミコンダクタソリューションズ株式会社 通信装置および通信システム
WO2022050599A1 (ko) * 2020-09-07 2022-03-10 삼성전자 주식회사 카메라의 신호 라인을 감소시킨 전자 장치
US12347508B2 (en) 2021-02-12 2025-07-01 Nvidia Corp. Error detection pin encoding scheme to avoid maximum transitions and further improve signal integrity on high speed graphic memory interfaces
US11366776B1 (en) * 2021-04-13 2022-06-21 Renesas Electronics America Inc. Network device configuration based on slave device type
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Also Published As

Publication number Publication date
EP3008610A1 (en) 2016-04-20
JP2016528588A (ja) 2016-09-15
US9811499B2 (en) 2017-11-07
KR20160018781A (ko) 2016-02-17
US20140372642A1 (en) 2014-12-18
JP6257757B2 (ja) 2018-01-10
EP3008609A1 (en) 2016-04-20
TWI607318B (zh) 2017-12-01
KR20160019103A (ko) 2016-02-18
CA2911404A1 (en) 2014-12-18
US9639499B2 (en) 2017-05-02
US9552325B2 (en) 2017-01-24
EP3008610B1 (en) 2017-08-30
KR101790900B1 (ko) 2017-10-26
JP2016528589A (ja) 2016-09-15
EP3008609B1 (en) 2017-08-30
US20140372644A1 (en) 2014-12-18
CN105283862A (zh) 2016-01-27
CN105283863A (zh) 2016-01-27
WO2014201293A1 (en) 2014-12-18
US20170220518A1 (en) 2017-08-03
CA2911401A1 (en) 2014-12-18
US9582457B2 (en) 2017-02-28
TW201506634A (zh) 2015-02-16
WO2014201289A1 (en) 2014-12-18
US20140372643A1 (en) 2014-12-18

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